CN102237145A - Clamp-in storage device and testing method thereof - Google Patents

Abstract

A clamped storage device and a test method thereof are provided. The clamped storage device comprises a control unit, a storage unit and a signal processing and measuring unit. The control unit outputs a plurality of signals including a mode selection signal and a set of control signals. The memory unit is controlled by the control unit to read data at a predetermined address, and the memory unit has a set of output terminals. The signal processing and measuring unit has a set of input terminals and a set of output terminals, wherein the input terminals are connected to the set of output terminals of the storage unit, the signal processing and measuring unit reads the data from the set of input terminals and determines whether to perform a predetermined processing on the data according to the mode selection signal. Thereafter, the data is output through the set of output terminals.

Description

Clamp-in storage device and testing method thereof

technical field

The invention relates to a clamp-in storage device, and in particular to a clamp-in storage device with multiple data output channels, which is beneficial to the testing process.

Background technique

In the design of a conventional clamp-on memory device, the time planning for writing and reading is usually different. The main reason is that when the storage device writes data, the driving capability of the data line will be much greater than the load of the bit line and the memory cell itself, so during writing, Data can be directly written into the storage memory unit through the data line and the bit line in a short time. However, during reading, after the memory device unit precharges the bit line and the data line, then the data of the storage memory cell will be sent to the bit line and the data line, and wait until the potential on the data line is established, and then use the sense amplifier device (sense amplifier) amplifies the weak voltage difference, and finally reads the internal value of the storage memory unit from the data bus. The reading process is tedious and cumbersome, so the reading time of the storage device is usually much longer than the writing time of the storage device.

As chip systems become more and more complex, the demand for memory capacity is also increasing. If the read time cannot be shortened, the test time of the clamp-in storage device will occupy most of the test time of the chip system, so how to effectively shorten the read time of the storage device to speed up the subsequent test and verification process, in Under the application conditions of increasing storage capacity, it is indeed necessary to exist.

In the verification method of traditional clamp-in storage devices, a data bus with a word width is usually used, and the control device accesses the content value of the storage device to determine whether the entire storage device is read and written normally. This method mainly needs to set a group of addresses for the storage device first, and then the control device reads back the data from the corresponding address of the storage device. time, which in turn causes additional testing costs, especially on systems with larger storage capacity, this approach is even more inapplicable.

Therefore, it is necessary to continue research and development on the authentication mechanism of the clamp-in storage device.

Contents of the invention

The present invention provides a clamp-on storage device that allows for faster measurement techniques, at least during the verification of results.

The invention provides a clamp-in storage device, which includes a control unit, a storage unit and a signal processing and measuring unit. The control unit outputs multiple signals, including a mode selection signal and a set of control signals. The storage unit is controlled by the control unit to read a data at a predetermined address, and the storage unit has a set of output terminals. The signal processing and measurement unit has a group of input terminals and a group of output terminals, wherein the input terminals are connected to the group of output terminals of the storage unit, the signal processing and measurement unit reads the data from the group of input terminals, and selects signals according to the mode , to determine whether to perform a predetermined process on the data. Thereafter, the data is output through the set of output endpoints.

The present invention provides a method for testing a storage device, which is used in the clamp-in storage device, including writing a test data from the control unit to the storage unit. Moreover, the start mode selection signal directly outputs the test data through the set of output terminals, and is transmitted to an output port through the signal processing and measuring unit.

The present invention proposes a testing method for a storage device, which is used in a clamp-in storage device, wherein the clamp-in storage device includes a storage unit, a plurality of output terminals and a signal processing unit, wherein in a normal operation mode , after the signal processing unit processes the data output by the storage unit, the data is output through an output port. The test method includes: writing a test data into the storage unit; and directly outputting the test data from the output port through an output path of the signal processing unit without signal processing.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a system rack of a clamp-in storage device according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a signal processing and measuring device according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a system rack of a clamp-in storage device according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of a circuit structure of a signal processing and measuring device according to another embodiment of the present invention.

[Description of main component symbols]

100, 150: Clamp-on storage device

102, 152: storage device

104, 154: Signal processing and measurement devices

106, 156: output device

108, 158: Control device

200: multiplexer

202: Signal processing device

204: bit selection device

210: direct output path

Detailed ways

In the design of the clamp-in storage device, the present invention uses a large number of existing I/O ports in the chip system as the read-back path of the storage device to achieve the effect of fast measurement. Some examples are given below to illustrate the present invention, but the present invention is not limited to the examples given. In addition, appropriate combinations of the above-mentioned embodiments can be made.

With the advancement of technology, the number of transistors that can be placed per unit area has been increasing, and the circuits that can be realized are becoming more and more complex. Therefore, more and more circuits are packaged into the chip for design, and the storage space requirements are getting higher and higher. bigger and bigger. Based on the above reasons, the design of the embedded memory system gradually replaces the design of a single-function chip (stand alone) and becomes the mainstream of future designs.

FIG. 1 is a schematic diagram of a system architecture of a clamp-in storage device according to an embodiment of the present invention. Referring to FIG. 1 , the system architecture of the clamp-in storage device 100 includes, for example, a control device 108 , a storage device 102 , a signal processing and measurement device 104 and an output device 106 in terms of general functions. The clamp-on storage device 100 can access the storage device 102 through the control device 108 in a normal data access operation mode. When the outside world intends to write data into the storage device 102 , the control device 108 obtains the location and data to be written from the data bus according to the input of the control signal, and then transmits the data to the storage device 102 for writing. When the outside world wants to read data from the storage device, the control device will obtain the position to be read through the data bus according to the input of the control signal and send it to the storage device 102, and finally read the data from the storage device 102.

The clamp-in storage device 100 is a chip system with a clamp-in storage device, which not only provides space for data storage, but also needs to be able to process data. If the signal processing device starts to calculate the data in the storage device, the control device 108 will read the previously stored data from the storage device 102, and then the signal processing and measurement device 104 will process it. When the signal processing and measurement device 104 is completed After the action, the processed information will be sent to the output device 106 to adjust the signal level and strength, and finally sent to the I/O port for output and connection with the outside world.

Before describing the technology of the present invention in more detail, several factors that must be considered when designing a storage device in a general conventional clamp-in storage system are described. Due to the limitation of chip area and package, usually the number of I/O ports cannot be too much. In addition, based on the consideration of the data read-back time during the detection process, the width of the data bus provided by the control device must be wide enough so that the times of addressing and reading will not be too frequent. Although increasing the width of the data bus can greatly shorten the test time, but in this way, the number of I/O ports must be increased, and the packaging cost and chip area will also increase relatively. Therefore, in the design of traditional storage devices , to determine the width of the data bus, the factors of test time and chip area must be considered at the same time.

The writing and reading times of the storage device 102 are usually very different, and the reading time is usually longer than the writing time of the storage device 102 . However, in the design of the clamp-in storage system, due to the evolution of technology, the clock of the system is getting faster and faster, and the amount of data that needs to be processed has also increased significantly. When the demand for storage device capacity is increasing, and the number of I/O ports is also increasing, in order to increase the test performance of the chip system, if the test plan of the storage device still considers the control device 108 to read data for verification , will definitely increase the testing time and cost of the whole chip system.

The invention proposes a design mechanism that can shorten the test time for the storage device in the clamp-in storage system. However, the invention is also not limited to the use of authentication data. In the present invention, the original path for reading the data of the storage device through the control device is changed to output by other I/O ports of the chip system, and the characteristic that the I/O ports of the general chip system are usually much larger than the width of the data bus of the storage device is used. In a better situation, when each location in the storage device has its corresponding I/O port available for output, under this arrangement, the storage device reads all the data in the same time as the traditional storage device. Take a position at the same time. In this way, the test time of the storage device can be greatly shortened.

In the present invention, for example, different designs are made in the signal processing and measuring device 104 so that the verification data can also be output through the same I/O port, DA[1]...DA[YZ] instead of output from the control device 108 . The data of the storage device 102 may, for example, be marked by X, Y, and Z to represent the address of the data bit. In this embodiment, the number of output terminals of the storage device 102 is, for example, DI[1], DI[2], .

In addition to the control device 108 having a data bus and a control bus to allow the outside to do general data access to the storage device 102 through the control device 108, the signal processing and measurement device 104 receives a readback mode control signal generated by the control device 108, and also It is the mode select signal to set the operating mode of the signal processing and measurement device 104 . The control device 108 generates control signals to respectively control the operations of the storage device 102 , the signal processing and measurement device 104 and the output device 106 , and the signal processing and measurement device 104 is further controlled by the control signal of the read mode.

FIG. 2 is a schematic circuit diagram of a signal processing and measuring device according to an embodiment of the present invention. Referring to FIG. 2, the signal processing and measuring device 104 can retain the readout mode of the general clamp-in storage system, and also provide another readout path of the storage device, which can be selected to output in normal mode or output in normal mode according to the signal in the readback mode. Output in measured mode.

As shown in FIG. 2 , in the signal processing and measuring device 104 , there is an output unit corresponding to each input terminal DI, which includes a multiplexer 200 , a signal processing device 202 , and a direct output path 210 . The input terminal DI of the signal processing and measuring device 104 is respectively connected to the output terminal DI of the storage device 102 . One input of the multiplexer 200 is connected to the input terminal DI via a direct output path 210 . The other input of the multiplexer 200 is connected to the input terminal DI via the signal processing device 202 . The signal processing device 202 processes the input data as required, such as converting digital signals into analog signals. The multiplexer 200 outputs the signal at one end to the output end DO according to the selection control of the readback mode.

For example, when the control signal of the readback mode is in a low state (Low), which represents a normal mode, the multiplexer 200 will select the signal processed by the signal processing device 202 and output the signal. And when the control signal of the readback mode is set to a high state (High), this represents that the signal processing and measurement device 104 is set to a measurement mode. At this time, the data of the storage device 102 passes through the direct output path 210, and is processed by the signal processing and measurement device. The output terminal DO of the device 104 is output.

Returning to the operation of the overall circuit in FIG. 2 , the output terminal DO of the signal processing and measurement device 104 is connected to an input terminal of an output device 106 . When the output device 106 receives the input signal, it adjusts the level and strength of the signal, and then sends it to the I/O output port DA. Please note here that the output device 106 is an optional component, which is used to adjust the signal level and intensity to meet the signal requirements required for subsequent driving. In some applications, the output device 106 is not a necessary component .

Through the arrangement shown in Fig. 1 and Fig. 2, a large number of I/O output ports can be utilized as output ports for data readback in verify operation mode. The complete verification data of the storage device 102 is quickly read out. Since the I/O output ports at this time are shared with the normal mode, the number of extra I/O ports will not be increased. In increasingly complex chip systems, memory capacity and I/O ports will continue to increase, and the method of this embodiment will be more suitable for this type of chip system.

In terms of the number of I/O ports considered, the design in Fig. 2 is only one of them. In the readback mode, based on the concept of directly outputting the verification data in the storage device through the I/O port, the read back verification data can be sorted out to use the output of the I/O port more efficiently end.

FIG. 3 is a schematic diagram of a system architecture of a clamp-in storage device according to another embodiment of the present invention. Referring to FIG. 3 , in another embodiment of the fast measurement, the clamp-in storage device 150 includes a control device 158 , a storage device 152 , a signal processing and measurement device 154 and an output device 156 . Compared with the embodiment in FIG. 1 , the difference is that the signal processing and measuring device 154 adds a set of bit selection signals. The control device 158 controls the signal processing and measurement device 154 in cooperation with an external bit selection signal. The function of the bit select signal is as follows. When the number of I/O ports is not enough to output all the bit data of a whole column in the storage device 102 at one time, the output control device can use the bit selection signal at this time, according to the mode of time-division multiplexing, in the same I/O On the port, make timely switching at different times to obtain the output of different verification bit data, and finally collect the data of all bits in a whole column. In this way, appropriate changes can be made to the signal processing and measurement device 154 .

FIG. 4 is a schematic diagram of a circuit structure of a signal processing and measuring device according to another embodiment of the present invention. Referring to FIG. 4 , the signal processing and measuring device 154 includes an input signal DI[1][Z:1] to an input signal DI[Y][Z:1], wherein Y represents the number of words, and Z represents the number of digits. Each output terminal DO[1] to DO[Y] is used to output a word of output signal, where a word has Z bits, and Z is 8 for example, but the value of Z is not limited to 8. For each output terminal, there is an output unit, including a multiplexer 200 , a bit selection device 204 , and a signal processing device 202 . The signal input terminal DI is received by the storage device 152 at a time and contains a digital word data containing Z bits, which are sent to the bit selection device 204 and the signal processing device 202 respectively, which are respectively connected to the two input terminals of the multiplexer, and read back The selection of the mode signal outputs one of the two output terminals DO, the number of which is reduced to Y in this embodiment.

Under normal operation, when the control signal of the readback mode is at a low state, the signal processing and measuring device 154 is programmed to be in a normal mode. After the input signals are respectively input with Z-bit data from the input terminal DI, after being calculated by the signal processing device 202, the signals are sent to the output signals respectively to the output terminal DO through the corresponding multiplexers 200 respectively. Here, since the input data is Z-bit digital data, the signal processing device 202 converts the Z-bit digital data into an analog single analog signal, for example. So in general operation, the SoC operates in the same way as the first embodiment of the signal processing and measurement device.

In addition, when the readback mode control signal is at a high state, the signal processing and measurement device 154 is configured to be in the measurement mode. At this time, the input signals DI[1][Z:1] to DI[Y][Z:1] will respectively pass through the bit selection device 204, and the bit data will be output in time and order by using the bit selection signal. The control method is, for example, using M control lines, where M=log ₂ Z, to sequentially time-division and send different bit data to the output end of the bit selection device 204 respectively. For example, the bit selection device 204 can determine which input bit data DI[1][Z:1] will be sent to the output terminal of DO[1] through the setting of the bit selection signal. Taking a word with 8 bits of data as an example, the input signal DI[1][8:1], the bit selection signal can select DI[1][1], DI[1][2].. Which bit of .DI[1][8] is output to the DO[1] location. After 8 data readbacks, a complete word data can be collected.

Through the switching control of the bit selection line, the bit selection device 204 with the sequence number 1 to the bit selection device 204 with the sequence number Y can pass the bit data directly through the multiplexer 1 to the multiplexer Y in sequence, and then respectively pass the signal It is directly sent to the output terminals DO[1] to DO[Y] without any signal processing. The method of time-division and multiplexing solves the problem that the number of I/O ports of the clamp-in storage device cannot output the entire column data of the storage device at one time, but the advantages of a large number of I/O ports of the system chip can still be used to speed up storage. The read-back action of the device further reduces the test time of the storage device.

Next, the output device 156 behind the signal processing and measuring device 154 performs signal processing required for subsequent operations, such as enhancing the voltage level of the signal.

It should be noted that when the system is in the data readback state of the verification mode, although the signal output by the I/O port is an analog signal, it corresponds to one bit of data, and there are only two states. Therefore, as long as the two states of the bit data can be distinguished, it can be determined by the subsequent sensing mechanism without affecting the function in normal operation. In other words, the clamp-in storage device 150 does not have to output through the output device 156 , but can be directly output by the signal processing and measuring device 154 for external data verification.

As far as the overall operation mechanism is concerned, the operation effects of the control device, storage device, signal processing and measurement device and output device of the clamp-in storage device can also be as follows, for example.

The control device is used to generate the control signal when the storage device accesses data, the control timing required by the signal processing and measurement device when accessing the output data of the storage device, and the control signal related to the output configuration of the output device.

The storage device determines which address of the storage device to access through the signal input by the control device. The read and write actions are mainly determined by the input signal of the control device. The corresponding address will be sent to the storage device and the data will be read out. When data is to be written into the storage device, the control device will send the address and data to be input to the storage device and write the data into the corresponding address. .

The signal processing and measuring device can receive the signal read by the storage device, and the operation mode of the circuit can be determined by the control signal of the readback mode. When the readback mode is in a low state, the signal processing and measuring device operates in the normal mode at this time, and the storage The data read out by the device will first be processed by the signal processing device, and then processed by the multiplexer, and then sent to the input terminal of the output device.

When the readback mode is in a high state, the signal processing and measuring device is operating in the measuring mode, and the data read from the storage device will be directly sent to the input terminal of the output device after passing through the multiplexer. This method mainly uses the characteristic that the I/O output port is much larger than the width of the data bus, and directly sends the data read from the storage device to the output device for output, and can read a large amount of data at one time without affecting the normal operation of the circuit. , and can speed up the test time of the storage device.

Output device: the input signal is provided by the output signal of the signal processing and measuring device, the output signal is the I/O output port, the output data from the signal processing and measuring device is strengthened through the output device, and finally sent to the I/O output port, used to enhance the circuit drive capability.

In addition, the storage device is not limited to a specific type of storage device. The I/O port of the present invention has dual functions, in addition to achieving normal operation of the storage device, it can also be used for other fast data measurement functions. When the data is verified, it does not need to undergo signal processing and is directly output from the I/O port. In the direct output method, according to the number of output terminals of the I/O port, the bit data can also be directly output in a multiplexed manner according to timing. Also, the selection of the output sequence can vary according to the actual design.

The present invention proposes a design for a clamp-in storage device. If it is applied to the rapid measurement technology, the read-back path of the storage device can be changed through the signal processing and measurement device, and the original data bus can be changed to one that is much larger than the width of the data bus. The I/O port to output. During the test, since multiple pieces of data can be read at one time, the test time can be shortened and the cost can be reduced.

In addition, the present invention uses the signal processing and measurement device to change the read-back path of the storage device, which can fully utilize the I/O port output of the system chip, and will not increase the number of extra pins.

In addition, the system chip of the present invention can quickly test and verify the storage device by using this method. If the verification is performed under the same test time, this method can execute more sets of test procedures, so the coverage of the test will be more complete. .

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection of the present invention The scope is to be determined as defined by the appended claims.

Claims (16)

1. A clamp-on storage device comprising: A control unit that outputs multiple signals, including a mode selection signal and a set of control signals; a storage unit controlled by the control unit to read a data at a predetermined address, the storage unit has a set of output terminals; and A signal processing and measurement unit has a set of input terminals and a set of output terminals, wherein the input terminal is connected to the set of output terminals of the storage unit, the signal processing and measurement unit reads the data from the set of input terminals, and according to The mode selection signal determines whether to perform a predetermined process on the data, and then outputs the data through the set of output terminals. 2. The clamp-on memory device as claimed in claim 1, wherein the number of the signal processing and the set of input terminals and the set of output terminals of the measurement unit are the same and correspond to each other. 3. The clamp-in memory device as claimed in claim 2, wherein the signal processing and measurement unit comprises: a plurality of signal processing devices, each corresponding to each output terminal of the set of output terminals, for receiving the data from the output terminal and performing the predetermined processing on the data; a plurality of multiplexers, each of the multiplexers corresponding to each output endpoint of the set of output endpoints, wherein each of the multiplexers includes: a first input end, used to directly receive the data input by the storage unit; and a second input terminal coupled to a signal processing device of the plurality of signal processing devices to receive the data after the predetermined processing; Wherein the multiplexer is controlled by the mode selection signal to output the data of the first input terminal or the second input terminal. 4. The clamp-on memory device as claimed in claim 3, wherein when the mode selection signal is activated, the plurality of multiplexers output the data at the first input end, otherwise output the data at the second input end. 5 . The clamp-in memory device as claimed in claim 1 , wherein the set of input terminals of the signal processing and measurement unit is a set of output terminals every fixed number, corresponding to an output of the set of output terminals. 6. The clamp-in memory device as claimed in claim 4, wherein the signal processing and measurement unit comprises: a plurality of output cells, one for each setting of the set of output endpoints, each of which includes: A multiplexer has a first input terminal, a second input terminal, and an output terminal, wherein the output terminal constitutes the set of output terminals, and the multiplexer is selected by the mode selection signal from the first input terminal or the The output of the second input terminal; A selection unit has an output terminal and a group input terminal, wherein the output terminal is connected to the first input terminal of the multiplexer, and the group input terminal is connected to the group of output terminals corresponding to the storage unit, through The one-bit selection signal generated by the control unit sequentially outputs the data of the group input terminal to the output terminal; and A signal processing unit has an output terminal and a group input terminal, wherein the group input terminal is connected to the group of output terminals corresponding to the storage unit, converted into a single analog signal and output from the output terminal. 7. The clamp memory device as claimed in claim 6, wherein the number of the group input terminals is the number of bits contained in one word data. 8 . The clamp memory device as claimed in claim 6 , wherein when the mode selection signal is enabled, the multiplexers output the data of the first input terminal, otherwise output the data of the second input terminal. 9. The clamp-in memory device according to claim 1, wherein the memory unit further comprises a set of data signal terminals connected to the control unit, and the control unit directly writes and reads data to the memory unit. 10. The clamp-in storage device according to claim 1, further comprising an output unit connected to the group of output terminals of the signal processing and measurement unit, controlled by one of the group of control signals, and after the signal is strengthened output. 11. The clamp memory device as claimed in claim 1, wherein the control unit is controlled by a readback mode control signal to activate the mode selection signal. 12. The clamp-on memory device of claim 1, wherein the mode selection signal is enabled in a test mode to control the signal processing and measurement unit. 13. A testing method for a storage device, used for the clamp-in storage device according to claim 1, comprising: writing a test data from the control unit to the storage unit; The mode selection signal is activated, the test data is directly output through the group of output terminals, and then transmitted to an output port through the signal processing and measuring unit. 14. The testing method of a storage device as claimed in claim 13, further comprising sensing a signal of the test data output by the signal processing and measuring unit to determine bit content. 15. A method for testing a storage device, used in a clamp-in storage device, wherein the clamp-in storage device includes a storage unit with a plurality of output terminals, and a signal processing unit, wherein in a normal operation mode Next, after the signal processing unit processes the data output by the storage unit, it is output from an output port. The test method includes: write a test data to the storage unit; and Through an output path of the signal processing unit, the test data is directly output from the output port without signal processing. 16. The testing method of a storage device as claimed in claim 15, further comprising sensing a signal of the test data output by the signal processing unit to determine bit content.

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