CN102222477B - Grid driving method, grid driving circuit and pixel structure - Google Patents
Grid driving method, grid driving circuit and pixel structure Download PDFInfo
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Abstract
The invention relates to a grid driving method, a grid driving circuit and a pixel structure. The grid driving method comprises the following steps of: loading first grid driving voltage on the grid of the pixel of which the data driving voltage is a positive-polarity signal, and loading second grid driving voltage on the grid of the pixel of which the data driving voltage is a negative-polarity signal, wherein the first grid driving voltage is higher than the second grid driving voltage. In the invention, different grid driving voltage is loaded on the grids of the pixels of the positive-polarity signal and the negative-polarity signal so as to meet charging requirements of the pixel electrodes of the positive-polarity signal and the negative-polarity signal; simultaneously, the lower second grid driving voltage is loaded on the grid of the pixel of the negative-polarity signal so as to effectively solve grid bias problem of a thin-film transistor (TFT) and prolong the service life of the TFT; compared with the prior art, the invention has the advantage that: the consumption power of loading the second grid driving voltage is low, so that the power consumption of a liquid crystal panel is reduced.
Description
Technical field
The present invention relates to lcd technology, relate in particular to a kind of grid drive method, gate driver circuit and dot structure.
Background technology
In at present traditional liquid crystal display, in order to prevent that liquid crystal is in for a long time under dc state and catabiosis occurs, the data drive voltage that data line offers pixel electrode is AC signal, when data drive voltage during higher than public electrode voltages, this data drive voltage is called positive signal, during lower than public electrode voltages, this data drive voltage is called the negative polarity signal when data drive voltage.
In traditional liquid crystal display, no matter take which kind of type of drive, thin film transistor (TFT) (Thin FilmTransistor, be called for short: when pixel TFT) is opened, no matter data drive voltage is positive signal or negative polarity signal, and the gate drive voltage that is carried in the TFT grid is all a high-voltage signal.If for a long time load higher gate drive voltage on the TFT of the pixel electrode of negative polarity signal, the serviceable life that can reduce TFT due to higher TFT grid bias, cause more early, faster, larger TFT skew; And, also increased unnecessary liquid crystal panel power consumption.
Summary of the invention
The invention provides a kind of grid drive method, gate driver circuit and dot structure, in order to realize promoting the serviceable life of TFT, the power consumption of saving liquid crystal panel.
The invention provides a kind of grid drive method, comprising:
Be to load the first grid driving voltage on the grid of pixel of positive signal in data drive voltage, be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, described first grid driving voltage is higher than described second grid driving voltage.
The invention provides a kind of gate driver circuit, comprise: loaded circuit, be used for loading the first grid driving voltage on data drive voltage is the grid of pixel of positive signal, and be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
Described first grid driving voltage is higher than described second grid driving voltage.
The invention provides a kind of dot structure, comprise one-row pixels at least, wherein also comprise: two signal lines that are used for driving described one-row pixels; Described two signal lines are respectively used to load first grid driving voltage and second grid driving voltage, and described first grid driving voltage is higher than described second grid driving voltage;
The pixel that it is positive signal that the signal line that wherein loads the first grid driving voltage is used for driving described one-row pixels data drive voltage; The pixel that it is the negative polarity signal that the signal line that loads the second grid driving voltage is used for driving described one-row pixels data drive voltage.
The present invention loads different gate drive voltages by the grid in positive signal and the pixel of negative polarity signal, satisfies the charging requirement of the pixel electrode of positive signal or negative polarity signal; Simultaneously, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
Description of drawings
Fig. 1 is the process flow diagram of grid drive method one embodiment of the present invention;
Fig. 2 is the structural representation of gate driver circuit embodiment two of the present invention;
Fig. 3 is the structural representation of gate driver circuit embodiment three of the present invention;
Fig. 4 is the structural representation of gate driver circuit embodiment four of the present invention;
Fig. 5 is the structural representation of dot structure embodiment one of the present invention;
Fig. 6 is the structural representation of dot structure embodiment two of the present invention.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is the process flow diagram of grid drive method one embodiment of the present invention.As shown in Figure 1, the present embodiment comprises following part:
101, on being the grid of pixel of positive signal, data drive voltage loads the first grid driving voltage;
102, on being the grid of pixel of negative polarity signal, data drive voltage loads the second grid driving voltage.
Wherein the first grid driving voltage is higher than the second grid driving voltage.
Find through research, under identical gate drive voltage, the required duration of charging of positive-negative polarity signal can be different, and the duration of charging of positive signal is greater than the negative polarity signal.The grid drive method that the present embodiment provides utilizes this achievement in research, it is the lower second grid driving voltage of on-load voltage on the grid of pixel of negative polarity signal in data drive voltage, compared with prior art the duration of charging of proper extension negative polarity signal pixels, do not need very high gate drive voltage just to be well positioned to meet the charging requirement of negative polarity signal pixels.
The grid drive method that the present embodiment provides can be applied to multiple type of drive, and the below is described respectively:
(1) be applied to the frame inversion driving mode
In the frame inversion driving mode, if it is positive signal that data line offers the data drive voltage of current frame pixel, to offer the data drive voltage of next frame pixel be the negative polarity signal to data line, that is to say, for each frame image signal, the data drive voltage that data line offers pixel is all positive signal or negative polarity signal, and for continuous some frame image signals, the data drive voltage that data line provides alternately is positive signal and negative polarity signal.
If the data drive voltage of current frame pixel is positive signal, load the first grid driving voltage on the grid of current frame pixel, so that the current frame pixel electrode charges fully; The data drive voltage of next frame pixel is the negative polarity signal, loads the second grid driving voltage on the grid of next frame pixel, so that the next frame pixel electrode charges fully.
In the frame inversion driving mode, by the high-low pressure conversion that above-mentioned gate drive voltage carries out with the frame counter-rotating, satisfy the charging requirement of the pixel electrode of positive signal or negative polarity signal; Simultaneously, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
(2) be applied to the line inversion driving mode
Being expert in inversion driving mode, for a certain frame image signal, is positive signal if data line offers the data drive voltage of the capable pixel of n, and to offer the data drive voltage of the capable pixel of n+1 be the negative polarity signal to data line; For the next frame of this frame image signal, the data drive voltage that data line offers the capable pixel of n is the negative polarity signal, and the data drive voltage that data line offers the capable pixel of n+1 is positive signal.
If the data drive voltage of certain delegation's pixel of a certain frame image signal is positive signal, load the first grid driving voltage on the grid of this delegation's pixel, so that this delegation's pixel electrode charges fully; The data drive voltage of next line pixel is the negative polarity signal, loads the second grid driving voltage on the grid of next line pixel, so that the next line pixel electrode charges fully.
Be expert in inversion driving mode, by above-mentioned gate drive voltage retinue and with the high-low pressure conversion that the frame counter-rotating is carried out, satisfy the charging requirement of the pixel electrode of positive signal or negative polarity signal; Simultaneously, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
(3) be applied to 1 point (Dot) interlacing inversion driving mode
In 1 interlacing inversion driving mode, for a certain frame image signal, if it is positive signal that data line offers the data drive voltage of the capable odd column pixel of n, to offer the data drive voltage of the capable even column pixel of n be the negative polarity signal to data line, the data drive voltage that data line offers the capable odd column pixel of n+1 is the negative polarity signal, and the data drive voltage that data line offers the capable even column pixel of n+1 is positive signal; Next frame for this frame image signal, the data drive voltage that data line offers the capable odd column pixel of n is the negative polarity signal, the data drive voltage that data line offers the capable even column pixel of n is positive signal, the data drive voltage that data line offers the capable odd column pixel of n+1 is positive signal, and the data drive voltage that data line offers the capable even column pixel of n+1 is the negative polarity signal.
Otherwise, for a certain frame image signal, if it is the negative polarity signal that data line offers the data drive voltage of the capable odd column pixel of n, to offer the data drive voltage of the capable even column pixel of n be positive signal to data line, the data drive voltage that data line offers the capable odd column pixel of n+1 is positive signal, and the data drive voltage that data line offers the capable even column pixel of n+1 is the negative polarity signal; Next frame for this frame image signal, the data drive voltage that data line offers the capable odd column pixel of n is positive signal, the data drive voltage that data line offers the capable even column pixel of n is the negative polarity signal, the data drive voltage that data line offers the capable odd column pixel of n+1 is the negative polarity signal, and the data drive voltage that data line offers the capable even column pixel of n+1 is positive signal.
If the data drive voltage of a certain row pixel of certain delegation of a certain frame image signal is positive signal, load the first grid driving voltage on the grid of this pixel, so that this pixel electrode charges fully; If the data drive voltage of a certain row pixel of certain delegation of a certain frame image signal is the negative polarity signal, load the second grid driving voltage on the grid of this pixel, so that this pixel electrode charges fully.
In 1 interlacing inversion driving mode, load different gate drive voltages by the grid in positive signal and the pixel of negative polarity signal, satisfy the charging requirement of the pixel electrode of positive signal or negative polarity signal; Simultaneously, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
(4) be applied to 2 point (Dot) interlacing inversion driving modes
In 2 interlacing inversion driving modes, if every delegation pixel is divided into a plurality of groups, each group comprises 2 adjacent pixels, for a certain frame image signal, if it is positive signal that data line offers the data drive voltage of the capable odd number group pixel of n, to offer the data drive voltage of the capable even number set pixel of n be the negative polarity signal to data line, the data drive voltage that data line offers the capable odd number group pixel of n+1 is the negative polarity signal, and the data drive voltage that data line offers the capable even number set pixel of n+1 is positive signal; Next frame for this frame image signal, the data drive voltage that data line offers the capable odd number group pixel of n is the negative polarity signal, the data drive voltage that data line offers the capable even number set pixel of n is positive signal, the data drive voltage that data line offers the capable odd number group pixel of n+1 is positive signal, and the data drive voltage that data line offers the capable even number set pixel of n+1 is the negative polarity signal.
Otherwise, for a certain frame image signal, if it is the negative polarity signal that data line offers the data drive voltage of the capable odd number group pixel of n, to offer the data drive voltage of the capable even number set pixel of n be positive signal to data line, the data drive voltage that data line offers the capable odd number group pixel of n+1 is positive signal, and the data drive voltage that data line offers the capable even number set pixel of n+1 is the negative polarity signal; Next frame for this frame image signal, the data drive voltage that data line offers the capable odd number group pixel of n is positive signal, the data drive voltage that data line offers the capable even number set pixel of n is the negative polarity signal, the data drive voltage that data line offers the capable odd number group pixel of n+1 is the negative polarity signal, and the data drive voltage that data line offers the capable even number set pixel of n+1 is positive signal.
If the data drive voltage of a certain group of pixel of certain delegation of a certain frame image signal is positive signal, load the first grid driving voltage on the grid of this group pixel, so that this pixel electrode charges fully; If the data drive voltage of a certain group of pixel of certain delegation of a certain frame image signal is the negative polarity signal, load the second grid driving voltage on the grid of this group pixel, so that this pixel electrode charges fully.
In 2 interlacing inversion driving modes, load different gate drive voltages by the grid in positive signal and the pixel of negative polarity signal, satisfy the charging requirement of the pixel electrode of positive signal or negative polarity signal; Simultaneously, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
With above-mentioned 2 interlacing inversion driving modes be similarly, the present embodiment also can be used for multiple spot (greater than 2 points) interlacing inversion driving mode, and wherein every delegation pixel is divided into a plurality of groups, and each group comprises pixel adjacent more than 3.
For above-mentioned various type of drive, the present invention also provides corresponding gate driver circuit, specifically describes as follows.
Gate driver circuit embodiment one of the present invention:
The gate driver circuit that the present embodiment provides comprises a loaded circuit, this loaded circuit is used for loading the first grid driving voltage on data drive voltage is the grid of pixel of positive signal, and be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, wherein the first grid driving voltage is higher than the second grid driving voltage.
The gate driver circuit that the present embodiment provides can be applied to above-mentioned 4 kinds of type of drive, by in data drive voltage being the lower second grid driving voltage of on-load voltage on the grid of pixel of negative polarity signal, effectively alleviate TFT grid bias problem, extended the serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
Gate driver circuit embodiment two of the present invention:
Fig. 2 is the structural representation of gate driver circuit embodiment two of the present invention.As shown in Figure 2, the present embodiment comprises: loaded circuit 1 and shift register 2, wherein, shift register 2 is connected with loaded circuit 1.
Loaded circuit 1 is used for loading the first grid driving voltage on data drive voltage is the grid of pixel of positive signal, and be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, the first grid driving voltage is higher than the second grid driving voltage, and first grid driving voltage and second grid driving voltage are that the 3rd gate drive voltage that loaded circuit 1 is exported according to shift register 2 obtains.
Particularly, shift register 2 is exported to loaded circuit 1 with the 3rd gate drive voltage, and loaded circuit 1 obtains respectively first grid driving voltage and second grid driving voltage according to the 3rd gate drive voltage, then is carried in respectively on the grid of respective pixel.
Above-mentioned shift register 2 can be for providing the parts of gate drive voltage for a frame image signal one-row pixels in existing display panels, loaded circuit 1 newly-increased in the present embodiment is connected between the grid of shift register 2 and pixel, process for the 3rd gate drive voltage that shift register 2 is provided and obtain first grid driving voltage and second grid driving voltage, then be carried on the grid of respective pixel.
Gate driver circuit embodiment three of the present invention:
Fig. 3 is the structural representation of gate driver circuit embodiment three of the present invention.Fig. 3 only shows the driving circuit of the capable pixel gates of n.As shown in Figure 3, the present embodiment specifically comprises: loaded circuit 10 and shift register 11, and wherein loaded circuit 10 comprises the first circuit 12 and second circuit 13, wherein the first circuit 12 is connected with second circuit and is connected with shift register 11 respectively.
The basic functional principle of above-mentioned shift register 11 is: when the output signal of the capable pixel gates driving circuit of n-1 shift register is high-voltage signal, flip-flop shift 11 output CLK1, when the output signal of the capable pixel gates driving circuit of n+1 shift register is high-voltage signal, flip-flop shift 11 output low-voltage signals.Particularly, when the grid of T1 received high-voltage signal, T1 opened, T1 outputs to high-voltage signal the grid of T3, and T3 opens, and T3 exports CLK1, when CLK1 was the cut-in voltage of the capable pixel of n, T3 was with the gate drive voltage output of this cut-in voltage as the capable pixel of n; When the grid of T2 and T4 received high-voltage signal, T2 and T4 opened, and T2 outputs to Vss the grid of T3, and T3 closes, and T4 exports Vss, made shift register 11 output low-voltage signals, also namely stopped exporting the gate drive voltage of the capable pixel of n.
See Fig. 3, the first circuit 12 1 ends connect the first clock signal clk 2, the first circuit 12 is used for when CLK2 is unblocked level, be to load the first grid driving voltage on the grid of pixel of positive signal in data drive voltage, to be the first circuit 12 obtain according to the 3rd gate drive voltage of shift register 11 outputs the first grid driving voltage.As a kind of better embodiment, the first circuit 12 can comprise a TFT switching device A1, breadth length ratio (the Width/Length of A1, be called for short: W/L) relatively large, it can be with the output of input signal near-complete, that is to say, when the input signal of A1 was the 3rd gate drive voltage, the first grid driving voltage of A1 output was close with the 3rd gate drive voltage or equate.Particularly, the grid of A1 connects the first clock signal clk 2, and the drain electrode of A1 connects shift register 11, specifically connects the drain electrode of T3, the source electrode output first grid driving voltage of A1.When the first clock signal clk 2 for data drive voltage is the cut-in voltage of the capable pixel of n of positive signal, A1 opens, A1 will with the grid of exporting to the capable pixel of this n that the 3rd gate drive voltage is close or first grid driving voltage that equate is complete of T3 output.
See Fig. 3, second circuit 13 1 ends connect second clock signal CLK3, second circuit 13 is used for when CLK3 is unblocked level, be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, to be second circuit 13 obtain according to the 3rd gate drive voltage of shift register 11 outputs the second grid driving voltage.As a kind of better embodiment, second circuit 13 can comprise the 2nd TFT switching device A2, the W/L less of A2, the W/L of A2 is less than A1, output after it can reduce higher applied signal voltage that is to say, when the input signal of A2 is the 3rd gate drive voltage, the second grid driving voltage of A2 output is less than the 3rd gate drive voltage, and the second grid driving voltage is also just less than the first grid driving voltage like this.Particularly, the grid of A2 connects second clock signal CLK3, and the drain electrode of A2 connects shift register 11, specifically connects the drain electrode of T3, the source electrode output first grid driving voltage of A2.When second clock signal CLK3 is data drive voltage when being the cut-in voltage of the capable pixel of n of negative polarity signal, A2 obtains the grid that the second grid driving voltage is exported to the capable pixel of this n after the 3rd gate drive voltage of T3 output is reduced.
In gate driver circuit provided by the invention, the first circuit and second circuit are not limited only to the switching device into TFT; other devices that can realize above-mentioned functions all belong to invention which is intended to be protected; for example the first circuit and second circuit can be the circuit of resistance formation; the resistance value of the first circuit can arrange very little; make the first grid driving voltage be slightly less than the 3rd gate drive voltage; the resistance value setting of second circuit is larger, makes the second grid driving voltage much smaller than the 3rd gate drive voltage.
Further, the present embodiment can also comprise the 7th TFT switching element T 7, the grid of T7 connects the output terminal of n+1 capable (being next line) pixel gates driving circuit shift register, and the drain electrode of T7 connects low-voltage signal Vss, and the source electrode of T7 connects respectively the source electrode of A1 and A2.When the grid of T7 received high-voltage signal, T7 opened, and T7 exports Vss, made A1 and A2 output low-voltage signal, also namely stopped exporting the gate drive voltage of the capable pixel of n.
The gate driver circuit that the present embodiment provides can be used for frame inversion driving mode and line inversion driving mode, the grid line of every delegation pixel of display panels all is connected with a gate driver circuit shown in Figure 3, and two output lines of gate driver circuit shown in Figure 3 all are connected on same grid line.Above-mentioned the first clock signal clk 2 and second clock signal CLK3 are along with counter-rotating alternately is unblocked level take at least one frame as unit, when being used for frame inversion driving mode and line inversion driving mode, the first clock signal clk 2 and second clock signal CLK3 alternately provide unblocked level with the counter-rotating of frame.
Gate driver circuit embodiment four of the present invention:
Fig. 4 is the structural representation of gate driver circuit embodiment four of the present invention.Fig. 4 only shows the driving circuit of the capable pixel gates of n.As shown in Figure 4, the present embodiment specifically comprises: loaded circuit 20 and shift register 11, wherein loaded circuit 20 comprises tertiary circuit 21, the 4th circuit 22, the 5th circuit 23 and the 6th circuit 24, and wherein tertiary circuit 21, the 4th circuit 22, the 5th circuit 23 and the 6th circuit 24 are connected with shift register 11 respectively.
Wherein the structure of shift register 11 and principle of work are identical with embodiment three, do not repeat them here.
See Fig. 4, one end of tertiary circuit 21 1 ends and the 4th circuit 22 all connects the 3rd clock signal clk 4, tertiary circuit 21 is used for when CLK4 is unblocked level, be to load the first grid driving voltage on the grid of pixel of positive signal in data drive voltage, to be tertiary circuit 21 obtain according to the 3rd gate drive voltage of shift register 11 outputs the first grid driving voltage; The 4th circuit 22 is used for when CLK4 is unblocked level, be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, to be the 4th circuit 22 obtain according to the 3rd gate drive voltage of shift register 11 outputs the second grid driving voltage.As a kind of better embodiment, tertiary circuit 21 comprises the 3rd TFT switching device A3, and the 4th circuit 22 comprises the 4th TFT switching device A4, and the W/L of A3 is greater than A4.The W/L of A3 is relatively large, it can be with the output of input signal near-complete, the W/L less of A4, output after it can reduce higher applied signal voltage, that is to say, when the input signal of A3 and A4 was the 3rd gate drive voltage, the first grid driving voltage of A3 output was close with the 3rd gate drive voltage or equate, the second grid driving voltage of A4 output is less than the 3rd gate drive voltage, and the second grid driving voltage is also just less than the first grid driving voltage like this.Particularly, A3 is connected grid and is connected the 3rd clock signal clk 4 with A4, and A3 is connected drain electrode and is connected shift register 11 with A4, specifically connect the drain electrode of T3, the source electrode output first grid driving voltage of A3, the source electrode output second grid driving voltage of A4.When the 3rd clock signal clk 4 is the cut-in voltage of the capable pixel of n frame n, A3 and A4 open, A3 will with the grid of exporting to the capable one part of pixel of n frame n that the 3rd gate drive voltage is close or first grid driving voltage that equate is complete of T3 output, the data drive voltage of this one part of pixel is positive signal, A4 reduces the rear grid that the second grid driving voltage is exported to the capable another part pixel of n frame n that obtains with the 3rd gate drive voltage of T3 output, and the data drive voltage of this another part pixel is the negative polarity signal.
See Fig. 4, one end of the 5th circuit 23 1 ends and the 6th circuit 24 all connects the 4th clock signal clk 5, the 5th circuit 23 is used for when CLK5 is unblocked level, be to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage, to be the 5th circuit 23 obtain according to the 3rd gate drive voltage of shift register 11 outputs the second grid driving voltage; The 6th circuit 24 is used for when CLK5 is unblocked level, be to load the first grid driving voltage on the grid of pixel of positive signal in data drive voltage, to be the 6th circuit 24 obtain according to the 3rd gate drive voltage of shift register 11 outputs the first grid driving voltage.As a kind of better embodiment, the 5th circuit 23 comprises the 5th TFT switching device A5, and the 6th circuit 24 comprises the 6th TFT switching device A6, and the W/L of A6 is greater than A5.The W/L less of A5, output after it can reduce higher applied signal voltage, the W/L of A6 is relatively large, it can be with the output of input signal near-complete, that is to say, when the input signal of A5 and A6 was the 3rd gate drive voltage, the second grid driving voltage of A5 output was less than the 3rd gate drive voltage, the first grid driving voltage of A6 output is close with the 3rd gate drive voltage or equate, the second grid driving voltage is also just less than the first grid driving voltage like this.Particularly, A5 is connected grid and is connected the 4th clock signal clk 5 with A6, and A5 is connected drain electrode and is connected shift register 11 with A6, specifically connect the drain electrode of T3, the source electrode output second grid driving voltage of A5, the source electrode output first grid driving voltage of A6.When the 4th clock signal clk 5 is the cut-in voltage of the capable pixel of n+1 frame n, A5 and A6 open, A5 reduces the rear grid that the second grid driving voltage is exported to the capable one part of pixel of n+1 frame n that obtains with the 3rd gate drive voltage of T3 output, the data drive voltage of this one part of pixel is the negative polarity signal, A6 will with the grid of exporting to the capable another part pixel of n+1 frame n that the 3rd gate drive voltage is close or first grid driving voltage that equate is complete of T3 output, the data drive voltage of this another part pixel is positive signal.
In gate driver circuit provided by the invention, tertiary circuit, the 4th circuit, the 5th circuit and the 6th circuit are not limited only to the switching device into TFT; other devices that can realize above-mentioned functions all belong to invention which is intended to be protected; for example they can be the circuit of resistance formation; the resistance value of tertiary circuit and the 6th circuit can arrange very little; make the first grid driving voltage be slightly less than the 3rd gate drive voltage; the resistance value setting of the 4th circuit and the 5th circuit is larger, makes the second grid driving voltage much smaller than the 3rd gate drive voltage.
In the present embodiment, the annexation of TFT switching element T 7 and working method are identical with embodiment three.
The gate driver circuit that the present embodiment provides can be used for 1 interlacing inversion driving mode and 2 interlacing inversion driving modes, the grid line of every delegation pixel of display panels all is connected with a gate driver circuit shown in Figure 4, and two output lines of gate driver circuit shown in Figure 4 are connected on different grid lines with delegation's pixel.Above-mentioned the 3rd clock signal clk 4 and the 4th clock signal clk 5 are along with counter-rotating alternately is unblocked level take at least one frame as unit, when being used for 1 interlacing inversion driving mode and 2 interlacing inversion driving modes, the 3rd clock signal clk 4 and the 4th clock signal clk 5 alternately provide unblocked level with the counter-rotating of frame.
For above-mentioned 1 interlacing inversion driving mode and 2 interlacing inversion driving modes, data drive voltage with one part of pixel in delegation's pixel is positive signal, the data drive voltage of another part pixel is the negative polarity signal, for these characteristics, the present invention also provides a kind of dot structure, comprise one-row pixels at least and be used for driving two signal lines of one-row pixels, two signal lines are respectively used to load first grid driving voltage and second grid driving voltage.It is the pixel of positive signal that the signal line that wherein loads the first grid driving voltage is used for driving the one-row pixels data drive voltage; It is the pixel of negative polarity signal that the signal line that loads the second grid driving voltage is used for driving the one-row pixels data drive voltage.The below introduces respectively corresponding dot structure in detail for different type of drive.
Dot structure embodiment one of the present invention:
Fig. 5 is the structural representation of dot structure embodiment one of the present invention.This dot structure is corresponding to 1 interlacing inversion driving mode, only show two row pixels in Fig. 5, for every delegation pixel, if it comprises a plurality of groups, each group comprises a pixel, article two, the signal line is respectively signal line 41 and signal line 42, and the data drive voltage that signal line 41 is used for the driving one-row pixels is the pixel 43 of positive signal, and the data drive voltage that signal line 42 is used for the driving one-row pixels is the pixel 44 of negative polarity signal.
For the first row pixel in Fig. 5, the data drive voltage of current time pixel 43 is positive signal (representing with "+" in figure), and what signal line 41 loaded is the first grid driving voltage; The data drive voltage of pixel 44 is negative polarity signal (representing with "-" in figure), and what signal line 42 loaded is the second grid driving voltage, and wherein the first grid driving voltage is higher than the second grid driving voltage.
The gate driver circuit that the dot structure of the present embodiment can adopt Fig. 4 to provide, particularly, the signal line 41 and 42 in two output lines difference connection layout 5 in Fig. 4.
The present embodiment drives one-row pixels with two signal lines, can load different gate drive voltages on the grid of positive signal and the pixel of negative polarity signal, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal particularly, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
Fig. 6 is the structural representation of dot structure embodiment two of the present invention.This dot structure is corresponding to 2 interlacing inversion driving modes, only show two row pixels in Fig. 6, for every delegation pixel, if it comprises a plurality of groups, each group comprises 2 adjacent pixels, article two, the signal line is respectively signal line 51 and signal line 52, and the data drive voltage that signal line 51 is used for the driving one-row pixels is the pixel 53 of positive signal, and the data drive voltage that signal line 52 is used for the driving one-row pixels is the pixel 54 of negative polarity signal.
For the first row pixel in Fig. 6, the data drive voltage of current time pixel 53 is positive signal (representing with "+" in figure), and what signal line 51 loaded is the first grid driving voltage; The data drive voltage of pixel 54 is negative polarity signal (representing with "-" in figure), and what signal line 52 loaded is the second grid driving voltage, and wherein the first grid driving voltage is higher than the second grid driving voltage.
A signal line in the present embodiment in two signal lines is used for driving the odd number group pixel of one-row pixels, and another signal line is used for driving the even number set pixel of one-row pixels.
The gate driver circuit that the dot structure of the present embodiment can adopt Fig. 4 to provide, particularly, the signal line 51 and 52 in two output lines difference connection layout 6 in Fig. 4.
The present embodiment drives one-row pixels with two signal lines, can load different gate drive voltages on the grid of positive signal and the pixel of negative polarity signal, the lower second grid driving voltage of on-load voltage on the grid of the pixel of negative polarity signal particularly, alleviation effectively TFT grid bias problem, extended serviceable life of TFT; Compared with prior art, the power that loading second grid driving voltage consumes is less, the power consumption of having saved liquid crystal panel.
The present invention can also be provided for the dot structure of multiple spot (greater than 2 points) interlacing inversion driving mode, and wherein every delegation pixel is divided into a plurality of groups, is with above-described embodiment difference, and each group comprises pixel adjacent more than 3.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be completed by the hardware that programmed instruction is correlated with, aforesaid program can be stored in a computer read/write memory medium, this program is when carrying out, execution comprises the step of said method embodiment, and aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (3)
1. gate driver circuit, it is characterized in that, comprise: loaded circuit is used for loading the first grid driving voltage on data drive voltage is the grid of pixel of positive signal, and is to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
Described first grid driving voltage is higher than described second grid driving voltage;
Described gate driver circuit also comprises: shift register, and described shift register is connected with described loaded circuit;
To be described loaded circuit obtain according to the 3rd gate drive voltage of described shift register output for described first grid driving voltage and described second grid driving voltage;
Described loaded circuit comprises:
The first circuit is used for when the first clock signal is unblocked level, is loading first grid driving voltage on the grid of pixel of positive signal in data drive voltage;
Second circuit is used for when the second clock signal is unblocked level, is loading second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
Described the first clock signal and described second clock signal are along with counter-rotating alternately is unblocked level take at least one frame as unit;
Described the first circuit comprises a TFT switching device, and described second circuit comprises the 2nd TFT switching device, and the breadth length ratio of a described TFT switching device is greater than described the 2nd TFT switching device;
The grid of a described TFT switching device connects described the first clock signal, and the drain electrode of a described TFT switching device connects shift register, the described first grid driving voltage of source electrode output of a described TFT switching device;
The grid of described the 2nd TFT switching device connects described second clock signal, and the drain electrode of described the 2nd TFT switching device connects shift register, the described second grid driving voltage of source electrode output of described the 2nd TFT switching device.
2. gate driver circuit according to claim 1, is characterized in that, described loaded circuit also comprises the 7th TFT switching device;
The grid of described the 7th TFT switching device connects the output terminal of the shift register of next line pixel, the drain electrode of described the 7th TFT switching device connects low-voltage signal, and the source electrode of described the 7th TFT switching device connects the source electrode of a described TFT switching device and the source electrode of described the 2nd TFT switching device.
3. gate driver circuit, it is characterized in that, comprise: loaded circuit is used for loading the first grid driving voltage on data drive voltage is the grid of pixel of positive signal, and is to load the second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
Described first grid driving voltage is higher than described second grid driving voltage;
Described gate driver circuit also comprises: shift register, and described shift register is connected with described loaded circuit;
To be described loaded circuit obtain according to the 3rd gate drive voltage of described shift register output for described first grid driving voltage and described second grid driving voltage;
Described loaded circuit comprises:
Tertiary circuit is used for when the 3rd clock signal is unblocked level, is loading first grid driving voltage on the grid of pixel of positive signal in data drive voltage;
The 4th circuit is used for when the 3rd clock signal is unblocked level, is loading second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
The 5th circuit is used for when the 4th clock signal is unblocked level, is loading second grid driving voltage on the grid of pixel of negative polarity signal in data drive voltage;
The 6th circuit is used for when the 4th clock signal is unblocked level, is loading first grid driving voltage on the grid of pixel of positive signal in data drive voltage;
Described the 3rd clock signal and described the 4th clock signal are along with counter-rotating alternately is unblocked level take at least one frame as unit;
Described tertiary circuit comprises the 3rd TFT switching device, described the 4th circuit comprises the 4th TFT switching device, described the 5th circuit comprises the 5th TFT switching device, described the 6th circuit comprises the 6th TFT switching device, the breadth length ratio of described the 3rd TFT switching device is greater than described the 4th TFT switching device, and the breadth length ratio of described the 6th TFT switching device is greater than described the 5th TFT switching device;
The grid of described the 3rd TFT switching device connects described the 3rd clock signal, and the drain electrode of described the 3rd TFT switching device connects shift register, the described first grid driving voltage of source electrode output of described the 3rd TFT switching device;
The grid of described the 4th TFT switching device connects described the 3rd clock signal, and the drain electrode of described the 4th TFT switching device connects shift register, the described second grid driving voltage of source electrode output of described the 4th TFT switching device;
The grid of described the 5th TFT switching device connects described the 4th clock signal, and the drain electrode of described the 5th TFT switching device connects shift register, the described second grid driving voltage of source electrode output of described the 5th TFT switching device;
The grid of described the 6th TFT switching device connects described the 4th clock signal, and the drain electrode of described the 6th TFT switching device connects shift register, the described first grid driving voltage of source electrode output of described the 6th TFT switching device.
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| CN103293731B (en) * | 2013-04-27 | 2017-06-23 | 深圳市金立通信设备有限公司 | It is a kind of to adjust the method and apparatus that display liquid crystal molecule overturns mode |
| CN105654919A (en) * | 2016-04-13 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display circuit and liquid crystal display driving method |
| CN106504717B (en) | 2016-12-27 | 2018-01-12 | 惠科股份有限公司 | Display device and driving method thereof |
| TWI613632B (en) * | 2017-02-20 | 2018-02-01 | 友達光電股份有限公司 | Gate driver |
| CN109584838A (en) * | 2019-01-30 | 2019-04-05 | 惠科股份有限公司 | Display panel driving method and display device |
| CN109671408A (en) * | 2019-01-30 | 2019-04-23 | 惠科股份有限公司 | Driving method, device and equipment of display panel and storage medium |
| CN109584837A (en) * | 2019-01-30 | 2019-04-05 | 惠科股份有限公司 | Display panel driving method and display device |
| CN109616072A (en) * | 2019-01-30 | 2019-04-12 | 惠科股份有限公司 | Display panel driving method and display device |
| CN110232887B (en) | 2019-06-04 | 2021-11-26 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN111276109A (en) * | 2020-03-27 | 2020-06-12 | Tcl华星光电技术有限公司 | Pixel charging method and display panel |
| CN111564132A (en) * | 2020-05-29 | 2020-08-21 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
| CN112731719A (en) * | 2020-12-31 | 2021-04-30 | 重庆惠科金渝光电科技有限公司 | Display panel, driving method thereof, and computer storage medium |
| CN113299249A (en) * | 2021-05-27 | 2021-08-24 | 惠科股份有限公司 | Liquid crystal display device and driving method thereof |
| CN113763818B (en) * | 2021-09-07 | 2023-06-02 | 武汉华星光电技术有限公司 | Display device |
| CN113936618A (en) * | 2021-10-27 | 2022-01-14 | 京东方科技集团股份有限公司 | Control method of liquid crystal display panel, liquid crystal display panel and electronic equipment |
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| CN1825414A (en) * | 2005-02-26 | 2006-08-30 | 三星电子株式会社 | Liquid crystal display and its driving method |
| CN101673582A (en) * | 2009-10-28 | 2010-03-17 | 友达光电股份有限公司 | Shift cache circuit |
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