CN102222032A - Device and method for fault injection of 1394 bus - Google Patents

Abstract

A 1394 bus fault injection device and method, belonging to the field of electronic testing, the invention solves the problem that the testing method in the prior art does not comprehensively consider various factors of the fault mode, so the accuracy of the evaluation result is poor. The logical storage input and output terminals of FPGA of the present invention are connected with the input and output terminals of EEPROM, the data buffer input and output terminals of FPGA are connected with the input and output terminals of SRAM, and the first 1394 chip input and output terminals of FPGA are connected with the first physical layer interface chip. The first input and output terminals are connected, the second input and output terminals of the first physical layer interface chip are the first 1394 bus interface, the second 1394 chip input and output terminals of the FPGA are connected with the first input and output terminals of the second physical layer interface chip, The second input and output end of the second physical layer interface chip is the second 1394 bus interface, and the FPGA is connected to the host machine through the RS232 serial bus.

Description

Fault injection device and method for 1394 bus

technical field

The invention relates to a fault injection device and method for a 1394 bus, belonging to the field of electronic testing.

Background technique

With the rapid development of electronic technology and the improvement of reliability requirements of electronic equipment, testability has become a new research point. The connotation of testability mainly includes two aspects of automatic test equipment (ATE) and built-in test (BIT). BIT refers to the ability to detect and isolate faults provided by the system or equipment. In order to evaluate whether BIT meets the requirements of testability design indicators, the ability of BIT must be verified, and fault injection technology is an effective means to verify BIT testability indicators. . Fault injection technology observes the ability of BIT to detect and isolate faults by artificially introducing faults, so as to verify whether the testability indicators of the system meet the design requirements, and make improvements to the system design according to the test results.

The predecessor of IEEE 1394 was a technology drafted by Apple Computer (Apple) in 1986. Apple called it FireWire (FireWire). In 1995, IEEE officially announced it as an industrial standard. The official name is high-performance serial bus. IEEE 1394-1995 standard. In 2000, the IEEE Association announced a revised version of the IEEE 1394-1995 standard——IEEE 1394a. The latest version is the IEEE 1394b standard launched in 2002.

However, the test methods in the prior art do not comprehensively consider various factors such as the integrity of the failure mode, the versatility of the injection, the effectiveness, and the practicability, so the accuracy of the evaluation results is poor.

Contents of the invention

The purpose of the present invention is to solve the problem that the test method in the prior art does not comprehensively consider the integrity of the failure mode, the versatility of the injection, the effectiveness, and the practicality, so the accuracy of the evaluation result is poor, and a 1394 test method is provided. Fault injection device and method for bus.

A kind of fault injection device of 1394 bus of the present invention, it comprises 1394 fault injectors and host machine, 1394 fault injectors comprise FPGA, the first physical layer interface chip, the second physical layer interface chip, SRAM and EEPROM,

The logic storage input and output terminals of the FPGA are connected to the input and output terminals of the EEPROM, the data buffer input and output terminals of the FPGA are connected to the input and output terminals of the SRAM, and the first 1394 chip input and output terminals of the FPGA are connected to the first physical layer interface chip. The output end is connected, the second input and output end of the first physical layer interface chip is the first 1394 bus interface, the second 1394 chip input and output end of the FPGA is connected with the first input and output end of the second physical layer interface chip, and the second physical layer interface chip The second input and output end of the layer interface chip is the second 1394 bus interface,

The FPGA is connected to the host machine through the RS232 serial bus.

The fault injection method based on the fault injection device of a kind of 1394 bus, the method may further comprise the steps:

Step 1. The host computer receives the user's input command, and sends the fault injection command and fault parameters to the fault injector;

The formation process of the fault injection command and fault parameters sent by the host to the fault injector is:

Step 11, the user interface module receives the fault injection command and parameters input by the user, and sends them to the parameter collection module;

Step 12, the parameter collection module sends the collected fault injection command and parameters to the fault injection module;

Step 13, the fault injection module identifies commands and parameters for fault injection, and converts them into data streams and transmits them to the communication module and the data analysis module respectively;

Step 14, the communication module sends the fault injection command and parameters to the 1394 fault injector through the RS232 serial bus to perform fault injection.

Step 2: The fault injector returns the data to the host to obtain the fault injection result.

The process of obtaining fault injection results is as follows:

Step 21, the communication module receives the feedback data of the 1394 fault injector, and sends it to the result recovery module;

Step 22, the data analysis module receives the feedback data sent by the result recovery module, and compares and analyzes it with the fault injection command and parameters sent by the fault injection module to verify the correctness of the fault injection and obtain the fault injection result.

Advantages of the present invention: the present invention is used for carrying out experimental verification to BIT, ATE etc. of IEEE 1394 bus. By artificially introducing faults into the IEEE 1394 bus, and observing and analyzing the behavior of the bus system when the fault is injected, it provides qualitative or quantitative evaluation results for test experiments, and the obtained evaluation results are accurate.

Description of drawings

Fig. 1 is the structural representation of the fault injection device of a kind of 1394 bus of the present invention;

Fig. 2 is the structural representation of FPGA;

Fig. 3 is a structural schematic diagram of the host computer;

Fig. 4 is the schematic diagram of the connection structure of FPGA and the first physical layer interface chip or the second physical layer interface chip;

Fig. 5 is the flow chart of the fault injection method of a kind of 1394 bus of the present invention;

Fig. 6 is a flow chart of the forming process of the fault injection command and the fault parameter sent by the host computer to the fault injector;

Fig. 7 is a flow chart of the process of acquiring fault injection results.

Detailed ways

Specific embodiment one: present embodiment is described below in conjunction with Fig. 1, the fault injection device of a kind of 1394 bus described in this embodiment, it comprises 1394 fault injectors and host computer 6, and 1394 fault injectors comprise FPGA1, the first physical layer Interface chip 2, second physical layer interface chip 3, SRAM4 and EEPROM5,

The logic storage input and output terminals of FPGA1 are connected with the input and output terminals of EEPROM5, the data buffer input and output terminals of FPGA1 are connected with the input and output terminals of SRAM4, and the first 1394 chip input and output terminals of FPGA1 are connected with the first physical layer interface chip 2. The input and output terminals are connected, the second input and output terminals of the first physical layer interface chip 2 are the first 1394 bus interface, the second 1394 chip input and output terminals of FPGA1 are connected with the first input and output terminals of the second physical layer interface chip 3, The second input and output end of the second physical layer interface chip 3 is the second 1394 bus interface,

The FPGA1 is connected to the host computer 6 through the RS232 serial bus.

The fault injection device for the IEEE1394 bus of the present invention is connected in series to the 1394 serial bus through two 1394 bus interfaces in actual use, and can receive data on the 1394 bus at the physical layer without injecting faults , caching and forwarding, so that the devices at both ends of the bus can complete normal bus communication. At the same time, different types of faults can be introduced into the bus. The basic types of faults on the bus include: physical faults and communication protocol faults. Physical faults are related to the electrical characteristics of the bus. IEEE 1394 uses differential transmission lines, and each port has a control module responsible for the mutual conversion between logical signals and physical twisted-pair signals (TPA and TPB). Electrical interference from the surrounding environment. Because of this, electrical failure modes that can occur on transmission lines include voltage instability between transmission lines or voltages that exceed ratings. At the same time, the inherent fault modes of the bus hardware include: signal open circuit, jump, constant 1 or 0. Communication protocol faults are related to the bus protocol, specifically including loss and damage of signal data packets, excessive transmission delay, buffer overflow, and so on. Comprehensively considering various factors such as the integrity of the failure mode, the versatility of injection, the effectiveness and practicability, the failures that can be injected by the present invention are communication protocol failures.

The present invention comprises two parts: the host computer 6 and the fault injector, the control software is installed in the host computer 6, the fault injector is the hardware for realizing injection, and the control software of the host computer 6 provides the user with a friendly human interaction interface, which can accept the user input (mouse, keyboard, etc.), and send fault injection commands and parameters to the fault injector to control the fault injection process. Fault injection commands include injection start, pause, and end; fault parameters include fault duration, fault interval time, fault type, fault injection time, etc. At the same time, the host-side control software also receives feedback from the fault injector to obtain fault injection results, bus system status and other relevant information and display them in the form of charts.

The fault injector is the core of the present invention, providing a fault injection mechanism. Under the control of the host computer, the injector can receive, buffer and forward data on the 1394 bus, and can also perform fault injection to cause data packets to be lost, damaged or delayed. The fault injector is divided into four parts from the hardware.

FPGA and its peripheral circuits. It mainly includes a large-capacity high-speed FPGA1 as the processing core, the logic of the FPGA1 is stored in a piece of EEPROM5, and is equipped with a large-capacity SRAM4 as a large amount of data buffer.

1394 interface chip. It mainly includes the first physical layer interface chip 2 and the second physical layer interface chip 3, which complete the conversion of digital signal/physical twisted pair signal, data transmission, monitoring of device connection and removal, speed signal, suspend and resume signal transmission etc.

Communications network. Define the data exchange interface between the fault injector and the host computer. Common methods include RS232, USB, and Ethernet. The RS232 method is used in the present invention.

Specific embodiment two: below in conjunction with Fig. 2 illustrate this embodiment, this embodiment is further described to embodiment one, FPGA1 comprises main control module 1-1, FPGA fault injection module 1-2, SRAM controller 1-3, the first PHY/LINK interface modules 1-4 and second PHY/LINK interface modules 1-5,

The first input and output terminals of the FPGA fault injection module 1-2 are connected to the main control module 1-1, and the main control module 1-1 is connected to the host computer 6 through the RS232 serial bus,

The second input and output of FPGA fault injection module 1-2 is connected with the first input and output of SRAM controller 1-3, and the second input and output of SRAM controller 1-3 is connected with SRAM4;

The third input and output end of the FPGA fault injection module 1-2 is connected to the first input and output end of the first PHY/LINK interface module 1-4, and the second input and output end of the first PHY/LINK interface module 1-4 is connected to the second input and output end of the first PHY/LINK interface module 1-4. A physical layer interface chip 2 is connected;

The fourth input and output end of the FPGA fault injection module 1-2 is connected with the first input and output end of the second PHY/LINK interface module 1-5, and the second input and output end of the second PHY/LINK interface module 1-5 is connected with the first input and output end of the second PHY/LINK interface module 1-5. The two physical layer interface chips 3 are connected.

PHY/LINK is the conversion of digital signal/physical twisted pair signal, bidirectional conversion.

1) Main control module 1-1: communicating with the control software in the host machine 6, receiving commands and parameters, so as to control the injection process and the recovery of the results.

2) FPGA fault injection module 1-2. Under the control of the main control module 1-1, the process of caching, forwarding and fault injection of 1394 bus data is performed. When no fault is injected, it accepts the input of the PHY/LINK interface module at one end, caches the data in SRAM4, and then fetches the data and transmits it to the PHY/LINK interface module at the other end. When a fault needs to be injected, the FPGA fault injection module 1-2 modifies the retrieved data, delays it, and then transmits it to the PHY/LINK interface module at the other end.

3) The first PHY/LINK interface module 1-4 and the second PHY/LINK interface module 1-5: controlled by the FPGA fault injection module 1-2, used to complete the link layer to the first physical layer interface chip 2 or The access of the second physical layer interface chip 3.

4) SRAM controllers 1-3. Controlled by the FPGA fault injection module 1-2, it is used to complete the read and write access to the external large-capacity SRAM4.

Specific Embodiment Three: The present embodiment will be described below in conjunction with FIG. 3 . This embodiment will further describe Embodiment 1. The host machine 6 includes a user interface module 6-1, a data analysis module 6-2, a parameter collection module 6-3, a fault Injection module 6-4, result recovery module 6-5 and communication module 6-6,

The communication end of the communication module 6-6 is connected with the 1394 fault injector through the RS232 serial bus, the fault command input end of the communication module 6-6 is connected with the first fault command output end of the fault injection module 6-4, and the communication module 6- The return data output terminal of 6 is connected with the input terminal of the result recovery module 6-5, the output terminal of the result recovery module 6-5 is connected with the first input terminal of the data analysis module 6-2, and the second input terminal of the fault injection module 6-4 The fault command output end is connected with the second input end of the data analysis module 6-2, the output end of the data analysis module 6-2 is connected with the data display input end of the user interface module 6-1, and the user interface module 6-1 receives user input For commands and parameters, the output end of the user interface module 6-1 is connected to the input end of the parameter collection module 6-3, and the output end of the parameter collection module 6-3 is connected to the input end of the fault injection module 6-4.

User interface module 6-1: Provides a friendly human interaction interface that can accept user input (mouse, keyboard, etc.), enabling users to perform operations such as fault type selection and parameter input; display fault injection results and bus status and other information.

Data analysis module 6-2: analyze the fault parameters set by the user, the injection results returned by the injector, the bus status and other information to verify the correctness of the fault injection. These information are further processed and sent to the user interface module 6-1 for display.

The parameter collection module 6-3: accepts user input from the user interface module 6-1, collects fault injection commands and parameters, and sends them to the fault injection module 6-4.

Fault injection module 6-4: identify the commands and data for fault injection and convert the corresponding parameters into data streams for transmission to the communication module 6-6 and data analysis module 6-2 to control the work of the injector.

Result recovery module 6-5: through the result recovery module 6-5, relevant information such as fault injection results and bus status are collected from the fault injector 6-4 and fed back to the data analysis module 6-1 for further processing.

Embodiment 4: This embodiment will be described below in conjunction with FIG. 4 . This embodiment will further describe Embodiment 1. Both the first physical layer interface chip 2 and the second physical layer interface chip 3 use TSB41AB3 chips.

The connection relationship between FPGA1 and the first physical layer interface chip 2 is the same as the connection relationship between FPGA1 and the second physical layer interface chip 3 , as shown in FIG. 4 .

The invention adopts IEEE 1394 physical layer interface chip TSB41AB3 to reduce the difficulty of FPGA logic design. TSB41AB3 is a physical layer chip that supports 3 cable interfaces. By multiplying the frequency of 24.576MHz crystal oscillator as a clock source, the maximum transmission rate can reach 400Mbps, and it supports standard PHY/LINK interface. The PHY/LINK interface mainly relies on CTL[1:0], D[7:0], LREQ, LPS, LINKON and SCLK signal lines to transmit control signals and various data packets between the physical layer and link layer modules. The main signals of the interface are defined as follows:

1) D[7:0]: bidirectional data line. The PHY/LINK interface supports three transmission speeds of 100Mbps, 200Mbps, and 400Mbps. According to the transmission speed, D[7:6], D[7:4], and D[7:0] are used respectively, and the unused data lines are set to 0.

2) CTL[1:0]: Bidirectional control line, used to determine the transmission direction of D[7:0].

3) LREQ: The link layer uses LREQ to send a string of bit streams to the physical layer to request access to the serial bus. The bit stream defines the type of request to be sent and the transmission speed of the data packet. According to the type of request, the length of the bit stream It ranges from 6 to 17 bits.

4) LPS: Indicates the working status of the link layer.

5) LINKON: Link open signal, which notifies the link layer to power on. The link layer automatically starts to output the LPS signal after detecting the LINKON signal.

Specific embodiment five: the present embodiment is described below in conjunction with Fig. 5, based on the fault injection method of the fault injection device of a kind of 1394 bus described in embodiment one, this method comprises the following steps:

Step 1, the host computer 6 receives the user's input command, and sends the fault injection command and fault parameters to the fault injector;

Step 2: The fault injector returns the data to the host machine 6 to obtain the fault injection result.

Embodiment 6: This embodiment will further explain Embodiment 5. The fault injection command in step 1 includes injection start, injection pause and injection end commands; fault parameters include fault duration, fault interval time, fault type and fault injection time.

Specific embodiment seven: the present embodiment is described below in conjunction with Fig. 6, and the embodiment five is further described in this embodiment, and the formation process of the fault injection command and the fault parameter sent by the host machine 6 to the fault injector is as follows:

Step 11, the user interface module 6-1 receives the fault injection command and parameters input by the user, and sends them to the parameter collection module 6-3;

Step 12, the parameter collection module 6-3 sends the collected fault injection command and parameters to the fault injection module 6-4;

Step 13, the fault injection module 6-4 recognizes the commands and parameters of the fault injection, and converts them into data streams and transmits them to the communication module 6-6 and the data analysis module 6-2 respectively;

Step 14, the communication module 6-6 sends the fault injection command and parameters to the 1394 fault injector through the RS232 serial bus to perform fault injection.

Embodiment 8: This embodiment will be described below in conjunction with FIG. 7 . This embodiment will further describe Embodiment 5. The process of obtaining the fault injection result in step 2 is as follows:

Step 21, the communication module 6-6 receives the feedback data of the 1394 fault injector, and sends it to the result recovery module 6-5;

Step 22, the data analysis module 6-2 receives the feedback data sent by the result recovery module 6-5, and compares and analyzes the command and parameters of the fault injection sent by the fault injection module 6-4 to verify the correctness of the fault injection, Get fault injection results.

Claims (8)

1. a kind of fault injection device of 1394 bus lines, it is characterized in that, it comprises 1394 fault injectors and host computer (6), and 1394 fault injectors comprise FPGA (1), the first physical layer interface chip (2), the second physical layer interface chip (3), SRAM (4) and EEPROM (5), The logic storage input and output terminals of FPGA (1) are connected with the input and output terminals of EEPROM (5), the data buffer input and output terminals of FPGA (1) are connected with the input and output terminals of SRAM (4), and the first 1394 The chip input and output end is connected with the first input and output end of the first physical layer interface chip (2), the second input and output end of the first physical layer interface chip (2) is the first 1394 bus interface, and the first 1394 bus interface of the FPGA (1) Two 1394 chip input and output terminals are connected with the first input and output terminals of the second physical layer interface chip (3), and the second input and output terminals of the second physical layer interface chip (3) are the second 1394 bus interface, The FPGA (1) is connected to the host computer (6) through the RS232 serial bus. 2. the fault injection device of a kind of 1394 bus according to claim 1, is characterized in that, FPGA (1) comprises main control module (1-1), FPGA fault injection module (1-2), SRAM controller ( 1-3), the first PHY/LINK interface module (1-4) and the second PHY/LINK interface module (1-5), The first input and output terminals of the FPGA fault injection module (1-2) are connected to the main control module (1-1), and the main control module (1-1) is connected to the host computer (6) through the RS232 serial bus, The second input-output end of the FPGA fault injection module (1-2) is connected with the first input-output end of the SRAM controller (1-3), and the second input-output end of the SRAM controller (1-3) is connected with the SRAM (4 ) connected; The third input and output end of the FPGA fault injection module (1-2) is connected with the first input and output end of the first PHY/LINK interface module (1-4), and the first input and output end of the first PHY/LINK interface module (1-4) The two input and output terminals are connected to the first physical layer interface chip (2); The fourth input and output end of the FPGA fault injection module (1-2) is connected with the first input and output end of the second PHY/LINK interface module (1-5), and the first input and output end of the second PHY/LINK interface module (1-5) The two input and output terminals are connected with the second physical layer interface chip (3). 3. the fault injection device of a kind of 1394 bus according to claim 1, is characterized in that, host computer (6) comprises user interface module (6-1), data analysis module (6-2), parameter collection module ( 6-3), fault injection module (6-4), result recovery module (6-5) and communication module (6-6), The communication end of the communication module (6-6) is connected with the 1394 fault injector through the RS232 serial bus, and the fault command input end of the communication module (6-6) is connected with the first fault command output end of the fault injection module (6-4) connected, the return data output end of the communication module (6-6) is connected with the input end of the result recovery module (6-5), and the output end of the result recovery module (6-5) is connected with the first output end of the data analysis module (6-2). One input terminal is connected, the second fault command output terminal of the fault injection module (6-4) is connected with the second input terminal of the data analysis module (6-2), and the output terminal of the data analysis module (6-2) is connected with the user interface The data display input of the module (6-1) is connected, the user interface module (6-1) receives user input commands and parameters, the output of the user interface module (6-1) is connected to the input of the parameter collection module (6-3) The output end of the parameter collection module (6-3) is connected with the input end of the fault injection module (6-4). 4. The fault injection device of a kind of 1394 bus according to claim 1, is characterized in that, the first physical layer interface chip (2) and the second physical layer interface chip (3) all select TSB41AB3 chip for use. 5. based on the fault injection method of the fault injection device of a kind of 1394 bus according to claim 1, it is characterized in that, the method comprises the following steps: Step 1, the host machine (6) receives the user's input command, and sends the fault injection command and fault parameters to the fault injector; Step 2, the fault injector returns the data to the host machine (6), and obtains the fault injection result. 6. The fault injection method of a kind of 1394 bus according to claim 5, it is characterized in that, the fault injection command in the step 1 comprises injection start, injection suspension and injection end order; Fault parameter comprises fault duration, fault interval time , fault type and fault injection time. 7. the fault injection method of a kind of 1394 bus according to claim 5, it is characterized in that, host machine (6) sends to the fault injection order of fault injector and the forming process of fault parameter is: Step 11, the user interface module (6-1) receives the fault injection command and parameters input by the user, and sends to the parameter collection module (6-3); Step 12, the parameter collection module (6-3) sends the collected fault injection command and parameters to the fault injection module (6-4); Step 13, the fault injection module (6-4) recognizes the command and parameters of fault injection, and converts it into a data stream and transmits it to the communication module (6-6) and the data analysis module (6-2) respectively; Step 14, the communication module (6-6) sends the fault injection command and parameters to the 1394 fault injector through the RS232 serial bus to perform fault injection. 8. the fault injection method of a kind of 1394 bus according to claim 5, is characterized in that, the acquisition process of the fault injection result in step 2 is: Step 21, communication module (6-6) receives the feedback data of 1394 fault injectors, and sends to result recovery module (6-5); Step 22, the data analysis module (6-2) receives the feedback data sent by the result recovery module (6-5), and compares and analyzes the command and parameters of the fault injection sent by the fault injection module (6-4) to verify Correctness of fault injection, get fault injection results.

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