CN102214637A - Circuit structure, semiconductor integrated circuit with circuit structure and design method of semiconductor integrated circuit - Google Patents
Circuit structure, semiconductor integrated circuit with circuit structure and design method of semiconductor integrated circuit Download PDFInfo
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- CN102214637A CN102214637A CN2010105705814A CN201010570581A CN102214637A CN 102214637 A CN102214637 A CN 102214637A CN 2010105705814 A CN2010105705814 A CN 2010105705814A CN 201010570581 A CN201010570581 A CN 201010570581A CN 102214637 A CN102214637 A CN 102214637A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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Abstract
The invention discloses a circuit structure, a semiconductor integrated circuit with the circuit structure and a design method of the semiconductor integrated circuit, which are used for improving the error range of the circuit manufacturing process of the semiconductor circuit around a circuit density transition region. The circuit structure of the invention comprises a semiconductor substrate and a material layer on the substrate. The material layer has a plurality of dense lines arranged closely adjacent to each other, isolated lines adjacent to the dense lines, and dummy (i.e., non-electrically functioning) shoulder-type barrier structures disposed in adjacent regions of the dense lines and the isolated lines. One end of the dummy shoulder barrier structure is connected to the drain line, and the other end extends outward along a direction substantially perpendicular to the drain line.
Description
Technical field
The invention relates to a kind of semiconductor integrated circuit technology, and particularly relevant for wire structures in a kind of integrated circuit and process thereof.
Background technology
Along with the development of semiconductor technology on fields such as material, design, technology, made each semiconductor subassembly from generation to generation become meticulousr and more complicated.
The wafer process technology of semiconductor circuit will comprise the geometrical pattern of a large amount of its access paths of transistor AND gate by a series of manufacturing process, be converted to and be arranged on various semiconductor material layers that pile up mutually, insulating barrier and conductive layer on the substrate.Interconnecting between the different stack layers can see through contact hole (contact hole) that stack layer offers or the lead among the through hole (via) and connect.Wherein, contact hole and through hole are formed in each material layer at lead place in similar vertical jack mode.
Yet along with transistorized assembly volume dwindles when reaching integrated circuit quicker and more high integration, the physical phenomenon between closely adjacent circuit unit produces desirable interconnection circuit performance impacts.With the conducting shell is example, and desirable metal line should possess the specific width through design, yet, there are many factors all may influence actual metal live width.For instance, the situation that some metal wire sections may shrink or expand because of the photolithography proximity effect (optical proximity effect) in the photoetching process, or the part metals line segment may have different surface topology difference because of different line density in the zones of different, for example, in chemico-mechanical polishing (chemical mechanical polishing, CMP) the load inequality that is caused in technology or the etch process.Photolithography proximity effect in the photoetching process makes and estrangedly has certain live width deviation with different circuit closely between distributing.Technologic bottleneck has also limited to effective dimension limit (critical dimension) on the wafer.Under the part situation, the actual printing width of comparatively estranged circuit can be much larger than the width of the equal circuit in dense zone, even if under identical width design, the live width deviation may cause membrane stress to a certain degree to estranged transitional region (being called the interval line estuary in line marine outfall again) intensive, and then produce the defective in metal hole and so on, for example copper cash space (copper line voids).Under opposite extreme situations comparatively, metallic circuit even can perk or fracture.Now, integrated circuit manufacturer adopts many different strategies to comprise optical near-correction (optical proximity correction, OPC) model and complicated design rule, control to obtain preferable dimension limit, only how pipe so avoids the stress defective to remain a very thorny problem on the metal wire sections of transitional region (marine outfall line).In addition, although above-mentioned paragraph is mainly described the problem of metal line, marine outfall uniaxial stress problem also is prevalent on the technology of macromolecular material, dielectric material, semiconductor and other material.
So, be necessary to develop effectively and be convenient to the real technological means of doing in fact, to reduce intensive linear stress in the ic manufacturing process to estranged transitional region.
Summary of the invention
The object of the present invention is to provide a kind of line construction, semiconductor integrated circuit and line construction method for designing.
A category of the present invention is to provide a kind of line construction that is used for semiconductor integrated circuit.According to one embodiment of the invention, this line construction is in the layer structure that is formed on the substrate, and the line construction in the present embodiment comprises several first kind lines (intensive line), the second class line (estranged line) and several the 3rd class lines.Wherein the 3rd class line is arranged at the outer peripheral areas of the first kind line and the second class line, and these the 3rd class lines are connected to the second class line respectively, and extends toward the direction vertical with the second class line haply.
According to another embodiment of the present invention, it discloses a kind of semiconductor integrated circuit and comprises substrate, is formed at the insulating barrier on the substrate and is arranged on the insulating barrier and the conductive line construction of tool.Has a connecting circuit (for example contact hole or through hole) in the insulating barrier.Line construction comprises several intensive lines, estranged line and conduction shoulder type barrier line.These intensive lines have tight arrangement style and are connected to connecting circuit in the insulating barrier.Estranged line is provided with contiguous intensive line, and estranged line also is connected to the connecting circuit in the insulating barrier.Conduction shoulder type barrier line is provided with contiguous intensive line and estranged line, and the shoulder type barrier line of wherein conducting electricity is connected to estranged line, and vertical with the direction of estranged line haply.In addition, conduction shoulder type barrier line directly do not link to each other (for example contact hole or through hole) with connecting circuit in the insulating barrier.Conduction shoulder type barrier line is as a kind of protection structure in the Wiring technique, and the shoulder type barrier line of therefore conducting electricity does not need to be electrically connected to the connecting circuit in the insulating barrier, this insulating barrier in the present embodiment may be arranged at conductor layer above or below.Yet this conduction shoulder type barrier line can be connected to the false through hole in the adjacent insulating barrier.Tool is not functional usually for false through hole itself herein, only for the convenience on making or technologic improvement and be provided with.
Another category of the present invention is to provide a kind of method for designing of line construction, is used for semiconductor integrated circuit.According to another embodiment of the present invention, this method for designing comprises: distinguish the interval, marine outfall of looking contiguous estranged line and several intensive lines; And, add shoulder type barrier line to above-mentioned interval, marine outfall, wherein shoulder type barrier line is connected with estranged line and is roughly vertical with estranged line.Distinguish that the action of looking the interval, marine outfall can further comprise the following step: (1) is distinguished and is looked several intensive lines, and these intensive lines satisfy predetermined line width limit respectively; (2) distinguish several spaces of looking intensive between the line; (3) be a block with above-mentioned space group; (4) several borders of definition block are as the interval, marine outfall; (5) draw first square frame with preliminary dimension, wherein first square frame utilizes the interval and estranged line in marine outfall several edges as first square frame; And (6) draw second square frame with the part of first square frame, and wherein second square frame utilizes estranged line to keep certain preset distance as one of them edge of second square frame and with above-mentioned intensive line.
The present invention can reduce intensive linear stress to estranged transitional region in the ic manufacturing process.
Can be further understood by following detailed Description Of The Invention and appended accompanying drawing about further embodiment of the present invention and spirit.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended the description of the drawings is as follows:
Fig. 1 is a kind of top view of line construction;
Fig. 2 shows the sweep electron microscope striograph occur in the metal hole defective among the copper cash;
Fig. 3 is the top view that a kind of line construction is provided with the empty interposed structure of protection usefulness around it;
Fig. 4 illustrates according to the present invention a kind of top view that is positioned at transition region and has the line construction of exemplary false conduction shoulder type barrier line among the part embodiment;
Fig. 5 A illustrates a kind of known line characteristics, has the top view of the empty interposed structure design of first kind of protection usefulness; It has false conduction shoulder type barrier line and Fig. 5 B illustrates a kind of line construction, is the top view according to the false structural design of second kind of protection usefulness;
Fig. 6 illustrates the top view according to the line construction that has exemplary shoulder type obstruct in another embodiment of the present invention;
Fig. 7 A illustrates according to the present invention the top view of the line construction that has metal shoulder type barrier line among the part embodiment, and Fig. 7 B is illustrated in the sweep electron microscope striograph with metallic circuit structure under the protection mechanism situation;
Fig. 8 A illustrates according to the present invention the top view of the line construction that has metal shoulder type barrier line among the part embodiment, and Fig. 8 B is illustrated in the sweep electron microscope striograph with metallic circuit structure under the protection mechanism situation;
Fig. 9 A illustrates according to the present invention the top view of the line construction that has metal shoulder type barrier line among the part embodiment, and Fig. 9 B is illustrated in the sweep electron microscope striograph with metallic circuit structure under the protection mechanism situation.
Figure 10 A illustrates according to the present invention the top view of the line construction that has metal shoulder type barrier line among the part embodiment, and Figure 10 B is illustrated in the sweep electron microscope striograph with metallic circuit structure under the protection mechanism situation;
Figure 11 illustrates the top view according to the false conduction shoulder of a kind of L font type barrier line among other interchangeable embodiment of the present invention;
Figure 12 A illustrates according among the part embodiment of the present invention to Figure 12 D, and the schematic flow sheet of step method one by one of false conduction shoulder type barrier line structure is set in Wiring technique.
[primary clustering symbol description]
100: line construction 101: intensive line
102: estranged line 103a: intensive to estranged transitional region
103b: intensive to estranged transitional region 300: line construction
301: intensive line 302: estranged line
305a: void is put feature structure 305b: void is put feature structure
400: line construction 401: intensive line
402: estranged line 410a: conduction shoulder type barrier line
410b: conduction shoulder type barrier line 410c: conduction shoulder type barrier line
410d: conduction shoulder type barrier line 500: line construction
501a: intensive line 501b: intensive line
501c: intensive line 502: estranged line
505a: void is put feature structure 505b: void is put feature structure
550: line construction 551a: intensive line
551b: intensive line 551c: intensive line
552: estranged line 553a: conduction shoulder type barrier line
553b: conduction shoulder type barrier line 553c: conduction shoulder type barrier line
554: line segment position 600: line construction
601a: intensive line 601b: intensive line
602a: estranged line 602b: estranged line
603: detach segment 610a: conduction shoulder type barrier line
610b: conduction shoulder type barrier line 610c: conduction shoulder type barrier line
700: line construction 701a: intensive line
701b: intensive line 701c: intensive line
702a: estranged line 702b: estranged line
710a: conduction shoulder type barrier line 710b: conduction shoulder type barrier line
710c: conduction shoulder type barrier line 710d: conduction shoulder type barrier line
800: line construction 801a: intensive line segment
801b: intensive line segment 801c: intensive line segment
801d: intensive line segment 801e: intensive line segment
802a: estranged line segment 802b: estranged line section
802c: estranged line section 810a: conduction shoulder type barrier line
810b: conduction shoulder type barrier line 810c: conduction shoulder type barrier line
810d: conduction shoulder type barrier line 810e: conduction shoulder type barrier line
810f: conduction shoulder type barrier line 900: line construction
901a: intensive line 901b: intensive line
901c: intensive line 902: estranged line segment
910a: conduction shoulder type barrier line 910b: conduction shoulder type barrier line
903: line segment position 1000: line construction
1001a: intensive line 1001b: contact mat
1001c: intensive line 1002: estranged line
1005: conduction shoulder type barrier line 1100: line construction
1101a: intensive line 1101b: intensive line
1101c: intensive line 1102a: estranged line segment
1102b: estranged line segment 1110a: conduction shoulder type barrier line
1110b: conduction shoulder type barrier line 1110c: conduction shoulder type barrier line
1231: space 1232: circuit
1233: space 1251: square frame
1252: square frame 1253: square frame
1254: square frame 1281: conduction shoulder type barrier line
1282: conduction shoulder type barrier line 1284: conduction shoulder type barrier line
Embodiment
The invention relates to wire structures and technology method thereof in a kind of semiconductor integrated circuit.What need special instruction is to disclose several different embodiments or embodiment in the following passage content, to realize various function of the present invention.Following specific assembly is routine or arrangement is set only for the convenience on illustrating, not in order to limit the scope of the invention.In addition, may repeat to mention part numeral or words in for example a plurality of in this exposure file, one to repeat be in order to separate say simple and brief for this, but not have any particular kind of relationship for example and/or between the configuration mode in order to a plurality of in pointing out to narrate.In addition, mention a feature when this exposure file and be formed on another feature, two features are connected and/or two features when coupling mutually, two features can be direct contact in some embodiments, two features also may be intervened mutually in other execution mode, then two features also can be not directly contact, and the present invention is not as limit.
In addition, for the space words, for example " low ", " on ", " laterally ", " vertically ", " more than ", " following ", " rising ", " decline ", " top ", " end " etc. with and derivative speech (as " laterally ", " downwards ", " making progress " etc.) be the relativeness that is used for describing between an assembly in the device that is illustrated in the invention accompanying drawing or feature and other assembly or the feature in this exposure file.Must explanation be, the space words should contain device different manipulate direction.For example, after device was reversed, a certain assembly was lower than another assembly by appearance or is positioned at the describing method of its below, and should correspond to a certain assembly is the top that is positioned at another assembly.That is to say that going up or inferior situation of absolute position may be contained in the below of relative position.In addition, device also can be rotated a special angle (for example 90 degree), and the space words also can be contained corresponding explanation.That is to say, but various explanations are done in the different whole orientation of space words adapting device itself, specially do not refer to specific absolute direction.
Can be further understood by following detailed Description Of The Invention and appended accompanying drawing about various embodiments of the present invention.
In the middle of the explanation of following embodiment, will illustrate as an example, yet the present invention is not limited to the particular conductivity wire rod with lead.Lead herein can comprise metal wire (for example copper, tungsten, aluminium, platinum wire rod or other various alloy wires).In addition, lead also can comprise non-metallurgy (non-metallurgical) line (for example semiconductor wire rod).
In the conductive layer of integrated circuit, in general good technology should possess to produce and meet dimension limit (critical dimension, CD) ability of the metal wire of specification is although may there be very big difference in its line route density of the adjacent domain at metal wire place.Seeing also Fig. 1, is the illustrated embodiment of simple transition curve line structure 100 among Fig. 1, and Fig. 1 illustrates the parallel line Structure Conversion and arrives the independently vertical view of uniline.In this example, the line that many parallel line structures form among Fig. 1 bunch promptly is regarded as intensive line 101, and independently uniline promptly is regarded as estranged line 102.In practical application, uniline (estranged line 102) often comes for the wherein extension in several intensive lines 101 of adjacent domain.Line bunch the intensive of (line cluster) top that forms at intensive line 101 is commonly called interval, line marine outfall (line estuary) to the intensive of estranged transitional region 103a and line bunch below to estranged transitional region 103b.
The bottleneck place of technology is being represented in interval, line marine outfall (line estuary) usually.The restriction that is brought on the various different process (as little shadow, etching, polishing, material, thin film deposition, surface topology) makes that the live width control in zone, line marine outfall is very difficult.For instance, the actual printing width of estranged metallic circuit can be much larger than the width of the equal circuit in dense zone, even if under identical width design.The live width deviation may cause membrane stress to a certain degree to estranged transitional region (being interval, line marine outfall) intensive, and then produces the defective in metal hole and so on, for example thin film void (film voids).Under opposite extreme situations comparatively, metallic circuit even can perk or fracture.Fig. 2 occurs in the actual illustration of the metal hole defective among the intensive copper cash for one scan formula electron microscope image show.
In the photolithographic exposure process, (optical proximity correction, OPC) model improves the consistency of line style printing, but limited to the improved effect of intensive line thickness variation on estranged transitional region generally to adopt optical near-correction.The advanced technologies design rule is mainly to add void to put feature structure (dummy feature) around wire structures in circuit layout.Fig. 3 illustrates the top view of the line construction 300 between a kind of transition region, and its line construction 300 has void and puts feature structure 305a, and 305b is arranged at around intensive line 301 (line bunch) and the estranged line 302.Yet even if void is put the position (for example only minimum technology spacing) at interval that feature structure is arranged on the most approaching above-mentioned intensive and estranged line, void is put feature structure and still is proved and is not enough to effectively relax intensive uniaxial stress on estranged transitional region.In addition, void is set on hand puts feature structure and also have some shortcomings, for example: (1) void is put feature structure and may be disturbed the electrical characteristic of circuit and the resistance-capacitance value that presets; And/or (2) void close space length demand of putting characteristic pattern has limited the tolerance of technology.
What proposed in this exposure file falsely (is and does not have an electrical characteristic, or mean do not possess the purpose of design when layer circuit such as telecommunication or electric energy transmitting function) shoulder type barrier structure can alleviate the uniaxial stress in density transition interval, and must not reduce the tolerance of technology.For instance, Fig. 4 illustrates according to the present invention a kind of top view that is positioned at transition region and has the line construction 400 of exemplary shoulder type barrier line among the part embodiment.As shown in Figure 4, four groups of false conduction shoulder type barrier line 410a, 410b, 410c and 410d are set at the transitional region (being the interval, marine outfall) of 402 on line bunch (line cluster) that intensive line 401 forms and estranged line.The false conduction shoulder type barrier line 410a of these protection usefulness, 410b, 410c and 410d are connected to an end of estranged line 402, and are extended by estranged line 402 past directions with estranged line 402 approximate vertical.Yet conduction shoulder type barrier line of the present invention must be not vertical with estranged line, as long as conduction shoulder type barrier line is not directly connected to intensive line or near other structure of intensive line, to avoid causing unnecessary mistake.The length of each conduction shoulder type barrier line need be enough to protect the interval, marine outfall, and the overall dimensions of conduction shoulder type barrier line can be followed the basic size or the spacing of general layer structure in the standard technology, to avoid causing technologic difficulty or extra manufacturing cost.Above-mentioned false conduction shoulder type barrier line does not have actual electric function, so do not need to be electrically connected to the connecting circuit (as electrical contact hole or through hole etc.) in other layer, yet for technologic convenience, false conduction shoulder type barrier line also can be connected on the false connecting circuit in other layer.In one of them embodiment, the length of conduction shoulder type barrier line is more than a times of length in the folded therebetween space of above-mentioned intensive line 401.
Fig. 5 A illustrates a kind of line construction 500, and its stage casing comprises intensive line 501a, 501b, 501c and estranged line 502 its extension dense-in-itself set line 501c.Void is put feature unit 505a, and 505b is arranged at around above-mentioned intensive line and the estranged line.Above-mentioned void is put feature structure 505a, and each self-contained a plurality of independently void of 505b are put feature unit, its often be designed near or equal the critical dimension size of relevant layers.
Fig. 5 B illustrates a kind of line construction 550; it is similar to the line construction 500 among Fig. 5 A; the stage casing of line construction 550 comprises intensive line 551a; 551b; 551c, the estranged line 552 that extends dense-in-itself set line 551c and one group of exemplary protection are conducted electricity shoulder type barrier line 553a with false (mean and do not possess the purpose of design when layer circuit such as telecommunication or electric energy transmitting function); 553b, 553c, it is arranged at intensive position to estranged transitional region.Among the embodiment that paints as accompanying drawing, each conduction shoulder type barrier line 553a, 553b, 553c all are connected to the line segment position of estranged line 552, and by the outside vertical extent in line segment position of estranged line 552.In other embodiment of part, conduction shoulder type barrier line is uninevitable vertical with the line segment position of estranged line 552, as long as conduction shoulder type barrier line is not directly connected to intensive line 551a, near other structure 551b or the intensive line is to avoid causing unnecessary mistake.Line segment position 554 is stretched out by a bent angle by intensive line 551a, and the distance between line segment position 554 and the intensive line 551c is not dimension limit (critical dimension in the line construction for this reason, CD) distance, therefore, in this embodiment, do not need to be provided with conduction shoulder type barrier line near line segment position 554 and the intensive line 551c.In another embodiment, if distance then is necessary to be provided with corresponding conduction shoulder type barrier line too near the function accuracy that may have influence on intensive line 551c between line segment position 554 and the intensive line 551c.
The length of each group conduction shoulder type barrier line need be enough to protect the interval, marine outfall, and the overall dimensions of conduction shoulder type barrier line can be followed the basic size or the spacing of general layer structure in the standard technology, to avoid causing technologic difficulty or extra manufacturing cost.Above-mentioned false conduction shoulder type barrier line does not have actual electric function, so do not need to be electrically connected to the connecting circuit (as electrical contact hole or through hole etc.) in other layer, yet for technologic convenience, false conduction shoulder type barrier line also can be connected on the false connecting circuit in other layer.For separating the convenience of saying, the design rule of the false conduction shoulder type barrier line described in this paragraph will describe through following example.
Fig. 6 illustrates according to the present invention the exemplary top view of one group of conduction shoulder type barrier line of the line construction of adjacent specific design among the part embodiment.As shown in Figure 6, line construction 600 among this embodiment comprises a detach segment 603 of intensive line bunch (by parallel intensive line 601a, 601b forms), two estranged line stretchers (be positioned at the estranged line 602a of intensive line top and be positioned at the estranged line 602b of intensive line below) and the minimum dimension of only being separated by.In addition, three groups of false conduction shoulder type barrier line 610a, 610b, 610c are disposed at this line construction 600.Wherein, conduction shoulder type barrier line 610a is connected to estranged line 602a in its interval, marine outfall, conduction shoulder type barrier line 610c is connected to estranged line 602b in its interval, marine outfall, and conduction shoulder type barrier line 610b is connected to the intensive line 601b in stage casing near the end points of detach segment 603.Although detach segment 603 is not directly to be extended out by intensive line 601b, the consistency of intensive line 601b live width also can improve because of the relation of false conduction shoulder type barrier line 610b.
Have and equal or various intensive near the line width of technological limits size restriction, all can utilize false conduction shoulder type barrier line that the embodiment of the invention discloses to reach live width protection effect to estranged transitional region.Fig. 7, Fig. 8, Fig. 9 and Figure 10 illustrate according to the several applications illustration that utilizes false conduction shoulder type barrier line with the protection circuit structure in the part example of the present invention; in addition in the lump display scan formula electron microscope (SEM) image its be presented near the zone, marine outfall defective circuit, wherein this defective circuit has hole, hole and space because of the membrane stress between transition region.
Fig. 7 A illustrates according to the present invention a kind of line construction 700 of the false conduction shoulder type barrier line that has protection usefulness among the part embodiment and looks schematic diagram on it.Shown in Fig. 7 A, this one needs shielded line construction 700 comprise the intensive line 701a that is positioned at middle section, 701b, the estranged line 702b that the estranged line 702a that 701c, dense-in-itself set line 701c up extend and another dense-in-itself set line 701c down extend.In addition, according to part embodiment of the present invention, one group of false conduction shoulder type barrier line 710a, 710b, 710c, the 710d configuration is extremely intensive to estranged transitional region.Wherein, conduction shoulder type barrier line 710a, 710b, 710c, 710d are connected to estranged line 702a, the end of 702b, and by this place stretch out and direction roughly with estranged line 702a, 702b is vertical.Because intensive line 701a is not to flush with 701b, so also do not line up between conduction shoulder type barrier line 710a and 710b or conduction shoulder type barrier line 710c and the 710d.Yet false conduction shoulder type barrier line must not need and estranged line 702a, and 702b is vertical, as long as conduction shoulder type barrier line is not directly connected to intensive line 701a, near other structure 701b or the intensive line is to avoid causing unnecessary mistake.Fig. 7 B is illustrated in the sweep electron microscope image that produces the line style defective under the protection mechanism situation with false conduction shoulder type barrier line on the line construction.
Fig. 8 A illustrates according to the present invention a kind of line construction 800 of the false conduction shoulder type barrier line that has protection usefulness among the part embodiment and looks schematic diagram on it.Shown in Fig. 8 A; the shielded line construction 800 of these need comprise the intensive line segment 801a that is positioned at middle section; 801b; 801c, 801d, the estranged line segment 802a that 801e, dense-in-itself set line segment 801c extend outward and two sections estranged line section 802b; 802c lays respectively at the intensive line 801a that staggers; 801b, 801d is between the 801e.According to one embodiment of the invention, utilize one group of false conduction shoulder type barrier line 810a, 810b, 810c, 810d, 810e, the 810f configuration illustrates to estranged transitional region to intensive.Wherein, false conduction shoulder type barrier line 810a, 810b, 810c, 810d, 810e, 810f are connected respectively to estranged line segment 802a or estranged line section 802b, 802c etc.In this embodiment, false conduction shoulder type barrier line 810a, 810b, 810c, 810d, 810e, 810f are roughly by the outside vertical extent of an end of one of them estranged line segment.Yet, false conduction shoulder type barrier line 810a, 810b, 810c, 810d, 810e, 810f must not need and estranged line segment 802a or estranged line section 802b, 802c is vertical, as long as conduction shoulder type barrier line is not directly connected to intensive line 801a, 801b, 801d, near 801e or the intensive line other structure is to avoid causing unnecessary mistake.Fig. 8 B is illustrated in the sweep electron microscope image that produces the line style defective under the protection mechanism situation with false conduction shoulder type barrier line on the line construction because of membrane stress.
Fig. 9 A illustrates according to the present invention a kind of line construction 900 of the false conduction shoulder type barrier line that has protection usefulness among the part embodiment and looks schematic diagram on it.Shown in Fig. 9 A, this one must shielded line construction 900 comprise the intensive line bunch that is positioned at middle section (comprise intensive line 901a, 901b, 901c) and the estranged line segment 902 that up extends of dense-in-itself set line segment 901c.According to one embodiment of the invention, utilize one group of false conduction shoulder type barrier line 910a, the 910b configuration illustrates to estranged transitional region to intensive.Wherein, false conduction shoulder type barrier line 910a, 910b are connected to estranged line segment 902 and outside vertical extent by rightabout respectively, are similar cruciform pattern.The cruciform pattern of this type often is found in the both sides of the intensive line of symmetry at place, circuit transition region marine outfall.Yet false conduction shoulder type barrier line 910a, 910b must not need vertical with estranged line segment 902, as long as conduction shoulder type barrier line is not directly connected to intensive line 901a, near other structure 901b or the intensive line is to avoid causing unnecessary mistake.Fig. 9 B is illustrated in the sweep electron microscope image that produces the line style defective under the protection mechanism situation with false conduction shoulder type barrier line on the line construction because of membrane stress.
Under the part situation, have that the intensive line of narrow spaced features is bunch inevitable not to be made of most bar circuits.Figure 10 A looks a kind of line construction 1000 that schematic diagram illustrates according to the present invention the false conduction shoulder type barrier line that has protection usefulness among the part embodiment on one, it has unconventional intensive line structure.In this example, unconventional intensive line bunch comprise short line segment (intensive line 1001a), contiguous contact mat 1001b and be clipped in short line segment and contact mat 1001b between intensive line 1001c.Estranged line 1002 is stretched by intensive line 1001c top and the right side between transition region forms the Haikou district.According to part embodiment of the present invention, utilize false conduction shoulder type barrier line 1005 to dispose and illustrate to the top of contact mat 1001b.Wherein, false conduction shoulder type barrier line 1005 is connected to estranged line 1002 and outside vertical extent.Yet, false conduction shoulder type barrier line 1005 must not need vertical with estranged line 1002, as long as conduction shoulder type barrier line 1005 is not directly connected to intensive line 1001a, intensive contact mat 1001b or near other structure the dense feature, to avoid causing unnecessary mistake.Figure 10 B is illustrated near line construction under the protection mechanism situation with false conduction shoulder type barrier line produces line style defective contact mat sweep electron microscope image.
In addition, the false conduction shoulder type barrier line of protection usefulness also can form with L font, O font, U font or other curve mode, replaces the linear pattern of describing in the aforementioned exposure paragraph.Figure 11 illustrates the illustrated embodiment according to the false conduction shoulder of a kind of L font type barrier line among other interchangeable embodiment of the present invention.In the top view of this embodiment as can be known, line construction 1100 comprises the intensive line that is positioned at middle section and bunch (comprises intensive line 1101a, 1101b, 1101c), the estranged line segment 1102b that down extends of the estranged line segment 1102a that up extends of dense-in-itself set line segment 1101c and dense-in-itself set line segment 1101c.According to one embodiment of the invention, utilize the false conduction shoulder type barrier line 1110a of one group of L font, 1110b, the 1110c configuration illustrates to estranged transitional region to intensive.Wherein, the false conduction shoulder of L font type barrier line 1110a, 1110b, 1110c are connected respectively to estranged line 1102a or estranged line 1102b and outside vertical extent.Yet, false conduction shoulder type barrier line 1110a, 1110b, 1110c must not need vertical with estranged line 1102a or estranged line 1102b, as long as L font conduction shoulder type barrier line is not directly connected to intensive line 1110a, near 1110b or the intensive line other structure is to avoid causing unnecessary mistake.
Figure 12 A illustrates according to its method flow schematic diagram of step one by one of false conduction shoulder type barrier line structure is set in Wiring technique among the part embodiment of the present invention to Figure 12 D.(step 1) illustrates how to distinguish the position that false conduction shoulder type barrier line optionally is set to Figure 12 A.In the middle of step 1, need distinguish in the relevant wiring layer of apparent line segment (as intensive line) and space therebetween earlier near the technological limits size, and it is grouped into a block, this block comprises a circuit 1232 that is clipped between space 1231 and the space 1233 in this figure.Figure 12 B and Figure 12 C (step 2) illustrate and how to distinguish and look interval, a marine outfall.In step 2, draw earlier many square frames with preliminary dimension, wherein those square frames are to utilize this block in the step 1 and estranged line 1232 respectively as the edge (as Figure 12 B) of those square frames respectively.And then filtering comprises any circuit square frame (as the square frame among Figure 12 C 1253), does not contain the formed marine outfall of any estranged line structure because of it, must give up so be not suitable for being provided with false conduction shoulder type barrier line.Therefore, pick out square frame 1251,1252 at last, 1254 is the interval square frame in marine outfall.The preliminary dimension of above-mentioned square frame is to be determined by various process conditions, for example the dimension limit of circuit, intensive distance between centers of tracks, desirable transition live width correction value and other technological parameter that is used for adjacent domain.(step 3) illustrates how to determine false conduction shoulder type barrier line actual position of establishing of painting in the square frame in interval, marine outfall to Figure 12 D.Be to form false conduction shoulder type barrier line 1281,1282,1284 respectively among the square frame 1251,1252,1254 in interval, marine outfall in step 3, wherein false conduction shoulder type barrier line is connected on the estranged line segment and vertically stretches out haply.Wherein the edge of the interval square frame in marine outfall and other intensive line keep a preset distance at interval at least, make wherein false conduction shoulder type barrier line structure reach this more than preset distance away from other intensive line whereby.In addition, false conduction shoulder type barrier line must not need to be the just in time vertical relation of an angle of 90 degrees with other estranged line.Conduction shoulder type barrier line can be straight line, curve or folding line (for example L font line).
Following paragraph for the print result of on different chips, carrying out the line construction among similar Fig. 1 relatively, utilize experimental data that therebetween difference is described.Adopt the different technology practices between each wafer, show the experimental result of the linewidth error value under the different process in the table ().Wafer A is not provided with any empty interposed structure as protection usefulness, and (standard deviation σ) is-5.7 nanometers to the standard deviation of its error; Wafer B is provided with traditional empty interposed structure pattern (dummification pattern) in other 100 nanometers of metallic circuit, and (standard deviation σ) is-2.9 nanometers to the standard deviation of the error that it obtains; Wafer C is provided with the conduction shoulder type barrier line of this case, the standard deviation of the error that it obtains (standard deviation, σ) be-1.7 nanometers, this shows that employing false conduction shoulder type barrier line manufacturing technology as shown in the embodiment of the present invention can be improved the error situation of wiring.
The experimental result of the linewidth error value under table (one) different process
| Wafer | State | Error (nanometer nm) |
| A | There is not empty interposed structure | -5.7 |
| B | General empty interposed structure (100 nanometers) | -2.9 |
| C | False conduction shoulder type barrier line | -1.7 |
Though the present invention discloses as above with execution mode; right its is not in order to limit the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the scope that appending claims defines.
Claims (10)
1. a line construction is characterized in that, is used for the semiconductor integrated circuit, and this line construction comprises:
One substrate; And
One stratiform structure, it is arranged on this substrate, and this layer structure comprises:
Several first kind lines, it has one and closely arranges style;
One second class line, it is provided with contiguous those first kind lines; And
Several the 3rd class lines, it is provided with contiguous those first kind lines and this second class line, and wherein those the 3rd class lines are connected to this second class line, and those the 3rd classes are linear is formed on vertical with this second class line haply direction.
2. line construction according to claim 1 is characterized in that, those the 3rd class lines are a L font or a U font.
3. line construction according to claim 1 is characterized in that, a T font mode shown greatly by those the 3rd class lines or a cross mode is connected to this second class line.
4. line construction according to claim 1, it is characterized in that, further comprise several functional properties conductivity through holes, those functional properties conductivity through holes are arranged in the insulating barrier, and wherein those the 3rd class lines directly do not pile up or are covered on those functional properties conductivity through holes in this insulating barrier or down.
5. line construction according to claim 1 is characterized in that, those the 3rd class lines are to pile up or be covered on the false through hole in the insulating barrier or down.
6. semiconductor integrated circuit is characterized in that it comprises:
One substrate;
One insulating barrier is formed on this substrate, and it comprises a connecting circuit; And
The conductive line construction of one tool is arranged on this insulating barrier, and this line construction comprises:
Several intensive lines, it has one and closely arranges style, and wherein those intensive lines are connected to this connecting circuit in this insulating barrier;
One estranged line, it is provided with contiguous those intensive lines, and wherein this estranged line is connected to this connecting circuit in this insulating barrier; And
One conduction shoulder type barrier line, it is provided with contiguous those intensive lines and this estranged line, wherein this conduction shoulder type barrier line is connected to this estranged line and is formed at haply on the direction vertical with this estranged line, wherein should conduction shoulder type barrier line directly link to each other with this connecting circuit in this insulating barrier.
7. semiconductor integrated circuit according to claim 6 is characterized in that, this is closely arranged style and has a spacing, and this conduction shoulder type barrier line has a length greater than this spacing.
8. semiconductor integrated circuit according to claim 6, it is characterized in that, those intensive lines, this estranged line maybe this conduction shoulder type barrier line are a L font respectively and have a main line segment and an attached line segment, roughly vertical and this attached line segment of this main line segment with this estranged line roughly with this estranged line parallel.
9. the method for designing of a line construction is characterized in that, is used for the semiconductor integrated circuit, and this method for designing comprises the following step:
Distinguish the interval, a marine outfall of looking contiguous an estranged line and several intensive lines; And
Add a shoulder type and intercept, wherein should the shoulder type intercept and be connected with this estranged line and roughly vertical with this estranged line to this interval, marine outfall.
10. the method for designing of line construction according to claim 9 is characterized in that, distinguishes that looking contiguous this interval, marine outfall comprises the following step:
Distinguish and look several intensive lines that those intensive lines have a predetermined live width respectively;
Distinguish and look those intensive lines several spaces therebetween;
With those space groups is a block;
Several borders that define this block are as this interval, marine outfall;
Drafting has one first square frame of a preliminary dimension, and wherein this first square frame utilizes interval and this estranged line in this marine outfall several edges as this first square frame; And
Draw one second square frame with the part of this first square frame, wherein this second square frame utilizes this estranged line to keep a preset distance as one of them edge of this second square frame and with those intensive lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/753,272 US8692351B2 (en) | 2010-04-02 | 2010-04-02 | Dummy shoulder structure for line stress reduction |
| US12/753,272 | 2010-04-02 |
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| Publication Number | Publication Date |
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| CN102214637A true CN102214637A (en) | 2011-10-12 |
| CN102214637B CN102214637B (en) | 2013-11-13 |
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| CN2010105705814A Active CN102214637B (en) | 2010-04-02 | 2010-11-29 | A circuit structure, a semiconductor integrated circuit having the same and a design method thereof |
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| US (2) | US8692351B2 (en) |
| CN (1) | CN102214637B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8341562B1 (en) * | 2011-07-21 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing metal pits through optical proximity correction |
| US9026955B1 (en) * | 2013-10-11 | 2015-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology for pattern correction |
| US9411924B2 (en) | 2013-10-11 | 2016-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology for pattern density optimization |
| US9263349B2 (en) * | 2013-11-08 | 2016-02-16 | Globalfoundries Inc. | Printing minimum width semiconductor features at non-minimum pitch and resulting device |
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|---|---|---|---|---|
| US20020070392A1 (en) * | 1998-11-04 | 2002-06-13 | Hiroaki Ohkubo | Electronic device, semiconductor device, and electrode forming method |
| CN1378266A (en) * | 2001-04-04 | 2002-11-06 | 华邦电子股份有限公司 | Method for generating virtual pattern of metal layer |
| US20030199150A1 (en) * | 2002-04-17 | 2003-10-23 | David Permana | Method of preventing seam defects in isolated lines |
| JP2005150389A (en) * | 2003-11-14 | 2005-06-09 | Semiconductor Leading Edge Technologies Inc | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101395060B1 (en) * | 2007-09-18 | 2014-05-15 | 삼성전자주식회사 | Semiconductor device including line patterns |
| JP2009170807A (en) * | 2008-01-18 | 2009-07-30 | Elpida Memory Inc | Semiconductor device provided with dummy gate pattern |
| US20100213569A1 (en) * | 2009-02-20 | 2010-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits having fuses and systems thereof |
-
2010
- 2010-04-02 US US12/753,272 patent/US8692351B2/en active Active
- 2010-11-29 CN CN2010105705814A patent/CN102214637B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020070392A1 (en) * | 1998-11-04 | 2002-06-13 | Hiroaki Ohkubo | Electronic device, semiconductor device, and electrode forming method |
| CN1378266A (en) * | 2001-04-04 | 2002-11-06 | 华邦电子股份有限公司 | Method for generating virtual pattern of metal layer |
| US20030199150A1 (en) * | 2002-04-17 | 2003-10-23 | David Permana | Method of preventing seam defects in isolated lines |
| JP2005150389A (en) * | 2003-11-14 | 2005-06-09 | Semiconductor Leading Edge Technologies Inc | Semiconductor device |
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| Publication number | Publication date |
|---|---|
| US20110241207A1 (en) | 2011-10-06 |
| CN102214637B (en) | 2013-11-13 |
| US20140208283A1 (en) | 2014-07-24 |
| US8692351B2 (en) | 2014-04-08 |
| US9437485B2 (en) | 2016-09-06 |
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