CN102208341A - Method for reducing resistance of polycrystalline silicon grid - Google Patents
Method for reducing resistance of polycrystalline silicon grid Download PDFInfo
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- CN102208341A CN102208341A CN2010101375124A CN201010137512A CN102208341A CN 102208341 A CN102208341 A CN 102208341A CN 2010101375124 A CN2010101375124 A CN 2010101375124A CN 201010137512 A CN201010137512 A CN 201010137512A CN 102208341 A CN102208341 A CN 102208341A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 89
- 238000000034 method Methods 0.000 title claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000005516 engineering process Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 82
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000003701 mechanical milling Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000001376 precipitating effect Effects 0.000 abstract 3
- 238000001035 drying Methods 0.000 abstract 1
- 238000000227 grinding Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 4
- 229910021645 metal ion Inorganic materials 0.000 description 4
- 210000004483 pasc Anatomy 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910021352 titanium disilicide Inorganic materials 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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Abstract
The invention discloses a method for reducing the resistance of a polycrystalline silicon grid, which comprises the following steps of: 1, precipitating one layer of interlayer media on the surface of a silicon wafer of a formed polycrystalline silicon grid; 2, flattening the layer of interlayer media by a chemical machine grinding technology or a dry process reverse etching technology until the upper surface of the polycrystalline silicon grid is exposed; 3, precipitating one layer of metal on the surface of the silicon wafer, and then carrying out a high-temperature annealing technology, thereby forming metal silicide on the polycrystalline silicon grid and then removing metal on a zone outside the polycrystalline silicon grid; and 4, precipitating interlayer media again on the surface of the silicon wafer. The method is compatible with the traditional equipment and production line. The resistance of the polycrystalline silicon grid can be obviously reduced, and the resistivity can be reduced to be below 1 ohm per centimetre to a lowest extent.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device.
Background technology
Semiconductor device based on polysilicon gate is present main flow, is made widely and uses.But silicon materials are a kind of semi-conducting materials, and its resistivity though can adopt the method for impurity to reduce its resistivity, has its limit than higher.Typically the bulk concentration that adopts ion implantation doping process can only reach impurity to polysilicon is 1 * 10
21～1 * 10
22Atom/cm
3(every cubic centimetre in atom), the resistivity of the polysilicon after the doping are about 40～100 Ω cm (ohmcm).The resistivity of such polysilicon gate can't satisfy the requirement of high speed device to speed and frequency.
For the semiconductor device of high speed or high frequency, do not adopt polysilicon to make grid usually at present, but adopt SiGe (SiGe), InP (indium phosphide) or metal to make grid.But this type of material is special, and technology difficulty is big, and price is far longer than the semiconductor device of common polysilicon gate usually.
For the common semiconductor device based on polysilicon gate, in order to reduce the resistivity of polysilicon gate, method commonly used is to form metal silicide, metal silicide commonly used such as WSi at the top of polysilicon gate
2(two tungsten silicides) etc.WSi is formed on the top at polysilicon gate
2Method as follows:
The 1st step saw also Fig. 1 a, first deposit one deck polysilicon 4 on silicon substrate 1, and the tungsten of deposit layer of metal again 7 then carries out high-temperature annealing process and makes tungsten 7 and polysilicon 4 reactions form two tungsten silicides.
The 2nd step saw also Fig. 1 b, etch polysilicon 4 and two tungsten silicides, form polysilicon gate 41 and on two tungsten silicides 71.
The 3rd step saw also Fig. 1 c, carries out lightly doped drain and inject (LDD) technology in the silicon substrate 1 of polysilicon gate 41 down either side, formed light dope ion implanted region 2.
The 4th step saw also Fig. 1 d, polysilicon gate 41 and on the both sides of two tungsten silicides 71 form side wall 5.
The 5th step saw also Fig. 1 e, carries out the source and leak injection technology in the silicon substrate 1 of the outer side-lower of two side walls 5, formed heavy-doped source and leaked injection region 3.
In the 6th step, see also Fig. 1 f, at silicon chip surface deposit one deck inter-level dielectric (ILD) 6.
Follow-up formation contact hole and carry out interconnection process.
Said method forms WSi at the top of polysilicon gate
2, typical WSi
2Resistivity be 5～20 Ω cm, though decrease, but can't satisfy at a high speed or the requirement of high-frequency element.And said method had just been introduced metal before polysilicon gate forms, metal ion can pollute semiconductor equipment and make whole cavity be infected with metal ion.Metal ion is a kind of very active dopant ion, in case enter in the normal device, can greatly change the performance of device.Therefore all adopt special installation and production line to produce specially for the technology that contains metal.
In the conventional semiconductor manufacturing process, metal commonly used is W (tungsten), Cu (copper), Al (aluminium), and semiconductor manufacturer only has the line configuration of these several metals usually.In conjunction with the production technology that reduces the polysilicon gate electrode resistance, semiconductor manufacturer generally can only form WSi at the top of polysilicon gate
2
If use Ti (titanium), Co (cobalt), Ni (nickel) to form the top that metal silicide covers polysilicon gate, the resistivity of polysilicon gate is reduced to below the 1 Ω cm with pasc reaction.But for these non-common metals, semiconductor manufacturer need dispose production line separately to each metal, this needs extremely expensive cost, and therefore under the production technology of traditional reduction polysilicon gate electrode resistance, general semiconductor factory may adopt these metals to produce hardly.
In addition in order to reduce the contact resistance of contact hole electrode, the semiconductor industry forms metal silicide in the position of contact hole usually, promptly form metal silicide on grid, source electrode, drain electrode etc. earlier, the bottom of contact hole electrode contacts with these metal silicides then.The method that reduces the resistance of contact hole electrode at present comprises the steps:
In the 1st step, forming silicon chip surface deposit one deck inter-level dielectric of polysilicon gate;
The 2nd step, adopt photoetching process and dry etch process or wet corrosion technique to remove the inter-level dielectric of contact hole position, expose the silicon (polysilicon) of contact hole position;
The 3rd step, in silicon chip surface deposit layer of metal, carry out high-temperature annealing process then, form metal silicide in the contact hole position;
In the 4th step, the metal silicide of reservation contact hole position is removed the metal of contact hole position with exterior domain;
In the 5th step, carry out follow-up formation contact hole and interconnection process.
But this method has significant limitation to domain, sees also Fig. 3, and contact hole is represented in the rhombus fill area among Fig. 3, and dashed rectangle is represented the metal silicide of contact hole position.For fear of short circuit between grid and source electrode, the drain electrode, will form metal silicide on grid, source electrode, the drain electrode must isolate mutually.Again in order to reduce the leakage current between grid and source electrode, the drain electrode, can not all form metal silicide on the grid, therefore can only on the part of the place of grid, form metal silicide usually, and can't on the active area part of grid, form metal silicide.For the following technology of 0.18 μ m, the size of grid and active area is all very little, will be more strict to the requirement of domain, and the method that therefore reduces the resistance of contact hole electrode is not suitable for the method for the resistance of the reduction polysilicon gate that the present invention discusses.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method that reduces the polysilicon gate electrode resistance, has overcome the limitation that traditional handicraft can only adopt tungsten, can reduce the resistance of polysilicon gate greatly.
For solving the problems of the technologies described above, the method that the present invention reduces the resistance of polysilicon gate comprises the steps:
In the 1st step, forming silicon chip surface deposit one deck inter-level dielectric of polysilicon gate;
The 2nd the step, with chemical mechanical milling tech and/or dry method anti-carve technology to this layer by layer between medium carry out planarization, until the upper surface that exposes polysilicon gate;
The 3rd step, in silicon chip surface deposit layer of metal, then carry out high-temperature annealing process, thereby above polysilicon gate, form metal silicide, then remove the metal of polysilicon gate with the exterior domain top;
The 4th step is at silicon chip surface deposit for the second time inter-level dielectric.
The present invention is when introducing metal, and except that the upper surface exposure of polysilicon gate, other zones on the silicon chip are all covered by the interlayer medium and protect, and has so just avoided the problem of metal ion to the device region diffusion of silicon chip fully.
And the present invention introduces metal after forming metal silicide above the polysilicon gate, subsequent technique is that contact hole forms technology and interconnection process, the equipment of subsequent technique has not been afraid of the pollution of metal material, and conventional semiconductor manufacturer can utilize existing device and production line to be achieved fully.
Therefore the method for the invention can adopt any metal silicide with low resistivity, can significantly reduce the resistance of polysilicon gate, and the minimum resistivity that makes is reduced to below the 1 Ω cm.
Description of drawings
Fig. 1 a～Fig. 1 f is each step schematic diagram of method of the resistance of existing reduction polysilicon gate;
Fig. 2 a～Fig. 2 e is each step schematic diagram of the method for the present invention's resistance of reducing polysilicon gate;
Fig. 3 is the domain schematic diagram of method of the resistance of existing reduction contact hole electrode.
Description of reference numerals among the figure:
The 1-silicon substrate; 2-light dope ion implanted region; The 3-heavy-doped source leaks the injection region; The 4-polysilicon; The 41-polysilicon gate; The 5-side wall; The 6-inter-level dielectric; The 7-tungsten; 71-two tungsten silicides.
Embodiment
The method that the present invention reduces the polysilicon gate electrode resistance comprises the steps:
The 1st step saw also Fig. 2 a, was forming silicon chip surface deposit one deck inter-level dielectric 6 of polysilicon gate 41.
In the 2nd step, adopt cmp (CMP) technology and/or dry method to anti-carve technology inter-level dielectric 6 is carried out planarization, until the upper surface that exposes polysilicon gate 41.
The 3rd step saw also Fig. 2 d, at silicon chip surface deposit one deck refractory metal, carried out high-temperature annealing process then, and in the zone that silicon is arranged, metal and pasc reaction form metal silicide.Have only polysilicon gate 41 tops to form metal silicide 71, other zones on the silicon chip are still metal.
To remove the metal removal of polysilicon gate 41 on the silicon chip then, and keep the metal silicide 71 of polysilicon gate 41 tops with the top of exterior domain.
The 4th step saw also Fig. 2 e, at silicon chip surface deposit for the second time inter-level dielectric 6.
After above-mentioned 4 steps, follow-up formation contact hole and carry out interconnection process.
Said method for example specifically comprised the steps: again in the 1st step
The 1.1st step, deposit one deck polysilicon on silicon substrate 1, this layer of etching polysilicon forms polysilicon gate 41;
The 1.2nd step, in the silicon substrate 1 of the down either side of polysilicon gate 41, carry out the lightly doped drain injection technology, form lightly-doped source and leak injection region 2;
The 1.3rd step at silicon chip surface deposit one deck medium (as silicon nitride), anti-carved this layer medium with dry etch process, thereby formed side wall 5 in the both sides of polysilicon gate;
The 1.4th step, outside two side walls 5, to carry out the source in the silicon substrate 1 of side-lower and leak injection technology, injection region 3 is leaked in the formation source;
The 1.5th step is at silicon chip surface deposit one deck inter-level dielectric 6.
Above-mentioned the 1.1st step to 1.5 steps only are example, for example the 1.3rd step and nonessential, can omit.Some ubiquitous semiconductor device structures also omit, and for example can comprise epitaxial loayer in the silicon substrate, and the polysilicon gate below has gate oxide etc.
Said method for example specifically comprised the steps: again in the 2nd step
The 2.1st step saw also Fig. 2 b, adopted chemical mechanical milling tech that inter-level dielectric 6 is ground, and the control that stops of CMP can be controlled the employing time, in fact there is no strict demand;
The 2.2nd step saw also Fig. 2 c, adopted dry etch process to anti-carve the remaining inter-level dielectric 6 of silicon chip surface, until the upper surface that exposes polysilicon gate 41.
Above-mentioned the 2.1st step, the 2.2nd step only are example, and the 2nd step of said method also can only be adopted chemical mechanical milling tech, perhaps only adopts dry method to anti-carve technology, perhaps adopt dry method to anti-carve technology earlier and adopt chemical mechanical milling tech again.
Common semiconductor device, the highest point that protrudes in silicon chip surface must be a grid, grid is usually than the second eminence height that protrudes in silicon chip surface at least
Therefore after the method for the invention the 2nd went on foot and finishes, when exposing the upper surface of polysilicon gate 41, other zones on the silicon chip were all still covered by interlayer medium 6 and protect.
Said method after the upper surface that exposes polysilicon gate 41, will guarantee that at least the minimum thickness of the inter-level dielectric 6 that other zones of silicon chip except that polysilicon gate 41 are covered exists in the 2nd step
More than.
Said method is in the 3rd step, and refractory metal for example is Ti, Co, Ni etc., and the metal silicide 71 that itself and pasc reaction form is respectively TiSi
2(titanium disilicide), CoSi
2(cobalt disilicide), NiSi (nickle silicide).These metal silicides 71 cover the top of polysilicon gate 41, can allow the resistivity of polysilicon gate be reduced to below the 1 Ω cm.
Said method can adopt metal and metal silicide are had the wet corrosion technique removal metal of higher selection ratio and keep metal silicide in the 3rd step.For example HF (hydrofluoric acid) is to TiSi
2The etching speed of (titanium disilicide) is just much smaller than its etching speed to Ti.
Said method is in the 4th step, and the inter-level dielectric of deposit for the second time can be same material with the inter-level dielectric of the deposit first time, also can be different materials.Its range of choice to material is the same with the inter-level dielectric of deposit for the first time.
Because the present invention reduces the method for polysilicon gate electrode resistance; the employing inter-level dielectric has been protected the silicon chip except that polysilicon gate; the step that again depositing metal and high annealing is formed metal silicide is placed on contact hole carries out before forming technology and interconnection process, has therefore broken through and can only adopt W to form WSi
2Limitation, can adopt any metal and pasc reaction to form metal silicide.And the method for the invention need not Special Equipment and production line, can be compatible fully with existing MOS transistor production technology.In addition, of the present invention to domain without limits, can be applicable to undersized process for fabrication of semiconductor device.
Claims (9)
1. a method that reduces the polysilicon gate electrode resistance is characterized in that, comprises the steps:
In the 1st step, forming silicon chip surface deposit one deck inter-level dielectric of polysilicon gate;
The 2nd the step, with chemical mechanical milling tech and/or dry method anti-carve technology to this layer by layer between medium carry out planarization, until the upper surface that exposes polysilicon gate;
The 3rd step, in silicon chip surface deposit layer of metal, then carry out high-temperature annealing process, thereby above polysilicon gate, form metal silicide, then remove the metal of polysilicon gate with the exterior domain top;
The 4th step is at silicon chip surface deposit for the second time inter-level dielectric.
2. the method for reduction polysilicon gate electrode resistance according to claim 1 is characterized in that, described the 1st step of method specifically comprises the steps: again
The 1.1st step, deposit one deck polysilicon on silicon substrate, this layer of etching polysilicon forms polysilicon gate;
The 1.2nd step, in the silicon substrate of the down either side of polysilicon gate, carry out the lightly doped drain injection technology, form lightly-doped source and leak the injection region;
The 1.3rd step at silicon chip surface deposit one deck medium, anti-carved this layer medium with dry etch process, thereby formed side wall in the both sides of polysilicon gate;
The 1.4th step, outside two side walls, to carry out the source in the silicon substrate of side-lower and leak injection technology, the injection region is leaked in the formation source;
The 1.5th step is at silicon chip surface deposit one deck inter-level dielectric.
3. the method for reduction polysilicon gate electrode resistance according to claim 1 is characterized in that, described method is in the 1st step, and described inter-level dielectric is silicon dioxide, silicon nitride, silicon oxynitride or its mixture pure or that be doped with boron, phosphorus, fluorine.
4. the method for reduction polysilicon gate electrode resistance according to claim 2 is characterized in that, described method is in the 1.3rd step, and described side wall is silicon dioxide, silicon nitride, silicon oxynitride or its mixture pure or that be doped with boron, phosphorus, fluorine.
5. the method for reduction polysilicon gate electrode resistance according to claim 2 is characterized in that, described side wall and inter-level dielectric are different materials.
6. the method for reduction polysilicon gate electrode resistance according to claim 1 is characterized in that, described the 2nd step of method specifically comprises the steps: again
In the 2.1st step, adopt chemical mechanical milling tech that inter-level dielectric is ground;
In the 2.2nd step, adopt dry etch process to anti-carve the remaining inter-level dielectric of silicon chip surface, until the upper surface that exposes polysilicon gate.
7. the method for reduction polysilicon gate electrode resistance according to claim 1 is characterized in that, after described method the 2nd went on foot and finishes, when exposing the upper surface of polysilicon gate, other zones on the silicon chip were all still covered by the interlayer medium.
8. the method for reduction polysilicon gate electrode resistance according to claim 7 is characterized in that, after described method the 2nd went on foot and finishes, the minimum thickness of the inter-level dielectric that area of silicon wafer covered except that polysilicon gate existed
More than.
9. the method for reduction polysilicon gate electrode resistance according to claim 1 is characterized in that, described method is in the 3rd step, and institute's metals deposited is any one in titanium, cobalt, the nickel.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1943027A (en) * | 2004-02-25 | 2007-04-04 | 国际商业机器公司 | CMOS silicide metal gate integration |
| CN101459068A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Production method for metal silicide contact layer |
-
2010
- 2010-03-31 CN CN2010101375124A patent/CN102208341A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1943027A (en) * | 2004-02-25 | 2007-04-04 | 国际商业机器公司 | CMOS silicide metal gate integration |
| CN101459068A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Production method for metal silicide contact layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140109 |
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Effective date of registration: 20140109 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20111005 |