CN102201815B - Binary operation decoding device with high operation frequency - Google Patents

Abstract

The invention provides a binary operation decoding device with high operation frequency. The binary operation decoding device comprises a first lookup table and a second lookup table, wherein the input end of the first lookup table and the input end of the second lookup table are coupled with the output end of a first register and used for receiving signals output by the first register; the input end of a third look-up table is coupled with the output end of the first look-up table and used for receiving the signal output by the first look-up table; the input end of a fourth look-up table is coupled with the output end of the second look-up table and used for receiving the signal output by the second look-up table; a first multiplexer having a first input terminal for receiving the signal outputted from the third look-up table, and a second input terminal for receiving the signal outputted from the fourth look-up table; and a second multiplexer having a first input terminal for receiving the signal outputted from the third look-up table and a second input terminal for receiving the signal outputted from the second look-up table.

Description

Binary operation decoding device with high operation frequency

technical field

The invention relates to a multi-bit full-text self-adaptive binary arithmetic coding decoder, in particular to a two-bit full-text self-adaptive binary arithmetic coding decoder with a shortened key path.

Background technique

The Context-adaptive Binary Arithmetic Coding (CABAC) decoding algorithm uses basic sequential operations to calculate ranges, offsets, and look-up tables for context variables. The data-dependent nature of full-text adaptive binary arithmetic coding and decoding results in 3 billion operations per second when processing high-definition images in real time, making full-text adaptive binary arithmetic coding and decoding difficult To achieve high-speed decoding. Basically, the full-text adaptive binary arithmetic coding bit decoder includes a decision bit decoder and a bypass bit decoder. Through experiments, it can be known that 80%-90% of all bits are encoded as decision bits, while the rest are coded as decision bits. Coded as bypass bits. Although U.S. Patent No. 7,262,722 of Jahanghir et al. has disclosed a method for improving the performance of full-text adaptive binary arithmetic coding using a parallel architecture, the full-text adaptive binary arithmetic coding decoding algorithm is not like video decoding of other H.264/AVC standards tools, it is not easy to use a parallel architecture to improve the performance of full-text adaptive binary arithmetic coding. Because the decoding of the full-text adaptive binary arithmetic coding uses continuous sequential decoding, however, the continuous sequential decoding will make the full-text adaptive binary arithmetic coding decoding the main bottleneck of the H.264/AVC standard.

Contents of the invention

An embodiment of the present invention discloses a bit decoder for multi-bit full-text adaptive binary arithmetic coding, including a first look-up table, with an input end coupled to an output end of a first register for receiving the first A signal output by the register; a second look-up table, having an input end coupled to the output end of the first register, for receiving the signal output by the first register; a third look-up table, having an input end coupled to the The output end of the first look-up table is used to receive the signal output by the first look-up table; a fourth look-up table has an input end coupled to the output end of the second look-up table for receiving the second look-up table The signal output by the table; a first multiplexer, with a first input end coupled to the output end of the third look-up table for receiving the signal output by the third look-up table, a second input end coupled to the The output end of the fourth look-up table is used to receive the output signal of the fourth look-up table; and a second multiplexer has a first input end coupled to the output end of the first look-up table for receiving For the signal output by the third look-up table, a second input end is coupled to the output end of the second look-up table for receiving the signal output by the second look-up table; wherein the first multiplexer and the second multiplexer All devices are controlled by a first signal. The bit decoder also includes a second register, a first adder, a second adder and a first comparison module connected in series, and the first comparison module is used for outputting the first signal. The bit decoder also includes a third multiplexer, with a first input end coupled to the output end of the second multiplexer through a third register, for receiving signals output by the second multiplexer; A fifth look-up table, having an input end coupled to the output end of the third multiplexer, for receiving the signal output by the third multiplexer; a sixth look-up table, having an input end coupled to the The output end of the third multiplexer is used to receive the signal output by the third multiplexer; a seventh look-up table has an input end coupled to the output end of the fifth look-up table for receiving the fifth The signal output by the look-up table; an eighth look-up table, having an input end coupled to the output end of the sixth look-up table, for receiving the signal output by the sixth look-up table; a fourth multiplexer, having a first An input end is coupled to the output end of the seventh look-up table for receiving the output signal of the seventh look-up table, and a second input end is coupled to the output end of the eighth look-up table for receiving the eighth look-up table The signal output by the look-up table; and a fifth multiplexer, which has a first input end coupled to the output end of the fifth look-up table for receiving the signal output by the fifth look-up table, and a second input end coupled Connected to the output terminal of the sixth look-up table to receive the output signal of the sixth look-up table; wherein both the fourth multiplexer and the fifth multiplexer are controlled by a second signal; wherein the first register The input end of the fifth multiplexer is coupled to the output end of the fifth multiplexer for storing the output signal of the fifth multiplexer. The bit decoder also includes a third adder, a fourth adder and a second comparison module connected in series, and the second comparison module is used for outputting the second signal.

Description of drawings

FIG. 1 is a schematic diagram of a video processing system.

FIG. 2 is a schematic diagram of a decision bit decoder of the video processing system of FIG. 1 .

FIG. 3 illustrates the critical path of the decision bit decoder of FIG. 2 .

FIG. 4 is a schematic diagram of a decision bit decoder disclosed by an embodiment of the present invention.

5 and 6 illustrate the detailed architecture of the decision bit decoder in FIG. 4 .

7 and 8 illustrate critical paths of the decision bit decoders of FIGS. 5 and 6 .

Description of reference symbols

10 Video processing system

11 Video source

12 Video Processor

13 Video Display

20 Decoder

25, 40, 405 registers

35 Decision Bit Decoder

30 bypass bit decoder

100, 300, 400 bit decoders

102, 116, 502 range registers

103, 503, 115, 530 Status index register

104, 652 rLPS lookup table

105, 505, 611 LPS lookup table

106, 506, 612 MPS lookup table

107, 110, 111, 112, 415, 409, 515, 516, 517, 518, 519, 610, 616, 623, 618, 620, 621, 622 Multiplexer

108, 109, 508, 509, 641, 643 adders

113, 513, 630 Comparison Module

114, 514, 635 Renormalization module

117, 501, 101 Offset register

118, 520 Input bit stream

119, 120 Update value

407, 500, 700 The first decision bit decoder

420, 600, 800 Second decision bit decoder

552, 614 The first rLPS look-up table

555, 613 Second rLPS look-up table

550 rLPS register

Detailed ways

FIG. 1 is a schematic diagram of a video processing system 10 for determining a multi-bit bin decoder. The video processing system 10 includes a video source 11 , a video processor 12 and a video display 13 . The video source 11 may be a reproduced or transmitted video signal that has been compressed and/or encoded using the H.264/AVC standard, wherein the H.264/AVC standard uses context-based adaptive binary arithmetic coding (Context-based adaptive binary arithmetic coding). coding, CABAC) technology for compression and/or encoding. The video source 11 outputs the H.264/AVC signal to the video processor 12 for decoding and reconstruction into an original video signal, and then the video processor 12 outputs the H.264/AVC signal to the video display 13 for users to watch.

The video processor 12 may include a processor, a decoder 20 and a memory. The processor is used to control the operation of the video processor 12; the decoder 20 is used to decode the incoming video signal; the memory is used to store the video signal, store data and/or look-up tables used in the decoding process, And used as a working area, in addition, the memory is also used as a confluence area and the connection of different parts in the video processor 12 . In addition, the decoder 20 may include one or more registers 25, 40, a decision bin decoder 35, and a bypass bin decoder 30.

FIG. 2 is a bit decoder 100 that processes one bit per clock (bin-per-cycle) of the video processing system 10 . The bit decoder 100 may comprise an offset register 101, a range register 102, a state index register 103, a reference least probable state (reference least probablestate, rLPS) look-up table 104, a least probable state (least probable state, LPS) look-up table 105, a most probable state (most probable state, MPS) look-up table 106, a plurality of adders 108,109, a plurality of multiplexers 107,110,111,112, a comparison module 113, a re-regulation module 114, a state index register 115, a range register 116, an offset register 117, and an input bit stream 118. The information stored in offset register 101, range register 102, and state index register 103 may be input from the output of register 25 of decoder 20 of FIG. Index register 103 is part of register 35 of FIG. 1 .

The input end of the rLPS look-up table 104, the input end of the MPS look-up table 106 and the input end of the LPS look-up table 105 are coupled to the output end of the state index register 103, and the output end of the state index register 103 outputs the current full-text state (context state) , and the current full-text status can be used to retrieve appropriate values from the rLPS look-up table 104 , the MPS look-up table 106 , and the LPS look-up table 105 . The output end of MPS look-up table 106 is coupled to the first input end of multiplexer 112, the output end of LPS look-up table 105 is coupled to the second input end of multiplexer 112, and the first input end of multiplexer 112 The second input terminal of the multiplexer 112 is used to receive the least probable state output from the LPS look-up table 105 . The input end of the multiplexer 107 is coupled to the output end of the rLPS look-up table 104, the control input end of the multiplexer 107 is coupled to the output end of the range register 102, and the input end of the multiplexer 107 is used to receive the rLPS look-up table 104 For the possible reference states output, the control input terminal of the multiplexer 107 is used to receive the signal output from the range register 102 , and the signal output from the range register 102 is used to control the multiplexer 107 . The output terminal of the multiplexer 107 is coupled to the first input terminal of the adder 108 and the first input terminal of the multiplexer 110 , and the second input terminal of the adder 108 is coupled to the output terminal of the range register 102 . In the adder 108 , the signal from the output of the multiplexer 107 received by the first input of the adder 108 is subtracted from the output signal of the range register 102 received by the second input terminal of the adder 108 . The output terminal of the adder 108 is coupled to the second input terminal of the multiplexer 110 and the first input terminal of the adder 109 , and the second input terminal of the adder 109 is coupled to the output terminal of the offset register 101 . In the adder 109 , the signal from the output of the adder 108 received by the first input terminal of the adder 109 is subtracted from the output signal of the offset register 101 received by the second input terminal of the adder 109 . The first input end of the multiplexer 111 is coupled to the output end of the offset register 101, the second input end of the multiplexer 111 is coupled to the output end of the adder 109, and the first input end of the multiplexer 111 is used for Receiving the signal output by the offset register 101 , the second input end of the multiplexer 111 is used to receive the difference output by the adder 109 .

In addition, the output terminal of the adder 109 is also coupled to the input terminal of the comparison module 113 , and the output terminal of the comparison module 113 is coupled to the control input terminals of the multiplexers 111 , 110 and 112 . The comparison module 113 is used to receive the difference output from the adder 109 and determine whether the difference output from the adder 109 is less than zero. The judgment result output by the comparing module 113 is used to control the multiplexers 111 , 110 and 112 . In addition, the output terminal of the multiplexer 112 is coupled to the input terminal of the state index register 115 , and the signal output by the multiplexer 112 is used to update the state index register 115 .

The first input end of the re-normalization module 114 is used to receive the input bit stream 118, and the second input end of the re-normalization module 114 is coupled to the output end of the multiplexer 111 for receiving the output signal of the multiplexer 111, The third input terminal of the re-normalization module 114 is coupled to the output terminal of the multiplexer 110 for receiving the output signal of the multiplexer 110, and the first output terminal of the re-normalization module 114 is coupled to the offset register 117. The input terminal, the second input terminal of the renormalization module 114 is coupled to the input terminal of the range register 116 , wherein the output signal of the renormalization module 114 is used to update the offset register 117 and the range register 116 in turn. The offset register 117 outputs an update value 119 and the range register 116 outputs an update value 120 . The updated value 119 and the updated value 120 will be used together with the updated state index register 115 in the next decoding cycle.

The bit decoder 300 in FIG. 3 is a schematic diagram of the bit decoder 100 in FIG. 2 including a critical path. In FIG. 3, a bit decoder 300 illustrates how the critical path of a bit decoder that processes one bit per clock (bin-per-cycle) becomes a design issue. As shown in Figure 3, the critical path of the bit decoder 300 that processes one bit (bin-per-cycle) per clock starts from the output end of the state index register 103 and passes through the rLPS look-up table 104, multiplexer 107, adder 108, Adder 109 , comparison module 113 , multiplexer 111 , renormalization module 114 to offset register 117 . The signal output from the range register 102 received by the control input of the multiplexer 107 is used to determine which signal among the multiple signals output from the rLPS look-up table 104 needs to be transmitted to the adder 108 via the multiplexer 107 . In the adder 108 , the signal output from the range register 102 received by the second input end of the adder 108 subtracts the output signal from the multiplexer 107 received by the first input end of the adder 108 . In the adder 109 , the signal from the output of the adder 108 received by the first input terminal of the adder 109 is subtracted from the output signal of the offset register 101 received by the second input terminal of the adder 109 . The input terminal of the comparison module 113 is used to receive the difference output from the adder 109 , and the judgment result of the comparison module 113 is used to control the multiplexer 111 . The signal output by the multiplexer 111 is provided to the renormalization module 114 for updating the offset register 117, and the update value 119 output by the offset register 117 will be used in the next decoding cycle. Thus, the critical path of the bit decoder 300 of FIG. 3 ends at the output of the offset register 117 . However, the processing capability of the bit decoder 300 that processes one bit per clock (bin-per-cycle) is not high enough to be used for real-time decoding of H.264/AVC video, especially when processing high-resolution images, the bit The processing capability of the decoder 300 is even more insufficient.

In order to increase the processing capacity, the bit decoder 400 processing two bits per clock as shown in FIG. 4 can be used to decode two bits per clock instead of one bit per clock. FIG. 4 is a schematic diagram of a bit decoder 400 processing two bits per clock according to an embodiment of the present invention. The bit decoder 400 includes a register 405 , a first decision bit decoder 407 , two multiplexers 415 , 409 and a second decision bit decoder 420 . The register 405 is coupled to the first decision bit decoder 407 and the multiplexer 409 . The first decision bit decoder 407 is coupled to the multiplexer 415 , the multiplexer 409 and the second decision bit decoder 420 . The output of the first decision bit decoder 407 outputs Offset1, Range1 and the RLPS1 signal accompanying the updated state, wherein Offset1 and Range1 are received by the second decision bit decoder 420, but the RLPS signal is accompanied by the external CTX2 RLPS/CTX2 State signal Input to multiplexer 415. The multiplexer 415 is controlled by a Source select signal and outputs the selection result to the second decision bit decoder 420 . The output terminals of the second decision bit decoder 420 output signals Offset2, Range2, RLPS2 and NextST, wherein the signals Offset2, Range2, RLPS2 and NextST output by the second decision bit decoder 420 will be compared with the RLPS1 from the first decision bit decoder 407. The signals are input into the multiplexer 409 together. The output signal from the multiplexer 409 is passed back to the register 405 so that another cycle can begin.

Although, for the high-resolution video of the H.264/AVC standard, a bit decoder processing two bits per clock has acceptable processing power, but its critical path is still a design issue, but after rearranging the decoding process and moving The look-up table to the previous stage can effectively shorten the critical path of the bit decoder which processes two bits per clock. A bit decoder that processes two bits per clock can be implemented according to the architecture of FIG. 5 .

Please refer to Figure 5 and Figure 6 . FIG. 5 illustrates the first decision bit decoder 500 , FIG. 6 illustrates the second decision bit decoder 600 , and the connection relationship between the first decision bit decoder 500 and the second decision bit decoder 600 . In Fig. 5, the first decision bit decoder 500 comprises an offset register 501, a range register 502, an rLPS register 550, a state index register 503, an MPS state look-up table 506, an LPS state look-up table 505, an A first rLPS lookup table 552 , a second rLPS lookup table 555 , multiplexers 515 - 519 , adders 508 - 509 , a state index register 530 , a comparison module 513 and a renormalization module 514 . In Fig. 6, the second decision bit decoder 600 includes a plurality of multiplexers 610, 616, 623, 618, 620, 621, 622, a renormalization module 635, a plurality of adders 641, 643, an rLPS look-up Table 652 , an MPS state lookup table 612 , an LPS state lookup table 611 , a first rLPS lookup table 614 , a second rLPS lookup table 613 , and a comparison module 630 . The input end of the MPS state look-up table 506 and the input end of the LPS state look-up table 505 are coupled to the output end of the state index register 503, and the MPS state look-up table 506 and the LPS state look-up table 505 are in order to receive the present state that the state index register 503 outputs . The input terminal of the first rLPS look-up table 552 and the first input terminal of the multiplexer 515 are coupled to the output terminal of the MPS state look-up table 506 for receiving the most probable state selected by the MPS state look-up table 506 . The first input terminal of the multiplexer 516 is coupled to the output terminal of the first rLPS look-up table 552 for receiving a 32-bit signal output from the first rLPS look-up table 552 . The input end of the second rLPS look-up table 555 and the second input end of the multiplexer 515 are coupled to the output end of the LPS state look-up table 505, in order to receive the least likely state selected by the LPS state look-up table 505, the multiplexer The second input terminal of 516 is coupled to the output terminal of the second rLPS look-up table 555 for receiving a 32-bit signal output by the second rLPS look-up table 555 .

The first input end of the adder 508 and the first input end of the multiplexer 517 are coupled to the output end of the rLPS register 550, the second input end of the adder 508 is coupled to the output end of the range register 502, and the multiplexer 517 The first input end of the adder 508 and the first input end of the adder 508 are used to receive the signal output from the rLPS register 550 , and the second input end of the adder 508 is used to receive the signal output from the range register 502 . In the adder 508, the signal output by the range register 502 will subtract the signal output from the rLPS register 550, and the output end of the adder 508 is coupled to the second input end of the multiplexer 517 and the second input end of the adder 509, The second input end of the adder 509 and the second input end of the multiplexer 517 are used to receive the output signal of the adder 508 . The output terminal of the offset register 501 is coupled to the first input terminal of the adder 509 and the first input terminal of the multiplexer 518, and the first input terminal of the multiplexer 518 and the first input terminal of the adder 509 are used for The signal output by the offset register 501 is received. In the adder 509 , the signal output from the offset register 501 is subtracted from the output signal from the adder 508 . The second input terminal of the multiplexer 518 is coupled to the output terminal of the adder 509 for receiving the difference outputted by the adder 509 . The output terminal of the adder 509 is also coupled to the input terminal of the comparison module 513, the input terminal of the comparison module 513 is used to receive the difference output of the adder 509, and the comparison module 513 determines whether the difference output of the adder 509 is less than zero. The output terminal of the comparison module 513 is coupled to the control input terminals of the multiplexers 518 , 517 , 516 and 515 , wherein the judgment result of the comparison module 113 is used to control the multiplexers 518 , 517 , 516 and 515 .

In addition, the output terminal of the multiplexer 515 is coupled to the input terminal of the state index register 530 , and the signal output by the multiplexer 515 is used to update the state index register 530 . The status index register 530 can output the updated status to the first input terminal of the multiplexer 610 of the second decision bit decoder 600 in turn (as shown in FIG. 6 ). Similarly, the first input end of the multiplexer 519 is coupled to the output end of the multiplexer 516, the second input end of the multiplexer 519 is coupled to another rLPS look-up table, and the multiplexer 519 receives 516 and another rLPS look-up table output signal, will output a 32-bit signal to the first input terminal of the multiplexer 616 of the second decision bit decoder 600 . The first input end of the re-normalization module 514 is used to receive the input bit stream 520, the second input end is used to receive the output signal of the multiplexer 518, the third input end is used to receive the output signal of the multiplexer 517, and then multiple The first input end of the multiplier 623 and the first input end of the adder 641 receive the offset signal output by the first output end of the renormalization module 514, and the second input end of the adder 643 receives the first output end of the renormalization module 514. The range signal output by the two output terminals, the normalization module 635 receives the shifted bit stream (shifted bitstream) output by the third output terminal of the normalization module 514 again, and the control input terminal of the multiplexer 618 receives the normalization module 514 again The 2 most significant bits (Most Significant Bit, MSB) in the range signal output by the second output end of the second output terminal are used as its control signal (as shown in FIG. 6 ).

The second input terminal of the multiplexer 610 and the input terminal of the rLPS look-up table 652 receive a StateIndex2 signal. The second input end of the multiplexer 616 is coupled to the output end of the rLPS look-up table 652 for receiving the output signal of the rLPS look-up table 652 (the first input end of the multiplexer 616 is coupled to the multiplexer 519 for receive the rLPS signal output from the multiplexer 519). The control input terminals of the multiplexer 610 and the multiplexer 616 receive a Stage2_Source_Se1 signal, and the Stage2_Source_Se1 signal is used as a control signal of the multiplexer 610 and the multiplexer 616 .

The input end of the MPS state look-up table 612 and the input end of the LPS state look-up table 611 are coupled to the output end of the multiplexer 610 for receiving signals output from the multiplexer 610 . The input terminal of the first rLPS look-up table 614 and the first input terminal of the multiplexer 620 are coupled to the output terminal of the MPS state look-up table 612 for receiving the most probable state selected by the MPS state look-up table 612 . The first input terminal of the multiplexer 621 is coupled to the output terminal of the first rLPS look-up table 614 for receiving a 32-bit signal output by the first rLPS look-up table 614 . The input end of the second rLPS look-up table 613 and the second input end of the multiplexer 620 are coupled to the output end of the LPS state look-up table 611 for receiving the least probable state selected by the LPS state look-up table 611 . The second input end of the multiplexer 621 is coupled to the output end of the second rLPS look-up table 613 for receiving the 32-bit signal output by the second rLPS look-up table 613 .

The input terminal of the multiplexer 618 is coupled to the output terminal of the multiplexer 616; according to the selection of the Stage2_Source_Se1 signal, the multiplexer 618 will receive a group of 8-bit signals output by the multiplexer 616, and the multiplexer 618 will receive the output from the multiplexer 616. Controlled by the 2 most significant bit signals of the renormalization module 514 , output a set of 8-bit signals to the first input end of the adder 643 and the first input end of the multiplexer 622 . The second input end of the multiplexer 622 and the second input end of the adder 641 are coupled to the output end of the adder 643 . In the adder 643 , the adder 643 subtracts a group of 8-bit signals output from the multiplexer 618 from the range signal output from the renormalization module 514 , and outputs the difference to the multiplexer 622 and the adder 641 . In the adder 641 , the adder 641 subtracts the difference signal output from the adder 643 from the offset signal output from the renormalization module 514 . The second input terminal of the multiplexer 623 is coupled to the output terminal of the adder 641 for receiving the difference outputted by the adder 641 . The output terminal of the adder 641 is also coupled to the input terminal of the comparison module 630 , the input terminal of the comparison module 630 is used to receive the difference output of the adder 641 , and the comparison module 630 determines whether the difference output of the adder 641 is less than zero. The output terminal of the comparison module 630 is coupled to the control input terminals of the multiplexers 623 , 622 , 621 and 620 , wherein the judgment result of the comparison module 630 is used to control the multiplexers 623 , 622 , 621 and 620 . The first input terminal of the renormalization module 635 is used to receive the shifted bit stream from the renormalization module 514 of the first decision bit decoder 500, and the second input terminal is coupled to the output terminal of the multiplexer 623 for Receiving the signal output by the multiplexer 623, the third input terminal is coupled to the output terminal of the multiplexer 622 to receive the signal output by the multiplexer 622, and the first output terminal outputs an offset signal to the first decision bit decoding The offset register 501 and the second output terminal of the device 500 output a range signal to the range register 502 of the first decision bit decoder 500 . And the offset register 501 and the range register 502 will use the offset signal and the range signal from the renormalization module 635 in the next cycle. Similarly, the signal output by the multiplexer 621 is sent to the rLPS register 550 and the signal output by the multiplexer 620 is sent to the state index register 503 for the first decision bit decoder 500 to use in the next cycle.

7 and 8 illustrate the critical path between bit decoder 500 and bit decoder 600 . As shown in Figures 7 and 8, a critical path between the bit decoder 500 and the bit decoder 600 starts from the output end of the range register 502 through the adder 508, and then extends from the output end of the adder 508 to the adder 509, Continue to extend from the output end of the adder 509 to the comparison module 513, then through the output end of the multiplexer 517, then through the output end of the normalization module 514 to the adder 643, continue to extend from the output end of the adder 643 to The adder 641 is connected to the comparison module 630 , and finally, the output signal of the comparison module 630 is used to control the multiplexer 623 to output the offset signal required for the next cycle through the renormalization module 635 .

In summary, compared to conventional designs, the critical path of a bit decoder processing two bits per clock is longer than that of a bit decoder processing one bit per clock. However, the method of rearranging the decoding process and moving the look-up table proposed by the present invention reduces the length of the critical path. The inventive design showed a 33% reduction in time requirements. For example, before the improvement of the present invention, the frequency of the bit decoder that processes two bits per clock is 150MHz (Fujitsu 90nm process), but after adopting the rearrangement decoding process proposed by the present invention, the bit decoder of two bits is processed per clock The frequency of the decoder can be increased to 225MHz.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (12)

1. a binary arithmetic operation decoding device for high operation frequency, comprises;

One first look-up table, has the output that an input is coupled to one first register, in order to receive the signal that this first register exports;

One second look-up table, has the output that an input is coupled to this first register, in order to receive the signal that this first register exports;

One the 3rd look-up table, has the output that an input is coupled to this first look-up table, in order to receive the signal that this first look-up table exports;

One the 4th look-up table, has the output that an input is coupled to this second look-up table, in order to receive the signal that this second look-up table exports;

One first multiplexer, has the output that a first input end is coupled to the 3rd look-up table, and in order to receive the signal that the 3rd look-up table exports, one second input is coupled to the output of the 4th look-up table, in order to receive the signal that the 4th look-up table exports; And

One second multiplexer, has the output that a first input end is coupled to this first look-up table, and in order to receive the signal that this first look-up table exports, one second input is coupled to the output of this second look-up table, in order to receive the signal that this second look-up table exports;

Wherein this first multiplexer and this second multiplexer are all controlled by one first signal.

2. binary arithmetic operation decoding device as claimed in claim 1, also comprise one second register of coupled in series, a first adder, a second adder and one first comparison module, this first comparison module is in order to export this first signal.

3. binary arithmetic operation decoding device as claimed in claim 1, also comprises:

One the 3rd multiplexer, has a first input end is coupled to this second multiplexer output by one the 3rd register, in order to receive the signal that this second multiplexer exports;

One the 5th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports;

One the 6th look-up table, has the output that an input is coupled to the 3rd multiplexer, in order to receive the signal that the 3rd multiplexer exports;

One the 7th look-up table, has the output that an input is coupled to the 5th look-up table, in order to receive the signal that the 5th look-up table exports;

One the 8th look-up table, has the output that an input is coupled to the 6th look-up table, in order to receive the signal that the 6th look-up table exports;

One the 4th multiplexer, has the output that a first input end is coupled to the 7th look-up table, and in order to receive the signal that the 7th look-up table exports, one second input is coupled to the output of the 8th look-up table, in order to receive the signal that the 8th look-up table exports; And

One the 5th multiplexer, has the output that a first input end is coupled to the 5th look-up table, and in order to receive the signal that the 5th look-up table exports, one second input is coupled to the output of the 6th look-up table, in order to receive the signal that the 6th look-up table exports;

Wherein the 4th multiplexer and the 5th multiplexer are all controlled by one second signal.

4. binary arithmetic operation decoding device as claimed in claim 3, wherein the input of this first register is coupled to the output of the 5th multiplexer, in order to store the signal that the 5th multiplexer exports.

5. binary arithmetic operation decoding device as claimed in claim 3, also comprise one the 3rd adder of coupled in series, one the 4th adder and one second comparison module, this second comparison module is in order to export this second signal.

6. binary arithmetic operation decoding device as claimed in claim 5, also comprises:

One the 6th multiplexer, has the output that a first input end is coupled to this first multiplexer, in order to receive the signal that this first multiplexer exports.

7. binary arithmetic operation decoding device as claimed in claim 6, also comprises:

One the 7th multiplexer, has the output that a first input end is coupled to the 6th multiplexer, and in order to receive the signal that the 6th multiplexer exports, one second input is coupled to the output of one the 9th look-up table, in order to receive the signal that the 9th look-up table exports; And

One the 8th multiplexer, has the output that an input is coupled to the 7th multiplexer, the signal that the output in order to receive the 7th multiplexer exports.

8. binary arithmetic operation decoding device as claimed in claim 7, wherein the 3rd multiplexer and the 7th multiplexer are all controlled by one the 3rd signal.

9. binary arithmetic operation decoding device as claimed in claim 7, wherein the first input end of the 3rd adder is coupled to the output of the 8th multiplexer, in order to receive the signal that the 8th multiplexer exports.

10. binary arithmetic operation decoding device as claimed in claim 7, also comprises:

One the 4th register, has an output and is coupled to the first input end of second adder and the first input end of one the 9th multiplexer, and wherein this second adder and the 9th multiplexer are in order to receive the signal of the 4th register output.

11. binary arithmetic operation decoding devices as claimed in claim 10, also comprise:

One the 5th register, has an output and is coupled to the first input end of first adder and the first input end of 1 the tenth multiplexer, and wherein this first adder and the tenth multiplexer are in order to receive the signal of the 5th register output.

12. binary arithmetic operation decoding devices as claimed in claim 11, also comprise:

One ruleization module again, there is a first input end in order to receive an incoming bit stream, one second input is coupled to the output of the 9th multiplexer, in order to receive the signal that the 9th multiplexer exports, one the 3rd input is coupled to the output of the tenth multiplexer, in order to receive the signal that the tenth multiplexer exports, one first output is coupled to the first input end of the 4th adder, one second output is coupled to the second input of the 3rd adder, wherein the first input end of the 4th adder and the second input of the 3rd adder are in order to receive the signal of this rule module output again.