CN102201382B - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same. The semiconductor package has a through hole and includes a chip, a molding compound, a dielectric layer, a first patterned conductive layer, a through hole conductive layer, a second patterned conductive layer and a solder ball. The chip has an active surface, a chip back surface and a chip side surface and comprises a connecting pad. The connecting pad is formed on the active surface. The sealant has a first sealant surface and a corresponding second sealant surface, wherein the pad is exposed from the first sealant surface. And sealing the adhesive and coating the back surface and the side surface of the chip. The dielectric layer is formed on the surface of the first sealing compound and is provided with an opening exposing the through hole. The through hole conductive layer is formed in the through hole. The first patterned conductive layer is formed in the opening. The second patterned conductive layer is formed on the second sealing surface and extends to the through hole conductive layer. The solder balls are formed on the patterned conductive layer on the surface of the second encapsulant.

Description

Semiconductor package and manufacturing method thereof

technical field

The present invention relates to a semiconductor package and its manufacturing method, and more particularly to a semiconductor package with stud bump and its manufacturing method.

Background technique

A traditional stacked semiconductor structure is formed by stacking multiple chips. Each chip has several solder balls, and the solder balls are formed on the chip by reflow. Another solder ball is used between the chips to electrically connect the chips stacked on each other by means of reflow soldering.

However, the chips go through a reflow process before being stacked, and another reflow process when they are stacked together, that is, each chip goes through at least two reflow processes. In this way, the warpage of the chip will be increased due to the high temperature of the reflow process, resulting in severe deformation of the stacked semiconductor structure.

Contents of the invention

The invention relates to a semiconductor package and its manufacturing method. The semiconductor package provides at least one solder ball. The wire bonding ball is formed by wire bonding, and the wire bonding ball is used to connect with a semiconductor component. Since the bonding process of the semiconductor component and the wire balls can be completed by means other than reflow, the deformation of the semiconductor package due to high temperature can be reduced.

According to an aspect of the present invention, a semiconductor package is provided. The semiconductor package includes a chip, sealing glue, a through hole, a first dielectric layer, a first patterned conductive layer, a through hole conductive layer, a second patterned conductive layer and a first wire ball. The chip has a chip side, an active surface opposite to a chip back and includes a first pad, and the first pad is formed on the active surface. The sealant has a first sealant surface and a second sealant surface opposite to each other. The first bonding pad is exposed on the surface of the first sealing glue, and the glue is sealing and covering the back side of the chip and the side surface of the chip. The through hole penetrates from the first sealing surface to the second sealing surface. The first dielectric layer is formed on the surface of the first sealant and has a first opening exposing the through hole. The through-hole conductive layer is formed in the through-hole. The first patterned conductive layer is formed in the first opening and extends to the through-hole conductive layer. The second patterned conductive layer is formed on the surface of the second sealant and extends to the through-hole conductive layer. The first wire balls are formed on the second patterned conductive layer.

According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided. The manufacturing method includes the following steps. Provide a carrier plate with an adhesive layer; arrange several chips on the adhesive layer, each chip has a chip side and an active surface opposite to a chip back and includes a first pad, the first pad Formed on the active surface and facing the adhesive layer; the chip side and the chip back of each chip are covered with a sealant, and the sealant has a first sealant surface and a second sealant surface opposite; several through-holes are formed The hole is in the sealant, and the through hole penetrates from the first sealant surface to the second sealant surface; the carrier board and the adhesive layer are removed, so that the first sealant surface exposes the first pad of the chip; a first dielectric Layered on the surface of the first sealing glue, the first dielectric layer has several first openings, and the first openings expose the through holes; a through hole conductive layer is formed in the through holes; a first pattern is formed The conductive layer is in the first opening and extends to the through-hole conductive layer; a second patterned conductive layer is formed on the surface of the second sealant and extends to the through-hole conductive layer; a first solder ball is formed by wire bonding technology patterning the second conductive layer; and cutting the encapsulant to separate the chips.

In order to make the above-mentioned content of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of a semiconductor package according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 3 is a flow chart showing the manufacturing process of the semiconductor package according to the first embodiment of the present invention.

4A to 4F are schematic diagrams illustrating the manufacturing of the semiconductor package shown in FIG. 1 .

FIG. 5 is a schematic diagram of a semiconductor device according to a second embodiment of the present invention.

Description of main component symbols:

100, 200: semiconductor package

102: chip

104: Sealant

106: first dielectric layer

110: second dielectric layer

112: tin ball

114: The first wire ball

116: twisting part

118, 318: Semiconductor components

120: Second pad

122: First pad

124: through hole

126: The first sealing surface

128: Second sealing surface

130: first opening

132: chip protection layer

134: Second opening

136: the first patterned conductive layer

138: second patterned conductive layer

140: Paste layer

142: carrier board

144: active surface

146, 148, 150: side

152: Through-hole conductive layer

154: pad protection layer

156: Chip back

158: chip side

352: Second welding wire ball

S102-S126: Steps

Detailed ways

The following preferred embodiments are proposed as an illustration of the present invention, but the contents of the embodiments are only for illustration purposes, and the drawn drawings are for illustration purposes, and are not used to limit the protection scope of the present invention. Furthermore, the illustrations of the embodiments also omit unnecessary components to clearly show the technical characteristics of the present invention.

first embodiment

Please refer to FIG. 1 , which shows a schematic diagram of a semiconductor package according to a first embodiment of the present invention. The semiconductor package 100 has a through hole 124 and includes a chip 102, an encapsulant 104, a first dielectric layer 106, a first patterned conductive layer 136, a through hole conductive layer 152, a second patterned conductive layer 138, a second dielectric layer 110 , a plurality of solder balls 112 and a plurality of first solder balls 114 .

The sealant 104 has a first sealant surface 126 and a second sealant surface 128 opposite to each other.

The second patterned conductive layer 138 is formed on the second encapsulation surface 128 , and the first wire bonding balls 114 can be formed on the second patterned conductive layer 138 . The position of the first wire ball 114 can overlap with the through hole 124 , as shown by the first wire ball 114 on the left in FIG. 1 . Alternatively, the position of the first wire ball 114 can also be staggered by a distance from the through hole 124 along the extending direction of the second sealing surface 128 , as shown by the first wire ball 114 on the right in FIG. 1 .

The first bonding wire ball 114 is formed by wire bonding technology, so the first bonding wire ball 114 has a protruding twisted portion 116 , which is the shape formed after the bonding wire is twisted by the bonding tool head.

Please refer to FIG. 2 , which shows a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 200 further includes a semiconductor component 118 , where the semiconductor component 118 may be a chip or another semiconductor package. The semiconductor device 118 includes a plurality of second pads 120 .

In this embodiment, the second pad 120 of the semiconductor device 118 can be bonded to the first wire ball 114 by a bonding process other than reflow to form the stacked semiconductor package 200 . The aforementioned bonding process is, for example, an ultrasonic bonding (ultrasonic bonding) technology.

The material of the first wire ball 114 may be metal, such as a combination of at least one of gold (Au), aluminum (Al) and copper (Cu). However, this is not intended to limit the present invention, and the material of the first wire ball 114 may also be composed of other conductive materials. When the material of the first wire ball 114 is gold, since the texture of gold is relatively soft, the combination of the first wire ball 114 and the second pad 120 of the semiconductor component 118 is facilitated under the use of ultrasonic bonding technology. .

Since the semiconductor component 118 is bonded to the first wire ball 114 by a bonding process other than reflow, the number of times the semiconductor package 200 is subjected to high temperature processes can be reduced, and the amount of deformation of the semiconductor package 200 can be greatly reduced.

In addition, the second pad 120 of the semiconductor device 118 may include a pad protection layer 154 formed on the outermost layer of the second pad 120 by electroplating or sputtering to connect with the first wire ball 114. . The pad protection layer 154 can not only prevent the oxidation damage of the second pad 120 , but also improve the bonding between the second pad 120 and the first wire ball 114 . The pad protection layer 154 may be composed of a nickel (Ni) layer and a gold (Au) layer. Alternatively, the pad protection layer 154 may be composed of a nickel layer, a palladium (Pa) layer, and a gold layer, wherein the gold layer of the pad protection layer 154 may be formed on the outermost layer of the second pad 120 to connect with the first bonding wire. The ball 114 is connected.

Please return to FIG. 1 , the chip 102 has a chip side 158 , an opposite active surface 144 and a chip back 156 and includes a plurality of first pads 122 and a chip protection layer 132 . The first pads 122 and the chip protection layer 132 are formed on the active surface 144 of the chip 102 . The chip side 158 connects the active surface 144 and the chip back 156 , the chip protection layer 132 exposes the first pads 122 , and the encapsulant 104 covers the chip back 156 and the chip side 158 of the chip 102 and exposes the first pads 122 .

The first dielectric layer 106 is formed on the first sealing surface 126 and has a plurality of first openings 130 , and the first openings 130 expose the through holes 124 and the first pads 122 correspondingly.

The first patterned conductive layer 136 is formed on the first dielectric layer 106 and inside the first openings 130 . The through hole conductive layer 152 is formed in the through hole 124 . The through-hole conductive layer 152 can be a thin layer formed on the inner sidewall of the through-hole 124 ; or, the through-hole conductive layer 152 can also be a conductive column that fills the entire through-hole 124 .

The second patterned conductive layer 138 is formed on the second sealing surface 128 and extends to the through-hole conductive layer 152 , so that the second patterned conductive layer 138 can be electrically connected to the first patterned conductive layer 136 through the through-hole conductive layer 152 .

The second dielectric layer 110 is formed on the first patterned conductive layer 136 and has a plurality of second openings 134 . The second opening 134 exposes a portion of the through-hole conductive layer 152 and the first patterned conductive layer 136 .

The solder balls 112 are correspondingly formed in the second openings 134 to be electrically connected to the through-hole conductive layer 152 and the first pad 122 . The solder balls 112 are used to electrically connect to an external circuit, such as a circuit board (PCB), a chip or another semiconductor package.

The manufacturing method of the semiconductor package 100 of FIG. 1 will be described below with reference to FIG. 3 together with FIGS. 4A to 4F . FIG. 3 is a flow chart of manufacturing the semiconductor package according to the first embodiment of the present invention, and FIGS. 4A to 4F are schematic views of manufacturing the semiconductor package of FIG. 1 .

In step S102 , a carrier 142 with an adhesive layer 140 as shown in FIG. 4A is provided.

Next, in step S104 , as shown in FIG. 4A , several chips 102 are disposed on the adhesive layer 140 . The first pad 122 of each chip 102 faces the adhesive layer 140 . In order not to complicate the illustration, only a single chip 102 is shown in FIG. 4A .

The chips 102 can be redistributed on the adhesive layer 140 after the circuits are fabricated on the wafer and cut and separated.

Next, in step S106 , as shown in FIG. 4B , the sealant 104 is coated by encapsulation technology to cover the chip side 158 and the chip back 156 of the chip 102 , so that the sealant 104 and the chip 102 form an encapsulant. Wherein, the first sealing surface 126 is substantially flush with the active surface 144 .

The sealant 104 may include Novolac-based resin, epoxy-based resin, silicone-based resin or other suitable coating agents. The sealant 104 may also include a suitable filler, such as powdered silicon dioxide.

In addition, the packaging technology mentioned above is, for example, compression molding, injection molding or transfer molding.

The encapsulation process of this embodiment takes the redistributed chips 102 as a whole as the encapsulation object. Therefore, the process of this embodiment redistributes the encapsulant level package (Chip-redistribution Encapsulant Level Package) of the chip, which can make the manufactured semiconductor Packages are listed as Chip Scale Package (CSP) or Wafer Level Package (WLP) levels.

In addition, the redistributed chips 102 can be separated by an appropriate distance, so that solder balls can be formed between two adjacent chips 102, that is, solder balls 112 between the chip side 158 and the side 146 of the encapsulant 104, such as Figure 1 shows. In this way, the diced semiconductor package 100 can become a fan-out semiconductor package.

Then, in step S108 , as shown in FIG. 4C , laser or mechanical drilling techniques are used to form the through holes 124 . The through hole 124 penetrates from the first sealing surface 126 to the second sealing surface 128 .

Then, in step S110 , as shown in FIG. 4D , the carrier 142 and the adhesive layer 140 are removed. After the carrier 142 and the adhesive layer 140 are removed, the first bonding pad 122 and the chip protection layer 132 are exposed on the first sealing surface 126 of the sealing compound 104 .

After the step S110 , the above-mentioned sealing body can be inverted (invert), so that the first sealing surface 126 faces upward, as shown in FIG. 4E .

Then, in step S112, as shown in FIG. 4E , a dielectric material is formed to cover the first sealing surface 126, the chip protection layer 132 and the first pad 122 by applying a technique of application, and then the patterning is applied. The first opening 130 exposing the through holes 124 and the first contact pads 122 is formed on the dielectric material to form the first dielectric layer 106 .

The above-mentioned coating technique is for example printing (printing), spin-coating (spinning) or spraying (spraying), and the above-mentioned patterning technique is for example photolithography (photolithography), chemical etching (chemical etching), laser drilling (laser drilling) , mechanical drilling or laser cutting.

Then, in step S114, a conductive material is first formed to fill in the through hole 124 and cover the first dielectric layer 106 (the first dielectric layer 106 is shown in FIG. 4E ) and the second sealing surface 128 (the second sealing surface 128 After the adhesive surface 128 is shown in FIG. 4F ), the conductive material is patterned using a patterning technique to form a first patterned conductive layer 136 and a second patterned conductive layer 138 as shown in FIG. 4F .

The techniques for forming the conductive material are, for example, chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spray coating, sputtering or vacuum deposition.

The conductive material formed on the first dielectric layer 106 is patterned into a first patterned conductive layer 136, and the first patterned conductive layer 136 is formed on the first dielectric layer 106 and the first openings 130 (first The opening 130 is shown in FIG. 4E ) and extends to contact the through-hole conductive layer 152 , and the conductive material filled in the through-hole 124 forms the through-hole conductive layer 152 . The conductive material formed on the second encapsulant surface 128 is patterned into a second patterned conductive layer 138 , and the second patterned conductive layer 138 extends to contact with the via conductive layer 152 .

In this step S114 , the first patterned conductive layer 136 , the through-hole conductive layer 152 and the second patterned conductive layer 138 are formed simultaneously. However, this is not intended to limit the present invention, and in other implementation aspects, the first patterned conductive layer 136 , the through-hole conductive layer 152 and the second patterned conductive layer 138 can also be completed by different process technologies with the same or different materials.

Then, in step S116 , the above-mentioned coating technique combined with the above-mentioned patterning technique is used to form the second dielectric layer 110 as shown in FIG. 4F on the first patterned conductive layer 136 . The second dielectric layer 110 has a plurality of second openings 134, some of the second openings 134 correspondingly expose the through-hole conductive layer 152, and other second openings 134 expose a part of the first patterned conductive layer 136 . The position of the second opening 134 in FIG. 4F corresponds to the position of the first pad 122 , but this is not intended to limit the present invention. In other implementation aspects, the second opening 134 may also be staggered by a distance from the first pad 122 along the extending direction of the second dielectric layer 110 .

Since the first dielectric layer 106, the first patterned conductive layer 136, the through-hole conductive layer 152, the second patterned conductive layer 138, and the second dielectric layer 112 are formed after the chip 102 is redistributed, the first dielectric layer The electrical layer 106 , the first patterned conductive layer 136 , the through-hole conductive layer 152 , the second patterned conductive layer 138 and the second dielectric layer 112 are redistributed layers (Redistributed layer, RDL).

Then, in step S118 , a plurality of solder balls 112 as shown in FIG. 4F are formed in the second openings 134 to be electrically connected to the first patterned conductive layer 136 .

After step S118 , the molding body shown in FIG. 4F can be turned upside down so that the second molding surface 128 faces upward.

Then, in step S120 , a plurality of first wire bonding balls 114 as shown in FIG. 1 are formed on the second patterned conductive layer 138 by wire bonding technology (the second patterned conductive layer 138 is shown in FIG. 1 ). So far, a package structure is formed.

In one implementation aspect, depending on the operation mode of the wire bonding machine, the inversion of step S118 is omitted.

Then, in step S122 , the package structure is cut to separate the chips 102 . So far, the semiconductor package 100 shown in FIG. 1 is formed.

As shown in FIG. 1 , since the cutting path passes through the overlapped sealant 104 , the first dielectric layer 106 and the second dielectric layer 110 , the side 146 of the sealant 104 , the second dielectric layer 110 in the cut semiconductor package 100 The side 148 of the first dielectric layer 106 is substantially aligned with the side 150 of the second dielectric layer 110 . Wherein, the side surface 146 of the sealant 104 connects the opposite first sealant surface 126 and the second sealant surface 128 .

Then, in step S124, the semiconductor device 118 is provided.

Then, in step S126 , the first wire ball 114 and the second pad 120 are butt-bonded by ultrasonic bonding technology, so that the semiconductor component 118 is stacked on the first wire ball 114 . So far, the stacked semiconductor package 200 shown in FIG. 2 is formed.

second embodiment

Please refer to FIG. 5 , which shows a schematic diagram of a semiconductor device according to a second embodiment of the present invention. The parts in the second embodiment that are the same as those in the first embodiment use the same reference numerals, which will not be repeated here. The difference between the semiconductor component 318 of the second embodiment and the aforementioned semiconductor component 118 is that the semiconductor component 318 further includes a plurality of second wire bonding balls 352 .

The technical features of the second wire ball 352 are similar to those of the first wire ball 114 , and will not be repeated here.

Similar to the manufacturing method of the semiconductor package 200 in the first embodiment, ultrasonic bonding technology can be used to butt the first wire bonding ball 114 in FIG. The components 318 are stacked on the first wire balls 114 to form a stacked semiconductor package similar to that shown in FIG. 2 .

In another embodiment, the semiconductor device 318 can also be a semiconductor package having a structure similar to that of the semiconductor package 100 . Furthermore, the two semiconductor packages 100 can be butted via ultrasonic bonding technology.

In the semiconductor package and its manufacturing method disclosed in the above embodiments of the present invention, the semiconductor package has a wire bonding ball formed by a wire bonding technique, and the bonding wire ball can be bonded with a semiconductor component to form a stack structure. Since the bonding process between the semiconductor component and the wire balls can be done in a way other than reflow, the deformation of the semiconductor package due to high temperature can be reduced.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (14)

1. semiconductor package part comprises:

One chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and this first connection pad is formed on this active surface;

One sealing has the surperficial and corresponding one second sealing surface of one first sealing, and this first connection pad is exposed on this first sealing surface, and this sealing also coats this chip back and this chip sides;

One perforation is through to this second sealing surface from this first sealing surface;

One first dielectric layer is formed at this first sealing surface and has one first perforate of exposing this perforation;

One perforation conductive layer is formed in this perforation;

One first patterned conductive layer is formed in this first perforate and extends to this perforation conductive layer;

One second patterned conductive layer is formed at this second sealing surface and extends to this perforation conductive layer; And

One first bonding wire ball is formed at and is positioned at this second patterned conductive layer.

2. semiconductor package part as claimed in claim 1, wherein the material of this first bonding wire ball is metal.

3. semiconductor package part as claimed in claim 1 more comprises:

The semiconductor assembly comprises one second connection pad, and this semiconductor subassembly is stacked on this first bonding wire ball and by this second connection pad and is electrically connected at this first bonding wire ball.

4. semiconductor package part as claimed in claim 1 more comprises:

The semiconductor assembly comprises one second bonding wire ball, and this semiconductor subassembly is stacked on this first bonding wire ball and by this second bonding wire ball and is electrically connected at this first bonding wire ball.

5. semiconductor package part as claimed in claim 1, wherein this chip more comprises a chip protection layer, and this chip protection layer is formed at this active surface and exposes this first connection pad, and this semiconductor package part more comprises:

One second dielectric layer is formed on this first patterned conductive layer and has one second perforate, this second perforate

Expose this perforation conductive layer; And

One tin ball is formed at this second perforate to be electrically connected at this perforation conductive layer.

6. semiconductor package part as claimed in claim 5, wherein the side of the side of a side of this sealing, this first dielectric layer and this second dielectric layer trims;

Wherein, this side of this sealing connects this first sealing surface and this second sealing surface.

7. the manufacture method of a semiconductor package part comprises:

Support plate with an adhesive layer is provided;

Several chips are set on this adhesive layer, each those chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and this first connection pad is formed on this active surface and towards this adhesive layer;

With this chip sides and this chip back of each those chip of a sealant covers, this sealing has relative one first sealing surface and one second sealing surface;

Form several perforations in this sealing, those perforations are through to this second sealing surface from this first sealing surface;

Remove this support plate and this adhesive layer, make this first sealing surface expose those first connection pads of those chips;

Form one first dielectric layer in this first sealing surface, this first dielectric layer has several the first perforates, and those perforations are exposed in those first perforates;

Form a perforation conductive layer in those perforations;

Form one first patterned conductive layer in those first perforates and extend to this perforation conductive layer;

Form one second patterned conductive layer in this second sealing surface and extend to this perforation conductive layer;

Form several the first bonding wire balls in being positioned at this second patterned conductive layer with the routing technology; And

Cut this sealing, to separate those chips.

8. manufacture method as claimed in claim 7, wherein the material of each those the first bonding wire ball is metal.

9. manufacture method as claimed in claim 7 more comprises:

The semiconductor assembly is provided, and this semiconductor subassembly comprises several the second connection pads; And

Dock those the first bonding wire balls and those the second connection pads, so that this semiconductor subassembly is stacked on those the first bonding wire balls.

10. manufacture method as claimed in claim 9 wherein more comprises in this step of those the first bonding wire balls of docking and those the second connection pads:

With the ultrasonic waves joining technique, dock those the first bonding wire balls and those the second connection pads.

11. manufacture method as claimed in claim 7 wherein more comprises:

The semiconductor assembly is provided, and this semiconductor subassembly comprises several the second bonding wire balls; And

Dock those the first bonding wire balls and those the second bonding wire balls, so that this semiconductor subassembly is stacked on those the first bonding wire balls.

12. the manufacture method as claim 11 is stated wherein more comprises in this step of those the first bonding wire balls of docking and those the second bonding wire balls:

With the ultrasonic waves joining technique, dock those the first bonding wire balls and those the second bonding wire balls.

13. such as the manufacture method that claim 7 is stated, wherein each those chip more comprises a chip protection layer, this chip protection layer is formed at this active surface and exposes this first connection pad, and this manufacture method more comprises:

Form one second dielectric layer in this first patterned conductive layer, this second dielectric layer has several the second perforates, and this perforation conductive layer is exposed in those second perforates; And

Form several tin balls in those the second perforates, to be electrically connected at this perforation conductive layer.

14. manufacture method as claimed in claim 13 wherein more comprises in this step of this sealing of cutting:

Cut this sealing along a cutting path, this cutting path this sealing, this first dielectric layer and this second dielectric layer through overlapping trims a side, the side of this first dielectric layer and the side of this second dielectric layer of this sealing after the cutting;

Wherein, this side of this sealing connects this first sealing surface and this second sealing surface.

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