CN102195740B

CN102195740B - Method and device for performing simplified decoding checking by low density parity check codes

Info

Publication number: CN102195740B
Application number: CN 201010118506
Authority: CN
Inventors: 张小军; 田应洪; 崔建明; 余磊; 李宝将; 刘静; 赖宗声
Original assignee: East China Normal University
Current assignee: East China Normal University
Priority date: 2010-03-05
Filing date: 2010-03-05
Publication date: 2013-06-19
Anticipated expiration: 2030-03-05
Also published as: CN102195740A

Abstract

The invention relates to a simplified checking method and device of a low-density parity check code, belonging to the technical field of communication. The present invention does not need a check matrix when checking. In the low signal-to-noise area, set different iteration thresholds according to different signal-to-noise ratios, and in the high-signal-to-noise area, set the threshold of the number of sub-rows whose sign bits of the information bits are continuous before and after the update of the sub-rows. When this threshold is exceeded, iterative decoding will end. Compared with the traditional parity check matrix method, the present invention does not use a parity check matrix, which greatly reduces the calculation amount of each parity calculation, reduces the bandwidth requirement of the memory, thereby reduces hardware overhead, saves power consumption, and reduces area.

Description

Simplified decoding and verification method and device for low-density parity-check codes

技术领域technical field

本发明涉及通信领域中的前向纠错技术，特别涉及低密度奇偶校验码的译码校验方法和装置。The invention relates to forward error correction technology in the field of communication, in particular to a method and device for decoding and checking low-density parity check codes.

背景技术Background technique

低密度奇偶校验码(LDPC)是由Gallager于1962年首先提出的一种纠错码。低密度奇偶校验码的主要思想是用低密度校验矩阵表示分组码，以便降低分组码编译码的复杂性，并且可使用迭代译码算法，从而使得码长的限制放宽，可以使用长码来逼近Shannon信道容量。非正则LDPC码的性能不仅优于正则LDPC码，甚至还优于Turbo码，是目前已知的最接近香农限的码，已经公布的最好的性能与香农限仅相差0.0045dB。由于其良好的编码性能、易于进行理论分析和研究，译码简单且可实行并行操作，适合硬件实现等优点，目前在多种通信系统中被采用。例如中国数字电视地面广播标准(DMB-TH)、DVB-S2、802.11n、WIMAX等标准都采用了LDPC码。Low-density parity-check code (LDPC) is an error-correcting code first proposed by Gallager in 1962. The main idea of the low-density parity-check code is to use the low-density parity-check matrix to represent the block code, so as to reduce the complexity of block code coding and decoding, and iterative decoding algorithm can be used, so that the code length limit can be relaxed, and long codes can be used to approach the Shannon channel capacity. The performance of non-regular LDPC codes is not only better than regular LDPC codes, but also better than Turbo codes. It is the code closest to the Shannon limit known so far, and the best performance that has been published is only 0.0045dB away from the Shannon limit. Because of its good encoding performance, easy theoretical analysis and research, simple decoding and parallel operation, suitable for hardware implementation, etc., it is currently used in many communication systems. For example, China's Digital TV Terrestrial Broadcasting Standard (DMB-TH), DVB-S2, 802.11n, WIMAX and other standards all use LDPC codes.

LDPC码属于线性分组码。LDPC码可通过校验矩阵来表示，该校验矩阵的行的大小为N，列的大小为M，码率R＝(N-M)/N。校验矩阵中每行中所含“1”的个数叫做行重，每列中所含“1”的个数叫做列重。规则LDPC码是指校验矩阵中所有的行重都相等，所有的列重也相等。非规则LDPC码与规则LDPC码相似，但是校验矩阵中所有的行中存在行重和其他行重不同的行，或者所有的列中存在列重与其他列重不同的列。如图1所示，码率R＝(7-4)/7＝3/7，第一行的行重为3，第一列的列重位2，由于第三行的行重为2，而其他行的行重为3，所以此LDPC码为非规则码。校验矩阵是一种稀疏矩阵，矩阵中“1”的个数非常稀少，例如DMB-TH标准中0.4码率的校验矩阵中“1”的密度仅为0.001。本发明主要与LDPC码的译码相关，下面介绍LDPC码的译码算法。LDPC codes are linear block codes. The LDPC code can be represented by a parity check matrix, the size of the rows of the parity check matrix is N, the size of the columns is M, and the code rate R=(N-M)/N. The number of "1" contained in each row of the parity check matrix is called the row weight, and the number of "1" contained in each column is called the column weight. The regular LDPC code means that all row weights in the parity check matrix are equal, and all column weights are also equal. The irregular LDPC code is similar to the regular LDPC code, but all the rows in the parity check matrix have rows with different weights from other rows, or all columns have columns with different weights from other columns. As shown in Figure 1, code rate R=(7-4)/7=3/7, the row weight of the first row is 3, the column weight of the first column is 2, because the row weight of the 3rd row is 2, And the line weight of other lines is 3, so this LDPC code is an irregular code. The parity check matrix is a kind of sparse matrix, and the number of "1" in the matrix is very rare. For example, the density of "1" in the parity check matrix with a code rate of 0.4 in the DMB-TH standard is only 0.001. The present invention is mainly related to the decoding of LDPC codes, and the decoding algorithm of LDPC codes is introduced below.

目前，研究人员已提出多种基于置信传递的译码算法，算法原理相似，其主要的区别在于传递的信息。主要的译码算法有置信传递(BP)算法、MPC Fossorier等人提出的最小和算法和美国伊利诺伊州大学Mansour，M.M.和Shanbhag，N.R.提出的TDMP算法。由于TDMP算法加快迭代速度，减少译码延时，美国伊利诺伊州大学Mansour，M.M.和Shanbhag，N.R.提出TDMP算法。TDMP算法不但计算量小，且节省数据存储量，这有利于减小LDPC译码器面积、降低功耗。At present, researchers have proposed a variety of decoding algorithms based on belief transfer. The algorithm principles are similar, and the main difference lies in the information transferred. The main decoding algorithms include the Belief Propagation (BP) algorithm, the minimum sum algorithm proposed by MPC Fossorier et al., and the TDMP algorithm proposed by Mansour, M.M. and Shanbhag, N.R. of the University of Illinois, USA. Because the TDMP algorithm accelerates the iteration speed and reduces the decoding delay, Mansour, M.M. and Shanbhag, N.R. of the University of Illinois in the United States proposed the TDMP algorithm. The TDMP algorithm not only has a small amount of calculation, but also saves data storage, which is conducive to reducing the area of the LDPC decoder and reducing power consumption.

为了便于理解本发明，下面对TDMP算法进行简短的数学描述。In order to facilitate the understanding of the present invention, a brief mathematical description of the TDMP algorithm is given below.

该算法主要针对校验矩阵符合AA架构的非规则LDPC码。所谓AA架构是指这个校验矩阵可分为S1×S2个子矩阵，即校验矩阵分为S1行，每行又分为S2列，分解后的每个子矩阵中每行和每列中“1”个数不会超过1。在本发明中，所谓的子行是指校验矩阵被分成的S1行；所谓的子矩阵是指每个子行又被分解成的S2列。如图2所示，矩阵分为S1＝4个子行，每个子行又可以分为S2＝8个子列，一共分为了S1×S2＝32个子矩阵，每个子矩阵为3×3矩阵。该算法的校验和信息节点的更新采用最小和算法，基本流程如下：This algorithm is mainly aimed at irregular LDPC codes whose parity check matrix complies with the AA structure. The so-called AA architecture means that the check matrix can be divided into S1×S2 sub-matrices, that is, the check matrix is divided into S1 rows, and each row is divided into S2 columns. In each row and column of each sub-matrix after decomposition, "1 "The number will not exceed 1. In the present invention, the so-called sub-rows refer to the S1 rows into which the check matrix is divided; the so-called sub-matrices refer to the S2 columns into which each sub-row is decomposed. As shown in Fig. 2, the matrix is divided into S1=4 sub-rows, and each sub-row can be divided into S2=8 sub-columns, and is divided into S1×S2=32 sub-matrices in total, and each sub-matrix is a 3×3 matrix. The update of the checksum and information nodes of this algorithm adopts the minimum sum algorithm, and the basic process is as follows:

(a)信息初始化。初始化变量节点信息Lq_v为初始信道信息，初始化校验节点信息R_cv为零。(a) Information initialization. The initial variable node information Lq _v is the initial channel information, and the initial check node information R _cv is zero.

(b)信息迭代计算。R_cv为当前子矩阵行计算时校验节点c向变量节点v传递的信息。R′_cv为上一次子行计算时校验节点c向变量节点v传递的信息。N(c)/v表示与校验节点c相连的除了变量节点v外的其余变量节点的集合。N(v)表示与校验节点c相连的所有变量节点的集合。Lq′_v表示上一次子行计算时与变量节点v相连的除了校验节点c外其余校验节点的集合。Lq_v表示当前子行中与变量节点v相连的所有校验节点的信息和。等式(1)和(2)的计算基于子行进行，完成校验节点信息的更新。每个子行的校验节点信息计算完成后，根据等式(3)，完成变量节点信息的更新。(b) Information iterative calculation. R _cv is the information transmitted from the check node c to the variable node v during the calculation of the current sub-matrix row. _R'cv is the information transmitted from the check node c to the variable node v during the last sub-row calculation. N(c)/v represents the set of other variable nodes connected to check node c except variable node v. N(v) represents the set of all variable nodes connected to check node c. _Lq'v represents the set of other check nodes connected to variable node v except check node c during the last subrow calculation. Lq _v represents the information sum of all check nodes connected to variable node v in the current sub-row. The calculations of equations (1) and (2) are performed based on sub-rows to complete the update of check node information. After the calculation of the check node information of each sub-row is completed, according to the equation (3), the update of the variable node information is completed.

Lq′_v＝Lq_v-R′_cv (1) _Lq′v ＝Lqv _- _R′cv (1)

${R R}_{cv cv} = = \underset{v v &Element; &Element; N N ((c c)) / / v v}{\prod \prod} Sign sign ((L L {q q}^{' '}_{v v})) \underset{v v &Element; &Element; N N ((c c)) / / v v}{Min Min} ((| | L L {q q}^{' '}_{v v} | |)) - - - - - - ((22))$

${Lq}_{v} = \underset{m &Element; (v)}{Σ} R_{cv}$ $Q_{v} = \underset{m &Element; (v)}{Σ} R_{cv}$

$= = {Lq Q}^{' '}_{v v} + + {R R}_{cv cv}$

(c)译码校验。一个子矩阵行的Lq_v计算完成后，根据Lq_v译出码字，Lq_v＜0则码字比特C(v)＝1，否则C(v)＝0，如等式(4)所示。然后根据校验矩阵H进行校验，校验计算如等式(5)，即计算码字比特与H矩阵每行的内积。函数mod(x，2)表示x模2运算。内积模2为0，则该行校验成功。如果H矩阵所有行都校验成功，则判定码字是正确的，译码成功标志位F为1，终止(a)步信息迭代计算。否则继续(b)步和(c)步。当达到最大迭代次数时，不管译码成功与否，强行退出整个迭代过程。(c) Decoding verification. After the calculation of Lq _v of a sub-matrix row is completed, the code word is decoded according to Lq _v , if Lq _v <0, the code word bit C(v)=1, otherwise C(v)=0, as shown in equation (4) . Then check is performed according to the check matrix H, and the check calculation is as in equation (5), that is, the inner product of the codeword bits and each row of the H matrix is calculated. The function mod(x, 2) represents x modulo 2 operation. If the inner product modulo 2 is 0, the verification of this line is successful. If all rows of the H matrix are verified successfully, it is determined that the codeword is correct, and the successful decoding flag F is 1, and the iterative calculation of information in step (a) is terminated. Otherwise, continue with steps (b) and (c). When the maximum number of iterations is reached, regardless of whether the decoding is successful or not, the entire iterative process is forcibly exited.

$C C ((v v)) = = \{\begin{matrix} 11 & L L {q q}_{v v} < < 00 \\ 00 & L L {q q}_{v v} &GreaterEqual; &Greater Equal; 00 \end{matrix} - - - - - - ((44))$

$F f = = (({Σ Σ}_{m m = = 11}^{M m} mod mod (({Σ Σ}_{n no = = 11}^{N N} C C ((v v)) \times \times H h ((m m,, n no)),, 22)) = = = = 00)) - - - - - - ((55))$

TDMP算法流程中，每一子行校验节点信息计算完成后，新的校验节点信息值被代入变量节点的更新中，提高了译码速度。数据吞吐率较典型最小和算法提高了一倍。同时，由于不需保存初始信道信息和变量节点信息Lq′_n，大大节省了存储器，减少了芯片面积，降低了功耗。In the TDMP algorithm flow, after the calculation of the check node information of each sub-row is completed, the new check node information value is substituted into the update of the variable node, which improves the decoding speed. The data throughput rate is doubled compared with the typical min-sum algorithm. At the same time, since the initial channel information and the variable node information Lq' _n do not need to be stored, the memory is greatly saved, the chip area is reduced, and the power consumption is reduced.

但在该算法流程中，由于每计算完一个子行的校验节点信息和变量节点信息后，都需要对译出的码字进行校验，因此产生了校验计算有效性问题。从公式(5)可以看出，当进行迭代判断时，需要进行矩阵的乘法，这就引入了复杂的计算，不仅要求增加逻辑电路以提高校验计算硬件的并行处理能力，并且要求存储器(特别是校验矩阵存储器)能提供足够高的带宽，而后一点难以达到或需要的代价很高。因此，有必要研究更好的迭代终止方法来解决这一问题。However, in the algorithm flow, since the decoded codewords need to be verified after each calculation of the check node information and variable node information of a sub-row is completed, the validity of the check calculation occurs. It can be seen from formula (5) that when iterative judgment is performed, matrix multiplication is required, which introduces complex calculations, which not only requires the addition of logic circuits to improve the parallel processing capability of the verification calculation hardware, but also requires memory (especially is check matrix memory) can provide a sufficiently high bandwidth, and the latter point is difficult to achieve or requires a high cost. Therefore, it is necessary to study better iteration termination methods to solve this problem.

发明内容Contents of the invention

本发明的目的是提供一种LDPC校验方法和装置，以克服现有校验技术的不足。本发明主要是针对符合AA架构的校验矩阵。矩阵中该校验方法在一次校验计算时不需要对校验矩阵进行操作，仅对每次更新前后的符号位的改变进行计算。这大大降低了计算量、减少了硬件消耗，能够更好地满足系统功耗、面积和速度要求。The purpose of the present invention is to provide an LDPC verification method and device to overcome the deficiencies of the existing verification technology. The present invention is mainly aimed at the parity check matrix conforming to the AA framework. The check method in the matrix does not need to operate the check matrix during a check calculation, but only calculates the change of the sign bit before and after each update. This greatly reduces the amount of calculation, reduces hardware consumption, and can better meet system power consumption, area and speed requirements.

本发明提供了一种低密度奇偶校验码的校验方法，该方法包括阈值表的设置、低信噪区码字校验、高信噪区码字校验和校验结果输出四个步骤，其中，首先根据仿真设置一个阈值表，迭代译码时，根据输入码字的码率和信噪比从阈值表中得到相应的阈值；在迭代的过程中，高信噪区码字校验和低信噪区码字校验分别根据阈值进行判断并输出校验标志；校验结果根据阈值表中得到的标志位选择高信噪区还是低信噪区的校验标志，并输出译码终止标志；当译码终止标志为1时，停止迭代。The invention provides a method for verifying low-density parity-check codes. The method includes four steps: setting a threshold table, verifying code words in low-signal-noise areas, verifying code words in high-signal-noise areas, and outputting verification results. , where, firstly, a threshold table is set according to the simulation, and the corresponding threshold is obtained from the threshold table according to the code rate and signal-to-noise ratio of the input codeword during iterative decoding; and low signal-noise area code word verification respectively according to the threshold and output the verification mark; the verification result selects the verification mark of the high signal-noise area or the low signal-noise area according to the flag bit obtained in the threshold table, and outputs the decoding Termination flag; when the decoding termination flag is 1, stop iteration.

本发明还提供了一种低密度奇偶校验码的译码校验装置，该装置包括控制器模块、阈值表存储器模块、子矩阵符号位改变判断模块、子行符号位改变判断模块、高信噪区码字校验模块、低信噪区码字校验模块和校验结果产生模块，其中，控制器模块控制整个装置的操作；阈值表存储器模块存储预先设置的参数；子矩阵符号位改变判断模块判断一个子矩阵更新前后信息位的符号位是否改变；子行符号位改变判断模块判断一个子行更新前后信息位的符号位是否改变；高信噪区码字校验模块根据子行符号位不改变的连续子行的个数与从阈值表中得到的阈值进行比较得到判断结果；低信噪区码字校验模块把输入的迭代次数和从阈值表中得到的阈值进行比较输出结果；校验结果产生模块处理对高信噪区和低信噪区的校验结果进行处理，产生译码终止标志。The present invention also provides a device for decoding and verifying low-density parity-check codes. The device includes a controller module, a threshold table memory module, a sub-matrix sign bit change judgment module, a sub-row sign bit change judgment module, a high-signal Noise area code word verification module, low signal to noise area code word verification module and verification result generation module, wherein, the controller module controls the operation of the entire device; the threshold table memory module stores preset parameters; the sub-matrix sign bit changes The judging module judges whether the sign bit of the information bit changes before and after a sub-matrix is updated; the sub-row sign bit changes the judgment module and judges whether the sign bit of the information bit changes before and after a sub-row is updated; The number of consecutive sub-rows whose bits do not change is compared with the threshold obtained from the threshold table to obtain the judgment result; the code word verification module in the low signal-to-noise area compares the input iteration number with the threshold obtained from the threshold table and outputs the result ; The verification result generation module processes the verification results of the high signal-to-noise area and the low-signal-noise area, and generates a decoding termination flag.

本发明方法的优点包括：The advantages of the inventive method include:

(1)每行子矩阵迭代计算完后进行译码校验时，由于本方法在低信噪区迭代终止仅需要进行迭代次数的比较，在高信噪区通过比较子行更新前后信息位的符号位不变的连续子行个数进行迭代终止，不需要进行矩阵的乘法运算，大大减少了计算量。(1) When performing decoding verification after the iterative calculation of each row of sub-matrix, since this method only needs to compare the number of iterations when the iteration is terminated in the low-signal-to-noise area, in the high-signal-to-noise area by comparing the information bits before and after the update of the sub-row The number of consecutive sub-rows whose sign bit remains unchanged is terminated by iteration, and matrix multiplication is not required, which greatly reduces the amount of calculation.

(2)本发明由于不需要从H矩阵中读取数据，极大地降低了H矩阵存储器的带宽要求。(2) Since the present invention does not need to read data from the H matrix, the bandwidth requirement of the H matrix memory is greatly reduced.

(3)本发明由于每次比较的仅是当前更新的符号位的数据，降低了码字存储器的带宽要求。读取码字存储器次数的减少有利于节省功耗。(3) The present invention reduces the bandwidth requirement of the code word memory because only the data of the currently updated sign bit is compared each time. The reduction in the number of times to read the codeword memory is beneficial to save power consumption.

附图说明Description of drawings

图1是LDPC码所采用的校验矩阵；Fig. 1 is the parity check matrix that LDPC code adopts;

图2是符合AA架构的H矩阵的表示形式；Figure 2 is a representation of the H matrix conforming to the AA architecture;

图3是配置参数信息表的内部结构；Fig. 3 is the internal structure of configuration parameter information table;

图4是本发明校验流程图；Fig. 4 is a verification flowchart of the present invention;

图5是本发明控制器装置结构框图；Fig. 5 is a structural block diagram of the controller device of the present invention;

图6是本发明子矩阵符号位改变判断模块结构图；Fig. 6 is the sub-matrix sign bit change judgment module structural diagram of the present invention;

图7是本发明子行符号位改变判断模块结构图；Fig. 7 is the structural diagram of the judging module for sub-row sign bit change in the present invention;

图8是本发明高信噪区码字校验模块结构示意图；Fig. 8 is a schematic structural diagram of a codeword checking module in a high-signal-to-noise area of the present invention;

图9是本发明低信噪区码字校验模块结构示意图；Fig. 9 is a schematic structural diagram of a codeword verification module in a low signal-to-noise area of the present invention;

图10是本发明校验结果输出模块示意图。Fig. 10 is a schematic diagram of the verification result output module of the present invention.

具体实施方式Detailed ways

下面结合具体实施方式和附图进一步说明本发明的方案。The solutions of the present invention will be further described below in conjunction with specific implementation methods and accompanying drawings.

本发明提出的校验方法包含如下内容：The verification method that the present invention proposes comprises following content:

(1)对于不同码率和信噪比的码字，设置一个阈值表。如图3所示，该阈值表包括四个部分：信噪比(Eb/N0)、码率、阈值和标志位(flag)。信噪比和码率是输入变量，阈值和标志位是输出变量，输入变量和输出变量是一一对应关系。一一对应的关系是通过仿真预先设定并存储在储存器中。信噪比和码率是输入码字的属性。阈值根据标志位的不同，其含义不同。当标志位为0时，阈值是处于低信噪区码字的阈值，它表示是迭代次数的最大值。当标志位为1时，阈值是处于高信噪区码字的阈值，它表示是子行符号位更新前后符号位连续不变子行的最大个数。标志位可通过公式(6)确定，其中E是一个信噪比，可通过仿真确定。(1) For codewords with different code rates and SNRs, set a threshold table. As shown in FIG. 3, the threshold table includes four parts: signal-to-noise ratio (Eb/N0), code rate, threshold and flag (flag). The signal-to-noise ratio and code rate are input variables, the threshold and flag bits are output variables, and the input variables and output variables have a one-to-one correspondence. The one-to-one correspondence is preset by simulation and stored in the memory. SNR and code rate are properties of the input codeword. The threshold has different meanings depending on the flag bit. When the flag bit is 0, the threshold is the threshold of the codeword in the low signal-to-noise area, which represents the maximum number of iterations. When the flag bit is 1, the threshold is the threshold of the codeword in the high signal-to-noise area, which indicates the maximum number of consecutive sub-rows whose sign bits are unchanged before and after the sub-row sign bit is updated. The flag bit can be determined by formula (6), where E is a signal-to-noise ratio, which can be determined by simulation.

$flag flag = = \{\begin{matrix} 00 & Eb Eb / / N N 00 \leq \leq E E. \\ 11 & Eb Eb / / N N 00 > > E E. \end{matrix} - - - - - - ((66))$

(2)对于低信噪区码字的判断，令从阈值表中得到的阈值为I_stop，比较迭代次数和I_stop，当迭代次数I大于I_stop时，则低信噪区校验标志Fi置1，停止迭代译码，否则Fi置0，继续进行迭代。(2) For the judgment of the codeword in the low signal-to-noise area, let the threshold obtained from the threshold table be I _stop , compare the number of iterations with I _stop , when the number of iterations I is greater than I _stop , then the check mark Fi in the low-signal-to-noise area Set to 1 to stop iterative decoding, otherwise set Fi to 0 to continue iteration.

${F f}_{i i} = = \{\begin{matrix} 00 & I I < < {I I}_{stop stop} \\ 11 & I I &GreaterEqual; &Greater Equal; {I I}_{stop stop} \end{matrix} - - - - - - ((77))$

(3)符号位的变化判决。用R(k)表示第k个子行，M(R(k))表示第k个子行中所有非零子矩阵的集合。如在图2中，第3个子行用R(3)表示，M(R(3))表示子行3中所有的非零子矩阵{2，4，8}。(3) Change judgment of the sign bit. Let R(k) represent the kth sub-row, and M(R(k)) represent the set of all non-zero sub-matrices in the k-th sub-row. As in FIG. 2, the third sub-row is represented by R(3), and M(R(3)) represents all non-zero sub-matrices {2, 4, 8} in sub-row 3.

LDPC的迭代译码过程中，每一次迭代都会更新变量节点信息。公式(8)表示子矩阵m更新前后变量节点信息的符号变化。其中，s_n代表子矩阵中更新前的第n个变量节点信息的符号，s′_n代表子矩阵中更新后第n个变量节点信息的符号。

代表异或运算，即如果更新前后的符号位相同则为1，否则结果为0。然后所得的结果进行位与运算，操作符为&。In the iterative decoding process of LDPC, the variable node information is updated every iteration. Formula (8) represents the sign change of variable node information before and after sub-matrix m is updated. Among them, s _n represents the symbol of the nth variable node information before updating in the sub-matrix, and s′ _n represents the symbol of the n-th variable node information in the sub-matrix after updating.

Represents an XOR operation, that is, if the sign bits before and after the update are the same, it is 1, otherwise the result is 0. The result is then bitwise ANDed with the operator &.

一个子行的所有的信息位更新前后的符号位变化等价于所有非零子矩阵中的信息位更新前后的符号位变化，所以第k个子行更新前后符号位是否不变化可通过公式(9)来判断，若T^(k) _counter等于0，则说明第k个子行更新前后符号位没有改变，若大于0，则说明第k个子行更新前后符号位有改变。The change of the sign bit before and after updating all the information bits of a sub-row is equivalent to the change of the sign bit before and after the update of the information bits in all non-zero sub-matrices, so whether the sign bit of the kth sub-row does not change before and after the update can be determined by the formula (9 ) to judge, if T ^(k) _counter is equal to 0, it means that the sign bit of the kth sub-row has not changed before and after the update, and if it is greater than 0, it means that the sign bit of the kth sub-row has changed before and after the update.

${T T}^{((k k))}_{counter counter} = = \underset{j j &Element; &Element; M m ((R R ((k k))))}{Σ Σ} c c ((k k,, j j)) - - - - - - ((99))$

子行连续符号位不改变的个数通过公式(10)来计算，如果第k个子行所有信息位的符号位没有改变，则连续子行符号位不变的个数加1，否则清零。The number of consecutive sign bits of sub-rows that do not change is calculated by formula (10). If the sign bits of all information bits of the kth sub-row do not change, the number of consecutive sub-row sign bits that do not change is increased by 1, otherwise it is cleared to zero.

${T T}_{counter counter} = = \{\begin{matrix} {T T}_{counter counter} + + 11 & {T T}^{((k k))}_{counter counter} &NotEqual; &NotEqual; 00 \\ {T T}_{counter counter} & {T T}^{((k k))}_{counter counter} = = 00 \end{matrix} - - - - - - ((1010))$

(4)对于高信噪区码字的判断，令阈值表中根据码率和信噪比得到的阈值参数为T_stop，高信噪区终止标志为F_h，如公式(11)所示，当计数器的值T_counter大于等于T_stop时，F_h置1，将停止迭代，否则F_h置0，继续进行迭代。(4) For the judgment of the codeword in the high SNR area, let the threshold parameter obtained according to the code rate and the SNR in the threshold table be T _stop , and the end flag of the high SNR area be F _h , as shown in formula (11), When the counter value T _counter is greater than or equal to T _stop , F _h is set to 1, and the iteration will stop, otherwise, F _h is set to 0, and the iteration continues.

${F f}_{h h} = = \{\begin{matrix} 00 & {T T}_{counter counter} < < {T T}_{stop stop} \\ 11 & {T T}_{counter counter} &GreaterEqual; &Greater Equal; {T T}_{stop stop} \end{matrix} - - - - - - ((1111))$

(5)校验结果输出如公式(12)所示，当flag等于0，即码字处于低信噪区时，校验结果F等于F_i；当flag等于1，即码字处于高信噪区时，校验结果F等于F_h。(5) The verification result output is as shown in formula (12), when the flag is equal to 0, that is, when the code word is in the low signal-to-noise area, the verification result F is equal to F _i ; when the flag is equal to 1, that is, the code word is in the high signal-to-noise area zone, the verification result F is equal to F _h .

$F f = = \{\begin{matrix} {F f}_{i i} & flag flag = = 00 \\ {F f}_{h h} & flag flag = = 11 \end{matrix} - - - - - - ((1212))$

本方法的具体流程如图4所示，当码字输入后，根据码字的码率和信噪比从阈值表中查得对应的阈值和标志位，高信噪区校验模块和低信噪区校验模块分别产生相应的校验标志，校验结果模块根据从阈值表中查得的标志位判断输出高信噪区的判断标志还是低信噪区的校验标志。如果校验结果输出的终止标志位为零，则继续进行迭代，否则停止进行迭代。The specific process of this method is shown in Figure 4. After the codeword is input, the corresponding threshold and flag are found from the threshold table according to the code rate and SNR of the codeword. The noise region verification module generates corresponding verification marks respectively, and the verification result module judges whether to output the judgment mark of the high signal-to-noise region or the verification mark of the low-signal-to-noise region according to the flag bits checked from the threshold table. If the termination flag bit of the verification result output is zero, then continue to iterate, otherwise stop to iterate.

根据本发明校验方法，得到的装置包括控制器模块、配置参数存储器、子矩阵码字信息位符号改变判断模块、子行码字符号改变判断模块、低信噪区校验模块、高信噪区校验模块和校验结果产生模块。According to the verification method of the present invention, the obtained device includes a controller module, a configuration parameter memory, a sub-matrix codeword information bit symbol change judgment module, a sub-row codeword symbol change judgment module, a low signal-to-noise area verification module, and a high-signal-to-noise region verification module. An area checking module and a checking result generating module.

控制器模块负责控制整个装置的工作。控制器模块接收校验使能信号，码率信号和校验矩阵存储器送来的数据信号。控制器模块发送地址信号、读写信号和片选信号读取译码信息位存储器和配置信息存储器的数据；子矩阵符号位改变判断模块判断一个子矩阵更新前后信息位的符号位是否改变；子行符号位改变判断模块判断一个子行更新前后信息位的符号位是否改变；高信噪区码字校验模块根据子行符号位不改变的连续子行的个数与从阈值表中得到的阈值进行比较得到判断结果；低信噪区码字校验模块把输入的迭代次数和从阈值表中得到的阈值进行比较输出校验标志；校验结果产生模块对高信噪区和低信噪区输出的校验标志进行处理，产生译码终止标志。The controller module is responsible for controlling the work of the whole device. The controller module receives the check enable signal, the code rate signal and the data signal sent from the check matrix memory. The controller module sends address signals, read and write signals and chip select signals to read the data of the decoding information bit memory and the configuration information memory; the sub-matrix sign bit change judgment module judges whether the sign bit of the information bit changes before and after a sub-matrix is updated; The row sign bit change judgment module judges whether the sign bit of the information bit changes before and after a sub-row is updated; the high signal-to-noise area code word checking module is based on the number of consecutive sub-rows whose sign bit does not change and the threshold value obtained from the threshold table. The threshold value is compared to obtain the judgment result; the code word verification module in the low signal-to-noise area compares the input iteration number with the threshold obtained from the threshold table to output the verification mark; the verification result generation module compares the high-signal-noise area and the low-signal-noise The check marks output by the area are processed to generate a decoding termination mark.

配置参数存储器保存国标DMB-TH的3种码率的校验矩阵，由于存储的是常数，采用只读存储器实现。配置参数存储器中存储单元的数据格式如图3所示，包含四部分：Eb/N0，码率，阈值和标志位。Eb/N0代表信道的信噪比。当标志位为0时，代表此时的Eb/N0处于低信噪区，阈值代表着迭代次数；当标志位为1时，代表这时的Eb/N0处于高信噪区，阈值代表着更新中符号位改变连续为零的个数的阈值。The configuration parameter memory saves the parity check matrix of the three code rates of the national standard DMB-TH, which is realized by a read-only memory because it stores constants. The data format of the storage unit in the configuration parameter memory is shown in Figure 3, which includes four parts: Eb/N0, code rate, threshold and flag. Eb/N0 represents the signal-to-noise ratio of the channel. When the flag bit is 0, it means that Eb/N0 is in the low signal-to-noise area at this time, and the threshold represents the number of iterations; when the flag bit is 1, it means that Eb/N0 is in the high signal-to-noise area at this time, and the threshold represents the update The threshold for the number of consecutive zeros where the sign bit changes.

子矩阵码字符号改变判断模块。如图6所示，s_n和s′_n分别代表一个子矩阵更新前后信息位的符号位。首先s_n和s′_n通过异或操作得到一个中间结果F″，异或操作之后，再把n个异或后的结果s″₁，s″₂...s″_n进行与操作，判断这个结果是否为零，如果为零，则子矩阵标志位F′置1，否则置0。Sub-matrix codeword symbol change judgment module. As shown in FIG. 6, s _n and s' _n respectively represent the sign bits of information bits before and after updating a sub-matrix. First, s _n and s′ _n obtain an intermediate result F″ through XOR operation, after XOR operation, then perform AND operation on n XOR results s″ ₁ , s″ ₂ ... s″ _n , and judge Whether the result is zero, if it is zero, the sub-matrix flag F' is set to 1, otherwise it is set to 0.

子行码字符号改变判断模块。如图7所示，本模块累加子矩阵码字符号位改变判断模块的输出结果，当行结束标志位使能时，停止累加，并输出累加结果。A sub-line codeword sign change judging module. As shown in Figure 7, this module accumulates the output result of the sub-matrix codeword number change judgment module, and when the end-of-row flag is enabled, the accumulation is stopped and the accumulation result is output.

高信噪区码字校验模块。如图8所示，对子行码字符号改变判断模块的输出结果进行累加，此模块产生一个迭代终止判断标志T_counter。如果T_counter大于等于从阈值表得到的阈值，则输出标志位为1，否则为零。Codeword verification module for high signal-to-noise areas. As shown in FIG. 8 , the output results of the sub-line codeword symbol change judgment module are accumulated, and this module generates an iteration termination judgment flag T _counter . If T _counter is greater than or equal to the threshold obtained from the threshold table, the output flag is 1, otherwise it is zero.

低信噪区码字校验模块。如图9所示，在低信噪区校验方法主要通过迭代次数I与设置的迭代次数阈值I_stop进行比较，如果I大于阈值I_stop，则停止迭代，否则继续进行迭代。当迭代终止时，输出终止标志符号和输出使能标志使能，输出使能代表这时的输出标志是有效的。Code word verification module for low signal-to-noise area. As shown in FIG. 9 , the verification method in the low signal-to-noise area mainly compares the iteration number I with the set iteration number threshold I _stop , if I is greater than the threshold I _stop , then stop the iteration, otherwise continue to iterate. When the iteration is terminated, the output termination flag and the output enable flag are enabled, and the output enable means that the output flag at this time is valid.

校验结果输出模块。如图10所示，当高信噪区和低信噪区的判断标志进入译码成功标志产生模块时，此模块需要从参数配置存储器中输入的标志位F_hl判断。当标志位1时，此时输出高信噪区的校验标志，否则输出低信噪区的校验标志。当译码成功标志为1时停止译码迭代，否则继续进行迭代。Verification result output module. As shown in Figure 10, when the judgment flags of the high signal-to-noise area and the low-signal-to-noise area enter the decoding successful flag generation module, this module needs to judge from the flag bit F _hl input in the parameter configuration memory. When the flag bit is 1, the check mark of the high signal-to-noise area is output at this time, otherwise the check mark of the low signal-to-noise area is output. Stop decoding iteration when the decoding success flag is 1, otherwise continue to iterate.

下文引入LDPC解码过程。The LDPC decoding process is introduced below.

初始化校验节点序列等于全0。初始化信息节点为所接收的信道信息。The initialization check node sequence is equal to all 0s. The initialization information node is the received channel information.

然后进行迭代计算。根据等式(1)和(2)计算校验节点序列R_cv。当一个子行的校验节点计算完成后，根据等式(3)计算变量节点。计算中，由于硬件的精度影响，需要对变量节点和校验节点序列进行量化。Then perform iterative calculations. The check node sequence R _cv is calculated according to equations (1) and (2). After the calculation of the check node of a sub-row is completed, the variable node is calculated according to equation (3). In the calculation, due to the influence of hardware precision, it is necessary to quantize the sequence of variable nodes and check nodes.

迭代计算过程不断进行，直到译码成功标志有效或者迭代次数达到最大值，才退出迭代计算。The iterative calculation process continues until the successful decoding flag is valid or the number of iterations reaches the maximum value before exiting the iterative calculation.

当每一块行变量节点信息更新完成，根据等式(4)得到译码码字。When the update of the variable node information of each block is completed, the decoding codeword is obtained according to equation (4).

根据本发明的校验方法，本实施例首先将H矩阵以子行划分为S1个子行和S2子列。这样划分的目的是与迭代计算过程一致，方便计算。对中国数字电视地面标准中0.4码率的校验矩阵，参数S1＝35，S2＝59。因此，校验矩阵可分为35个子行，一次整个矩阵的迭代可分为35次子迭代完成。According to the verification method of the present invention, in this embodiment, the H matrix is firstly divided into S1 sub-rows and S2 sub-columns by sub-rows. The purpose of this division is to be consistent with the iterative calculation process and to facilitate calculation. For the parity check matrix of the 0.4 code rate in the Chinese digital TV terrestrial standard, the parameters S1=35, S2=59. Therefore, the check matrix can be divided into 35 sub-rows, and one iteration of the entire matrix can be divided into 35 sub-iterations to complete.

图5是本发明的校验装置。下面以DMB-TH为例对该装置的工作原理进行详细的说明。当需要译码的码字进入译码器后，控制器模块根据输入的码率和校验使能信号产生控制信号。控制器模块发送地址信号、读写信号和片选信号读取译码信息位存储器和配置信息存储器的数据；控制器模块发送子矩阵符号位改变模块的数据选择信号和计算使能信号；控制器模块发送子行符号位改变模块的寄存器清零和数据使能信号；控制器模块发送低信噪区码字校验模块的比较使能和寄存器清零信号；控制器模块发送高信噪区码字校验模块的比较使能和寄存器清零信号；控制器模块发送译码成功标志产生模块的结果选择信号和寄存器清零信号。Fig. 5 is the verification device of the present invention. The working principle of the device will be described in detail below taking DMB-TH as an example. When the codeword to be decoded enters the decoder, the controller module generates a control signal according to the input code rate and the check enable signal. The controller module sends address signals, read and write signals and chip select signals to read the data of the decoding information bit memory and the configuration information memory; the controller module sends the data selection signal and the calculation enable signal of the sub-matrix sign bit change module; the controller The module sends the register clearing and data enabling signals of the sub-row sign bit change module; the controller module sends the comparison enabling and register clearing signals of the low signal-to-noise area code word verification module; the controller module sends the high signal-to-noise area code The comparison enable of the word verification module and the register clearing signal; the controller module sends the result selection signal and the register clearing signal of the successful decoding flag generation module.

当输入Eb/N0和码率时，存储器输出参数阈值和标志位。例如，当码率为0.4，Eb/N0＝1.0dB时，输出的标志位为0，代表这时的Eb/N0处于低信噪区；输出的阈值为6代表着迭代终止的次数的阈值为6，当迭代次数大于等于6时停止迭代。当码率为0.6，Eb/N0＝2.5dB时，输出的标志位为1，代表这时的Eb/N0处于高信噪区；输出的阈值为35代表着子行更新符号位不变个数为零的连续个数大于等于35时停止迭代。When Eb/N0 and code rate are input, the memory outputs parameter threshold and flag bit. For example, when the code rate is 0.4 and Eb/N0=1.0dB, the output flag is 0, which means that Eb/N0 is in the low signal-to-noise area; the output threshold is 6, which means that the threshold for the number of iteration terminations is 6. Stop iterating when the number of iterations is greater than or equal to 6. When the code rate is 0.6 and Eb/N0=2.5dB, the output flag is 1, which means that Eb/N0 is in a high signal-to-noise area at this time; the output threshold is 35, which means that the number of sub-row update sign bits remains unchanged Stop iteration when the consecutive number of zeros is greater than or equal to 35.

因为DMB-TH的每个子矩阵的大小为127，所以在每个子矩阵的迭代过程，s₁，s₂...s₁₂₇代表子矩阵更新前的符号位，s′₁，s′₂...s′₁₂₇代表一个子行更新后的符号位。令n的取值范围为1...127，s_n和s′_n通过异或操作得到一个中间结果s′_n，异或操作之后，再把127个异或后的结果s″₁，s″₂...s″₁₂₇进行与操作，判断这个结果是否为零，如果为零，则F″置1，否则置0。Because the size of each sub-matrix of DMB-TH is 127, so in the iterative process of each sub-matrix, s ₁ , s ₂ ... s ₁₂₇ represent the sign bits before the update of the sub-matrix, s′ ₁ , s′ ₂ .. .s' ₁₂₇ represents the updated sign bit of a subrow. Let the value range of n be 1...127, s _n and s′ _n get an intermediate result s′ _n through XOR operation, after XOR operation, then take 127 XOR results s″ ₁ , s " ₂ ...s" ₁₂₇ performs an AND operation to judge whether the result is zero, if it is zero, then F" is set to 1, otherwise it is set to 0.

当码字处于低信噪区，迭代次数I来源于主控模块，I_stop从配置信息存储器获得。如果I大于阈值I_stop，则停止迭代，否则继续进行迭代。当迭代终止时，输出校验标志和输出使能标志en_i，en_i为1时，代表这时的输出标志F_i是有效的，否则输出无效。When the codeword is in the low signal-to-noise area, the number of iterations I comes from the main control module, and I _stop is obtained from the configuration information memory. If I is greater than the threshold I _stop , stop the iteration, otherwise continue to iterate. When the iteration is terminated, the output verification flag and the output enable flag en_i, when en_i is 1, it means that the output flag F _i is valid at this time, otherwise the output is invalid.

当码字处于高信噪区，每个子矩阵判断后输出一个判断标志F′和使能标志en_i，子行的结束标志参数来源于主控制器，当子行计算结束时，此模块产生一个迭代终止判断标志T_counter。T_counter和从配置参数存储器中读入的参数T_stop比较，输出迭代终止标志。When the codeword is in the high signal-to-noise area, each sub-matrix outputs a judgment flag F' and an enable flag en_i after judgment, and the end flag parameter of the sub-row comes from the main controller. When the calculation of the sub-row ends, this module generates an iteration Termination judgment flag T _counter . T _counter is compared with the parameter T _stop read from the configuration parameter memory, and an iteration termination flag is output.

当高信噪区和低信噪区的校验标志进入译码成功标志产生模块时，此模块需要由参数配置存储器中输入的标志位F′_hl判断，并输出迭代终止标志。When the verification flags of the high-signal-noise area and the low-signal-noise area enter the decoding success flag generation module, this module needs to judge by the flag bit _F'hl input in the parameter configuration memory, and output the iteration termination flag.

以下说明校验装置的效果：The following describes the effect of the calibration device:

(1)该装置计算量小，校验速度快。该装置由于不需要进行矩阵的乘法运算，仅仅需要一些简单的与、异或、加法和比较等操作，当进行校验时仅需要信息位的符号位比较，因此大大节省了运算量。进行校验计算时127路并行，1次处理1个子矩阵。(1) The calculation amount of the device is small, and the verification speed is fast. Since the device does not need to perform matrix multiplication, it only needs some simple operations such as AND, XOR, addition, and comparison. When performing verification, it only needs to compare the sign bit of the information bit, thus greatly saving the amount of calculation. 127 parallel paths are used for verification calculation, and one sub-matrix is processed at a time.

(2)该装置的带宽要求低，节省存储器。该装置在校验计算时不需要读取校验矩阵存储器，同时校验时不需要读取信息位存储器，因为只要暂存原始的码字的符号位，而且译码码字的符号位在写入信息位存储器之前可以得到。存储器的读取次数少，带宽要求低，可以复用迭代计算时用到的存储器实现，从而节省了存储器。(2) The device requires low bandwidth and saves memory. The device does not need to read the check matrix memory when verifying and calculating, and does not need to read the information bit memory when verifying, because only the sign bit of the original codeword is temporarily stored, and the sign bit of the decoded codeword is written can be obtained before entering the information bit memory. The number of reads of the memory is small, the bandwidth requirement is low, and the memory used in the iterative calculation can be reused, thereby saving the memory.

Claims

1. A simplified decoding and verification method for low-density parity-check codes, characterized in that: the method includes the setting of a threshold table, codeword verification in low signal-to-noise regions, codeword verification and verification in high-signal-to-noise regions The results are output in four steps, among which, firstly, a threshold table is set according to the simulation, and when iterative decoding is performed, the corresponding threshold is obtained from the threshold table according to the code rate and SNR of the input codeword; in the iterative process, high SNR Area code word verification and low signal-noise area code word verification are judged according to the threshold and output the verification mark, and the verification result selects the verification mark of the high-signal-noise area or the low-signal-noise area according to the flag bits obtained in the threshold table , and output the decoding termination flag, when the verification result is 1, stop the iteration.

2. simplified decoding checking method according to claim 1, is characterized in that: in the setting step of described threshold value table, threshold value table comprises four parts: signal-to-noise ratio (Eb/N0), code rate, threshold value And flag bit, wherein, threshold value is set according to signal-to-noise ratio and code rate, and flag bit distinguishes high signal-to-noise ratio area and low signal-to-noise ratio area, and 1 mark high signal-to-noise ratio area, 0 mark low signal-to-noise ratio area.

3. simplified decoding verification method according to claim 1, is characterized in that: in the step of described low signal to noise area code word verification, at first obtain threshold value according to signal-to-noise ratio and code rate from threshold value table, Then compare the number of iterations with the threshold, if the number of iterations is greater than or equal to the threshold, the check flag of the low-signal-to-noise area codeword is 1, otherwise it is 0.

4. simplified decoding checking method according to claim 1, is characterized in that: in the step of described high signal-to-noise area code word checking, at first obtain threshold value from threshold value table according to signal-to-noise ratio and code rate, Then this threshold is compared with the total number of sub-rows whose sign bit does not change continuously before and after the sub-row update calculation, if the total number of sub-rows whose sign bit does not change continuously before and after the sub-row update calculation is greater than or equal to the threshold, the high signal-to-noise area code word calibration Check flag is 1, otherwise it is 0.

5. simplified decoding verification method according to claim 1, is characterized in that: in the step of described verification result output, according to signal-to-noise ratio and coding rate, obtain sign bit from threshold value table, sign bit is 1 output a high signal-to-noise area check mark, and output a low signal-to-noise area check mark when the flag bit is 0.

6. A decoding and checking device for low-density parity-check codes, characterized in that: the device includes a controller module, a threshold table memory module, a sub-matrix sign bit change check module, and a sub-row sign bit change check module , high signal-to-noise area code word verification module, low signal-to-noise area code word verification module and verification result generation module, wherein, the controller module controls the operation of the whole device; the threshold table memory module stores preset parameters; the sub-matrix The sign bit change verification module judges whether the sign bit of the information bit changes before and after a sub-matrix is updated; the sub-row sign bit change verification module judges whether the sign bit of the information bit changes before and after a sub-row update; the high signal-to-noise area code word verification The module compares the number of consecutive sub-rows whose sign bit does not change with the threshold value obtained from the threshold table to output the check mark; the low-signal-to-noise area code word verification module takes the input iteration number and obtains it from the threshold table The threshold value is compared to output a verification mark; the verification result generation module processes the verification results of the high signal-to-noise area and the low-signal-noise area, and outputs a decoding termination mark.

7. The device according to claim 6, characterized in that: in the threshold table memory module, the memory is a read-only memory, which stores the thresholds of the high signal-to-noise area and the low-signal-to-noise area, and also stores the high and low signal-to-noise values simultaneously. The distinguishing mark of the area; the threshold value of the low signal-noise area represents the threshold value of the number of iterations; the threshold value of the high signal-noise area represents the threshold value of the count value whose sign bit does not change after successive sub-row iterations, no matter in the high signal-noise area or the low signal-noise area region, iterations will terminate when this threshold is exceeded.

8. The device according to claim 6, characterized in that: the sub-matrix sign bit changes the checking module to determine whether the sign bit of the information bit before and after each sub-row update changes, and it is performed by the sign bit of the information bit before and after the update "XOR" operation, and then "AND" operation to get the result.

9. The device according to claim 6, characterized in that: said sub-row sign bit changes the checking module to judge whether the sign bit of the information bit changes before and after each sub-row update, and it accumulates the sign of the sub-matrix updated in this sub-row The bit changes the judgment result. After the accumulation of this line is completed, if the accumulation result is zero, output 1, otherwise output 0.

10. The device according to claim 6, characterized in that: said high-signal-to-noise area code word checking module is carried out cumulative calculation to the input data of the sub-row sign bit change judgment module, and the calculation result is stored in its own register ; Then compare it with the threshold value, if it is greater than or equal to the threshold value, the verification result of the high signal-to-noise area will output 1, otherwise it will output 0.

11. The device according to claim 6, characterized in that: said low-signal-to-noise area codeword verification module compares the input iteration number with the threshold obtained from the threshold table to obtain the verification mark.

12 . The device according to claim 6 , wherein the verification result generation module selects the code word verification flags in the high and low signal-to-noise areas according to the flag bits in the threshold lookup table. 13 .