CN102185596A - Bootstrapping sampling switch applied to high-speed and high-linearity analog-to-digital converter - Google Patents

Abstract

A bootstrap sampling switch applied to high-speed and high-linearity analog-to-digital converters, including: a clock booster, a gate-source voltage follower, a conduction switch and a charge-discharge enhancement circuit, and the clock booster generates several times The power supply voltage charges the capacitor; the gate-source voltage follower connects the capacitor between its gate-source when the conduction switch is closed, and maintains a relatively constant gate-source voltage difference under different voltage inputs; the charge-discharge enhancement circuit is added to the switch The charging or discharging circuit during switching shortens the turn-off and turn-on time, reduces the parasitic capacitance of the turn-on switch gate, thereby reducing the loss of stored charge on the capacitor, and no longer needs to use high-voltage MOS tubes, and at the same time achieves high Linearity of sampling (capable of exceeding one gigahertz sampling rate and obtaining spurious-free dynamic range greater than 95 dB under 65 nm CMOS process). This structure does not introduce complex logic control circuits, does not increase the chip area, and does not need to increase the requirements of the clock buffer.

Description

Bootstrap Sampling Switch for High-Speed and High-Linearity Analog-to-Digital Converters

technical field

The invention relates to an important module applied to a sample-and-hold circuit, in particular to an analog switch suitable for a high-speed, high-linearity analog-to-digital converter using bootstrapped and multiple charging and discharging path technologies.

technical background

In modern mixed-signal integrated circuits, the analog-to-digital converter is an indispensable part, and its conversion accuracy and speed play a decisive role in the performance of the whole system. The analog switches used in the sample-and-hold circuit determine the dynamic range and sampling rate of the ADC.

Figure 1 shows a simple sample-and-hold circuit made up of CMOS switches and capacitors. Traditional CMOS switches are difficult to use in high-linearity analog-to-digital converters due to their large on-resistance and variations with the magnitude of the input signal (green curve shown in Figure 2). Increasing the size of the MOS tube can reduce these non-ideal factors, but it will put forward higher requirements for the clock buffer, and correspondingly require greater power consumption. In addition, in the low-voltage design, when the power supply voltage is less than the sum of the threshold voltages of the NMOS transistor and the PMOS transistor, the traditional CMOS switch will have a region with a particularly large on-resistance.

In order to solve the problems encountered by traditional CMOS switches, as shown in Figure 3, a bootstrap switch (see references A.M.Abo and P.R.Gray, "A 1.5-V 10-bit 14.3-MS/s CMOS Pipeline Analog-to- Digital Converter," IEEE J.Solid-State Circuits, vol.34, pp.599-606, May 1999.) Through the clock booster (clock booster), it is generated at the gate and input of the MOS transistor that acts as a switch Relatively constant and close to the voltage drop of the power supply voltage, a small on-resistance that does not change with the input signal can be obtained. The low-plate sampling technology widely used in analog-to-digital converters requires switches with as short a turn-off time as possible. At the same time, in order to further increase the sampling rate, the sampling time is continuously compressed in the circuit design. Turn-on time puts forward higher requirements. This kind of bootstrap switch has the disadvantage of long turn-off time and turn-on time, and the high-voltage NMOS transistors (such as M11 and M12 in Figure 3) used to ensure reliability further limit the switching speed of the switch.

Contents of the invention

The object of the present invention is, by providing a bootstrap sampling switch applied to a high-speed high-linearity analog-to-digital converter, on the basis of the practice generally used at present, shortening the demand of the switch off and on time, the present invention in Under the premise of not increasing the design complexity and chip area, the multi-charging and discharging channel technology is used to improve the switching speed, and the high-voltage NMOS tube is no longer required.

The present invention is realized by adopting the following technical means:

The present invention is a bootstrap sampling switch applied to a high-speed high-linearity analog-to-digital converter, comprising: a clock booster, a gate-source voltage follower, a conduction switch and a charge-discharge enhancement circuit, and the clock booster generates two times the power supply voltage to charge the capacitor; the gate-source voltage follower connects the capacitor between its gate-source when the conduction switch is closed, and maintains a relatively constant gate-source voltage difference under different voltage inputs; the charge-discharge enhancement circuit increases A charge or discharge circuit during switch switching, where:

The aforementioned clock booster includes an inverter I1, two NMOS transistors M1 and M2, and two capacitors C1 and C2, wherein: the inverted clock signal is connected to the lower plate of the aforementioned capacitor C1, and connected to The lower plate of the aforementioned capacitor C2; the drains of M1 and M2 are connected to the power supply, their gates are connected to each other's sources, and to the upper plates of C1 and C2 respectively.

The aforementioned gate voltage follower includes five NMOS transistors M3, M4, M6, M8 and M9, two PMOS transistors M5 and M7, and a capacitor C3, wherein: the gate of M3 is connected to the gate of M2 in the aforementioned clock booster Connection, the drain is connected to the power supply, the source is connected to the upper plate of the capacitor C3, the gate of the NMOS transistor M4 is controlled by an inverted clock signal, the source is connected to the ground, and the drain is connected to the lower plate of the capacitor C3; the PMOS transistor M7 The source and the drain are respectively connected to the upper plate of the capacitor C3 and the gate of the aforementioned NMOS transistor M9, and the drain and source of M9 are respectively connected to the lower plate of the capacitor C3 and the input end; the gate of the NMOS transistor M6 is connected by a positive phase Clock signal control, the drain is connected to the gate of the PMOS transistor M7, the source is connected to the lower plate of the capacitor C3; the gate of M8 is connected to the gate of M9, the drain is connected to the gate of the PMOS transistor M7, and the source is connected to the aforementioned capacitor The lower plate of C3; the gate of the PMOS transistor M5 is controlled by a positive-phase clock signal, the source is connected to the power supply, and the drain is connected to the gate of the PMOS transistor M7.

The conduction switch includes an NMOS transistor M10, the source and drain of which are respectively connected to the input terminal and the output terminal, and the gate is connected to the gate of the NMOS transistor M9 in the aforementioned gate voltage follower.

The charging and discharging enhancement circuit includes two NMOS transistors M13 and M14, wherein: the gate of M13 is controlled by a positive phase clock signal, the drain is connected to the power supply, and the source is connected to the drain of the PMOS transistor M7; the gate of M14 is controlled by an inverse clock signal control, the drain is connected to the gate of the NMOS transistor M9, and the source is connected to the drain of M9.

Compared with the prior art, the present invention has the following obvious advantages and beneficial effects:

The present invention is applied to a bootstrap sampling switch of a high-speed high-linearity analog-to-digital converter. Compared with a traditional MOS tube of the same size, the switching speed of the switch is improved and the time is shortened on the premise of realizing high linearity. turn-off and turn-on times. A bootstrap sampling switch suitable for high-speed and high-linearity analog-to-digital converters is realized, which has the characteristics of simple structure, small area, low power consumption and fast switching speed.

Description of drawings

Figure 1 is a sample and hold circuit diagram using a traditional CMOS switch;

Fig. 2 is a schematic diagram of the on-resistance simulation results of NMOS transistors, PMOS transistors and CMOS switches under different input voltages;

Fig. 3 is the circuit diagram of the bootstrap switch proposed by Abo;

Fig. 4 is the high speed high linearity bootstrap switch circuit diagram that the present invention proposes;

Fig. 5 is a schematic diagram of the simulation result of the gate-source voltage of the conduction switch (M10) when the switch is switched in the traditional way and the present invention;

FIG. 6 is a frequency spectrum diagram of bootstrap switch sampling in the present invention.

Symbol Description:

41 is a charging and discharging enhancement circuit;

Specific implementation method

The bootstrap sampling switch in the embodiment of the present invention is shown in FIG. 4 . Including: clock booster, gate-source voltage follower, conduction switch and charge-discharge enhancement circuit.

1. The clock signal controls the bootstrap sampling switch from turn-off to turn-on:

The two NMOS transistors M6 and M13 are turned on at the same time, so that the gates of the three NMOS transistors M8, M9 and M10 can be charged before the PMOS transistor M7 is turned on. Since this part of the charging charge comes directly from the power supply instead of the capacitor C3, more charge can be added between the gate and source of the NMOS transistor M10 as a turn-on switch, corresponding to a higher gate-source voltage and lower on-resistance. In addition, a higher gate-source voltage can also speed up the turn-on speed of the two NMOS transistors M8 and M9, and indirectly speed up the turn-on speed of the PMOS transistor M7. When the PMOS transistor M7 is fully turned on, since the gate-source voltage is lower than the threshold voltage, the NMOS transistor M13 is turned off, and the gate voltage of the turn-on switch M10 is no longer affected. By comparing the charging paths marked with solid lines in FIG. 3 and FIG. 4 , the present invention shortens the turn-on time of the switch by adding an extra path.

2. The clock signal controls the bootstrap sampling switch from turn-on to turn-off:

After the NMOS transistor M14 is turned on, the gate and source of the conduction switch M10 are short-circuited, which is also the most direct way to turn off a MOS transistor. The NMOS transistor M4 will eventually pull the gate-source of the conduction switch M10 to ground. Since the gate-source voltage of the turn-on switch M10 is shorted together before being pulled to ground, it can be turned off faster than the traditional method of pulling its gate and source to ground separately as shown in FIG. off switch. Moreover, since the high-voltage MOS transistors (such as M11 and M12 in FIG. 3 ) that must be used in the traditional method are no longer needed, the parasitic capacitance on the gate of the turn-on switch M10 is reduced, and the turn-off speed is further accelerated. By comparing the discharge paths marked with dotted lines in FIG. 3 and FIG. 4 , the present invention shortens the turn-off time of the switch by optimizing the original path.

When the input signal is large, the NMOS transistor M14 used to short-circuit the gate and source of the switch M10 may not be opened directly, but as the NMOS transistor M4 reduces the source voltage of the NMOS transistor M14, the source and drain of the switch M10 are turned on. The discharge path will also be opened. Even so, the discharge rate will be faster than the traditional way as shown in Figure 3. Increasing the size of the NMOS transistor M4 can effectively increase the turn-off speed in this extreme situation, and the resulting parasitic capacitance will hardly occupy the charge stored on the capacitor C3. Since the voltage between the source and drain of the NMOS transistor M14 is always lower than the power supply voltage, there is no need to use a high-voltage MOS transistor to ensure the reliability of the circuit.

According to the simulation results of Fig. 5 and Fig. 6, it can be seen that the embodiment of the present invention uses a MOS tube of the same size as the traditional method, and under the premise of achieving high linearity, the switching speed is improved, and the turn-off and switching time are shortened. opening time.

Finally, it should be noted that: the above embodiments are only used to illustrate the present invention rather than limit the technical solutions described in the present invention; Those of ordinary skill in the art should understand that the present invention can still be modified or equivalently replaced; and all technical solutions and improvements that do not depart from the spirit and scope of the invention should be covered by the claims of the present invention.

Claims (2)

1. A bootstrap sampling switch applied to a high-speed high-linearity analog-to-digital converter, comprising: a clock booster, a gate-source voltage follower, a conduction switch and a charge-discharge enhancement circuit, characterized in that: a clock booster The voltage transformer generates several times the power supply voltage to charge the capacitor; the gate-source voltage follower connects the capacitor between its gate and source when the conduction switch is closed, and maintains a relatively constant gate-source voltage difference under different voltage inputs; charging The discharge enhancement circuit increases the charging or discharging loop when the switch is switched, where: The clock booster includes an inverter (I1), two NMOS transistors (M1) and (M2), two capacitors (C1) and (C2); the inverted clock signal is connected to the bottom of the capacitor (C1) The plate is connected to the lower plate of the capacitor (C2) through the inverter (I1); the drains of (M1) and (M2) are connected to the power supply, the gates are connected to each other’s sources, and the capacitors ( The upper plate of C1) and (C2); The gate voltage follower includes five NMOS transistors (M3), (M4), (M6), (M8) and (M9), two PMOS transistors (M5) and (M7), and a capacitor (C3), Among them: the gate of the NMOS transistor (M3) is connected to the gate of the NMOS transistor (M2) in the clock booster, the drain is connected to the power supply, the source is connected to the upper plate of the capacitor (C3), and the gate of the NMOS transistor (M4) The pole is controlled by an inverted clock signal, the source is connected to the ground, and the drain is connected to the lower plate of the capacitor (C3); the source and drain of the PMOS transistor (M7) are respectively connected to the upper plate of the capacitor (C3) and the NMOS transistor The gate of (M9), the drain and the source of the NMOS transistor (M9) are respectively connected to the lower plate and the input terminal of the capacitor (C3); the gate of the NMOS transistor (M6) is controlled by a positive-phase clock signal, and the drain is connected to The grid of (M7) is connected to the lower plate of the capacitor (C3) by the source; the grid of (M8) is connected to the grid of (M9), the drain is connected to the grid of (M7), and the source is connected to the capacitor (C3) ) of the lower plate; the gate of (M5) is controlled by a positive-phase clock signal, the source is connected to the power supply, and the drain is connected to the gate of (M7); The conduction switch includes an NMOS transistor (M10), its source and drain electrodes are respectively connected to the input terminal and the output terminal, and the gate is connected to the gate of the NMOS transistor (M9) in the gate voltage follower; The charging and discharging enhancement circuit includes two NMOS transistors (M13) and (M14), wherein: the gate of (M13) is controlled by a positive phase clock signal, the drain is connected to the power supply, and the source is connected to the drain of the PMOS transistor (M7) ; The gate of the NMOS transistor (M14) is controlled by an inverted clock signal, the drain is connected to the gate of the (M9), and the source is connected to the drain of the (M9). 2. the bootstrap sampling switch that is applied to high-speed high-linearity analog-to-digital converter according to claim 1, is characterized in that: the multiple power supply voltage that described clock booster produces is electric capacity charging; Its multiple is double.

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