CN102184897A - Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit - Google Patents
Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit Download PDFInfo
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- CN102184897A CN102184897A CN2011100761757A CN201110076175A CN102184897A CN 102184897 A CN102184897 A CN 102184897A CN 2011100761757 A CN2011100761757 A CN 2011100761757A CN 201110076175 A CN201110076175 A CN 201110076175A CN 102184897 A CN102184897 A CN 102184897A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 6
- 150000004706 metal oxides Chemical class 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 title abstract description 6
- 230000000295 complement effect Effects 0.000 title abstract description 4
- 230000001105 regulatory effect Effects 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000009628 steelmaking Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract 4
- 238000005516 engineering process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit. The manufacturing process comprises an N-well manufacturing step, an active area manufacturing step, a P-type field manufacturing step, a polycrystal manufacturing step, an N-type region manufacturing step, a P-type region manufacturing step, a contact hole manufacturing step, an aluminum wire manufacturing step and a passivation layer manufacturing step. The manufacturing process further comprises a base region manufacturing step and a capacitor manufacturing step which are carried out after the P-type field manufacturing step, and an N-type Ldd (Lightly Doped Drain) manufacturing step carried out after the polycrystal manufacturing step. According to the manufacturing process disclosed by the invention, a polycrystalline capacitor is optimized to be an MOS (Metal Oxide Semiconductor) capacitor by means of the added capacitor manufacturing step, thus the design precision of a product is improved; simultaneously, a bipolar and DMOS (Diffused Metal Oxide Semiconductor) structure is manufactured by means of the added base region manufacturing step and N-type Ldd manufacturing step; in addition, the performance of a circuit is further optimized by regulating the concentration of an N-type region.
Description
Technical field
The present invention relates to a kind of DBICMOS (diffused CMOS (Complementary Metal Oxide Semiconductor), bipolar and complementary metal oxide semiconductors (CMOS)) integrated circuit fabrication process.
Background technology
The manufacturing of current DBICMOS circuit generally is to adopt general integrated circuit fabrication process, yet the process application of this routine has caused following inconvenience when the DBICMOS circuit:
At first, in order to consider various process characteristics, circuit requirement photoetching level is too many;
Secondly, circuit characteristic has caused very big difficulty because the restriction of technology is comparatively fixing to design;
The 3rd, current DBICMOS is difficult to realize the requirement of designs high pressure.
Therefore, at above-mentioned situation, press for the manufacturing process of a kind of DBICMOS of being applicable to integrated circuit of exploitation now.
Summary of the invention
In order to solve the problem that above-mentioned prior art exists, the present invention aims to provide a kind of DBICMOS integrated circuit fabrication process based on the CMOS platform, to satisfy technology specific in the DBICMOS ic manufacturing process and designing requirement by the technological design of optimizing.
A kind of DBICMOS integrated circuit fabrication process of the present invention, this manufacturing process comprises N trap making step, active area making step, P type place making step, polycrystalline making step, N type district making step, p type island region making step, contact hole making step, aluminum steel making step and passivation layer making step, and described manufacturing process also is included in base making step and electric capacity making step and the N type Ldd making step after described polycrystalline making step after the making step of described P type place.
In above-mentioned DBICMOS integrated circuit fabrication process, described base making step is the patterned area that first photoetching forms the base, carrying out boron then in this patterned area injects, and the energy when boron injects is 32.5keV, the dosage range that injects is 4.5E13-5.5E13, under 1100 ℃ temperature, this patterned area is carried out high temperature advance subsequently, with the formation base, and the time range that advances is 20-30min.
In above-mentioned DBICMOS integrated circuit fabrication process, described electric capacity making step is that first photoetching forms capacitive region, then at this capacitive region growth gate oxide, to form mos capacitance, again described capacitive region is regulated and inject boron, and the energy when boron injects is 40keV, and the dosage range of injection is 5.5E11-5.7E11, to form the DBICMOS cut-in voltage.
In above-mentioned DBICMOS integrated circuit fabrication process, described N type Ldd making step is that low-doped drain region is set, and under 950 ℃ temperature, and to the propelling of annealing of this drain region, and the time range that advances is 30-60min.
In above-mentioned DBICMOS integrated circuit fabrication process, described N type district making step comprises that N type district is carried out arsenic to be injected, and the energy of arsenic when injecting be 110keV, and the dosage range of injection is 6E15-6E17.
Owing to adopted above-mentioned technical solution, the present invention adds electric capacity manufacture craft with the Si-gate CMOS process modification of original double-layered polycrystal for the individual layer polycrystalline by increasing the electric capacity making step, thereby polycrystalline electric capacity is optimized for mos capacitance, has improved the design accuracy of product; Simultaneously, by increasing base making step and N type Ldd (Lightly Doped Drain, lightly doped drain) making step, promptly the technology of integrated NDMOS (N type depletion type MOS) and NPN pipe (triode) on general CMOS technology basis has realized bipolar and the making DMOS structure; In addition, also further optimized circuit performance by the concentration of regulating N type district.The present invention can well satisfy the general user and require for the design and processes of DBICMOS circuit and can satisfy the designing requirement of common customer on the cmos circuit basis.
Embodiment
Below in conjunction with accompanying drawing, specific embodiments of the invention are elaborated.
The present invention, it is a kind of DBICMOS integrated circuit fabrication process, comprise the following steps: N trap making step, active area making step, P type place making step, base making step, electric capacity making step, polycrystalline making step, N type Ldd making step, N type district making step, p type island region making step, contact hole making step, aluminum steel making step and passivation layer making step, wherein
The base making step is the patterned area that first photoetching forms the base, carrying out boron then in this patterned area injects, and the energy when boron injects is 32.5keV, the dosage range that injects is 4.5E13-5.5E13, subsequently under 1100 ℃ temperature, this patterned area is carried out high temperature advance, with the formation base, and the time range that advances is 20-30min;
The electric capacity making step is that first photoetching forms capacitive region, has certain thickness gate oxide in the growth of the specific region of this capacitive region then, to form mos capacitance, again described capacitive region is regulated and inject boron, and the energy when boron injects is 40keV, the dosage range that injects is 5.5E11-5.7E11, to form DBICMOS (being NDMOS and MOS) cut-in voltage;
Near near the drain electrode a low-doped drain region being set, and under 950 ℃ temperature, to propellings of annealing of this drain region, and the time range of propelling is 30-60min to N type Ldd making step in raceway groove; Because part voltage is also born in this low-doped drain region, can prevent the hot electron degradation effect, therefore, the Ldd structure promptly be MOS for weaken the drain region electric field, to improve a kind of structure that the hot electron degradation effect is taked, can improve the puncture voltage of NDMOS by this structure, thereby reach designing requirement;
N type district making step comprises that N type district is carried out arsenic As to be injected, and the energy of arsenic when injecting be 110keV, and the dosage range of injection is 6E15-6E17.
Adopt the NDMOS and the NPN pipe of fabrication process of the present invention, their puncture voltage is generally greater than 12V, thereby can satisfy the diversification designing requirement of high pressure.
Below embodiment has been described in detail the present invention in conjunction with the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not constitute limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (5)
1. DBICMOS integrated circuit fabrication process, this manufacturing process comprises N trap making step, active area making step, P type place making step, polycrystalline making step, N type district making step, p type island region making step, contact hole making step, aluminum steel making step and passivation layer making step, it is characterized in that described manufacturing process also is included in base making step and electric capacity making step and the N type Ldd making step after described polycrystalline making step after the making step of described P type place.
2. DBICMOS integrated circuit fabrication process according to claim 1, it is characterized in that, described base making step is the patterned area that first photoetching forms the base, in this patterned area, carry out boron then and inject, and the energy of boron when injecting be 32.5keV that the dosage range of injection is 4.5E13-5.5E13, subsequently under 1100 ℃ temperature, this patterned area is carried out high temperature advance, with the formation base, and the time range that advances is 20-30min.
3. DBICMOS integrated circuit fabrication process according to claim 1, it is characterized in that, described electric capacity making step is that first photoetching forms capacitive region, then at this capacitive region growth gate oxide, to form mos capacitance, described capacitive region is regulated inject boron again, and the energy of boron when injecting is 40keV, the dosage range that injects is 5.5E11-5.7E11, to form the DBICMOS cut-in voltage.
4. DBICMOS integrated circuit fabrication process according to claim 1, it is characterized in that described N type Ldd making step is that low-doped drain region is set, and under 950 ℃ temperature, to the propelling of annealing of this drain region, and the time range that advances is 30-60min.
5. DBICMOS integrated circuit fabrication process according to claim 1 is characterized in that, described N type district making step comprises that N type district is carried out arsenic to be injected, and the energy of arsenic when injecting be 110keV, and the dosage range of injection is 6E15-6E17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110076175 CN102184897B (en) | 2011-03-28 | 2011-03-28 | Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110076175 CN102184897B (en) | 2011-03-28 | 2011-03-28 | Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit |
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| Publication Number | Publication Date |
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| CN102184897A true CN102184897A (en) | 2011-09-14 |
| CN102184897B CN102184897B (en) | 2013-11-06 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5171699A (en) * | 1990-10-03 | 1992-12-15 | Texas Instruments Incorporated | Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication |
| US5618743A (en) * | 1992-09-21 | 1997-04-08 | Siliconix Incorporated | MOS transistor having adjusted threshold voltage formed along with other transistors |
| US20030141566A1 (en) * | 2002-01-25 | 2003-07-31 | Agere Systems Guardian Corp. | Method of simultaneously manufacturing a metal oxide semiconductor device and a bipolar device |
| CN1514481A (en) * | 2002-12-31 | 2004-07-21 | 上海贝岭股份有限公司 | Technology of manufacturing high voltage semiconductor device |
| CN1734748A (en) * | 2004-08-13 | 2006-02-15 | 上海先进半导体制造有限公司 | Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit |
-
2011
- 2011-03-28 CN CN 201110076175 patent/CN102184897B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5171699A (en) * | 1990-10-03 | 1992-12-15 | Texas Instruments Incorporated | Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication |
| US5618743A (en) * | 1992-09-21 | 1997-04-08 | Siliconix Incorporated | MOS transistor having adjusted threshold voltage formed along with other transistors |
| US20030141566A1 (en) * | 2002-01-25 | 2003-07-31 | Agere Systems Guardian Corp. | Method of simultaneously manufacturing a metal oxide semiconductor device and a bipolar device |
| CN1514481A (en) * | 2002-12-31 | 2004-07-21 | 上海贝岭股份有限公司 | Technology of manufacturing high voltage semiconductor device |
| CN1734748A (en) * | 2004-08-13 | 2006-02-15 | 上海先进半导体制造有限公司 | Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit |
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| CN102184897B (en) | 2013-11-06 |
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