CN102184895A - Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof - Google Patents
Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof Download PDFInfo
- Publication number
- CN102184895A CN102184895A CN2011100872656A CN201110087265A CN102184895A CN 102184895 A CN102184895 A CN 102184895A CN 2011100872656 A CN2011100872656 A CN 2011100872656A CN 201110087265 A CN201110087265 A CN 201110087265A CN 102184895 A CN102184895 A CN 102184895A
- Authority
- CN
- China
- Prior art keywords
- side wall
- layer
- grid
- high voltage
- cmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000000295 complement effect Effects 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a manufacturing method of the side wall of a high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device. The method comprises the following steps of: providing a semiconductor substrate, and sequentially forming a gate oxide layer, a grid electrode layer and a grid electrode height-increasing layer on the semiconductor substrate; patterning a grid electrode and forming a drain and source expansion area in the substrate area except the grid electrode; depositing a first side wall layer on the whole surface of a wafer; etching the first side wall layer and forming a first side wall on the two sides of the grid electrode respectively; depositing a second side wall layer on the whole surface of the wafer; and etching the second side wall layer and forming a second side wall outside the first side wall. Correspondingly, the invention also provides the side wall of the high-voltage CMOS device. A big side wall of the high-voltage power device is obtained by manufacturing the grid electrode side walls for two times, so symmetrical widening of the drain and source expansion area under an autocollimation process is realized, and the voltage resistant degree of the high-voltage power device is improved. The manufacturing method is simple in process and is completely compatible with a high-voltage CMOS device process. The consistency among batches is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, the present invention relates to side wall (Spacer has another name called sidewall) of a kind of high voltage CMOS device and preparation method thereof.
Background technology
The application market of high-voltage intelligent power integrated circuit is very extensive, comprises Switching Power Supply AC/DC, DC/DC series products, AC/DC motor driver, flat panel display PDP driver etc.Along with the continuous expansion and the variation of the market demand, integrated circuit manufacturing company needs constantly to release high integration, high-voltage CMOS technique platform cheaply.In high-voltage CMOS technology, its high tension apparatus generally adopts LDMOS (Lateral Double Diffused MOS) structure or drain extension (Drain Extension) technology to improve withstand voltage degree.
Fig. 1 is the cross-sectional view of a high voltage CMOS device in the prior art.As shown in the figure, this device is formed on the Semiconductor substrate 100, is formed with patterned gate oxide 101 and polysilicon layer 102 on it successively, and this gate oxide 101 and polysilicon layer 102 constitute the grid part of device together.Expansion area 103 is leaked in the lightly doped source that is formed with certain width in the Semiconductor substrate 100 of grid both sides respectively, leak expansion area 103 in this source above, the both sides of grid are formed with the side wall 104 of this device respectively.In side wall 104 outsides, Semiconductor substrate 100, then form active, drain region 105.In the prior art, the width of side wall 104 is generally 0.7～1 times of gate height of device.
Along with the high-voltage intelligent power integrated circuit for the improving constantly of semiconductor device requirement of withstand voltage, industry is general to be adopted the source of widening device to leak the expansion area to deal with.Yet, notion according to self-registered technology, the width of the leakage expansion area, source of common high voltage CMOS device is subjected to the restriction of the lateral wall width of cmos device, can't obtain for example to surpass the enough wide leakage expansion area, source of lateral wall width, moreover the width of side wall is subjected to the restriction of the gate height of cmos device again.To this, there is the way of using lithography registration to determine the source in the prior art, drains to the distance of polysilicon gate, thereby determine the width of leakage expansion area, source.But the error of lithography registration is difficult to avoid, this can make again product batch with batch consistency relatively poor.
Summary of the invention
Technical problem to be solved by this invention provides side wall of a kind of high voltage CMOS device and preparation method thereof, thereby can form the leakage expansion area, source that bigger side wall obtains broad, has improved the withstand voltage degree of high voltage power device.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of side wall of high voltage CMOS device, comprise step:
Semiconductor substrate is provided, is formed with gate oxide, grid layer and grid on it successively and increases layer;
Gate patternsization and the area formation source outside described grid are leaked the expansion area;
At whole crystal column surface deposit first side wall layer;
Described first side wall layer of etching forms first side wall respectively in the both sides of described grid;
At whole crystal column surface deposit second side wall layer;
Described second side wall layer of etching forms second side wall respectively in the outside of described first side wall, and described first, second side wall constitutes the complete side wall of described high voltage CMOS device together.
Alternatively, described Semiconductor substrate is a silicon substrate.
Alternatively, described gate oxide and grid increase layer and are silicon dioxide, and described grid layer is a polysilicon.
Alternatively, described first side wall layer is a silicon dioxide, and described second side wall layer is a polysilicon.
Alternatively, the width of described side wall is 1.5～2.5 times of described gate height.
Alternatively, described silicon substrate is a N type silicon epitaxy layer substrate.
Correspondingly, the present invention also provides a kind of side wall of high voltage CMOS device, second side wall that comprises first side wall that lays respectively at the grid both sides and lay respectively at described first side wall outside, wherein said grid comprises that successively grid increases layer, grid layer and gate oxide, and described first, second side wall constitutes the complete side wall of described high voltage CMOS device together.
Alternatively, described gate oxide and grid increase layer and are silicon dioxide, and described grid layer is a polysilicon.
Alternatively, described first side wall is a silicon dioxide, and described second side wall is a polysilicon.
Alternatively, the width of described side wall is 1.5～2.5 times of described gate height.
Compared with prior art, the present invention has the following advantages:
The present invention obtains the big side wall of high voltage power device by making twice grid curb wall, has realized under self-registered technology the symmetry of leakage expansion area, source being widened, and has improved the withstand voltage degree of high voltage power device.Method of the present invention not only technology simple, with existing high-voltage CMOS technology compatibility fully mutually, and product batch with batch consistency fine.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, wherein:
Fig. 1 is the cross-sectional view of a high voltage CMOS device in the prior art;
Fig. 2 is the flow chart of manufacture method of side wall of the high voltage CMOS device of one embodiment of the invention;
Fig. 3 to Fig. 8 is the cross-sectional view of manufacturing process of side wall of the high voltage CMOS device of one embodiment of the invention;
Fig. 9 carries out the leakage injection of autoregistration source for the high voltage CMOS device of one embodiment of the invention after obtaining big side wall, the cross-sectional view of expansion area is leaked in the source that finally obtains broad.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Fig. 2 is the flow chart of manufacture method of side wall of the high voltage CMOS device of one embodiment of the invention.As shown in the figure, this manufacture method can start from step S201.This method comprises:
Execution in step S201 provides Semiconductor substrate, is formed with gate oxide, grid layer and grid on it successively and increases layer;
Execution in step S202 leaks the expansion area with gate patternsization and the area formation source outside grid;
Execution in step S203 is at whole crystal column surface deposit first side wall layer;
Execution in step S204, etching first side wall layer forms first side wall respectively in the both sides of grid;
Execution in step S205 is at whole crystal column surface deposit second side wall layer;
Execution in step S206, etching second side wall layer forms second side wall respectively in the outside of first side wall, and first, second side wall constitutes the complete side wall of high voltage CMOS device together.
Fig. 3 to Fig. 8 is the cross-sectional view of manufacturing process of side wall of the high voltage CMOS device of one embodiment of the invention.As shown in Figure 3, provide Semiconductor substrate 300, this Semiconductor substrate 300 can be silicon substrate, more specifically can be N type silicon epitaxy substrate.Be formed with gate oxide 301, grid layer 302 and grid on this Semiconductor substrate 300 successively and increase layer 303, this gate oxide 301 can be silicon dioxide, and grid layer 302 can be polysilicon, and grid increases layer and 303 can be silicon dioxide.
As shown in Figure 4, with the gate patternsization of high voltage CMOS device, and leakage expansion area 304, the area formation source outside grid, expansion area 304 is leaked in this source also can be called lightly doped drain (LDD).This step can adopt technology known in those skilled in the art to carry out, and just repeats no more at this.
As shown in Figure 5, at whole crystal column surface deposit first side wall layer 305, this first side wall layer 305 is used for forming first side wall 306, and its material can be silicon dioxide.
As shown in Figure 6, etching first side wall layer 305 forms first side wall 306 respectively in the both sides of grid.Described etching first side wall layer 305 also can adopt dry etching technology known in those skilled in the art to finish, and does not repeat them here.
As shown in Figure 7, at whole crystal column surface deposit second side wall layer 307, this second side wall layer 307 is used for forming second side wall 308, and its material can be polysilicon, distinguish mutually so that increase layer 303 material, make the etching of second side wall layer 307 have more selectivity with grid.
As shown in Figure 8, etching second side wall layer 307 forms second side wall 308 respectively in the outside of first side wall 306, and first, second side wall 306,308 constitutes the complete side wall of high voltage CMOS device together.In the present embodiment, the developed width of this complete side wall can reach 1.5～2.5 times of gate height, has obtained the side wall of super large, leaks the expansion area for the source that utilizes self-registered technology to obtain broad and lays the foundation.
Fig. 9 carries out the leakage injection of autoregistration source for the high voltage CMOS device of one embodiment of the invention after obtaining big side wall, the cross-sectional view of expansion area is leaked in the source that finally obtains broad.As shown in the figure, because the effect of blocking of the side wall of super large, the source and drain areas 310 of high voltage CMOS device is far away apart from gate location, also can obtain the source wideer than prior art and leak expansion area 304, has direct effect for the withstand voltage effect that improves high voltage power device.
The present invention has also described a kind of side wall of high voltage CMOS device, and as Fig. 8 or shown in Figure 9, this side wall can comprise first side wall 306 that lays respectively at the grid both sides and second side wall 308 that lays respectively at first side wall, 306 outsides.Wherein grid comprises successively that from top to bottom grid increases layer 303, grid layer 302 and gate oxide 301, and first, second side wall 306,308 constitutes the complete side wall of high voltage CMOS device together.
In the present embodiment, gate oxide 301 and grid increase layer 303 can be silicon dioxide, and grid layer 302 can be polysilicon.In addition, first side wall 306 can be silicon dioxide, and second side wall 308 can be polysilicon.The width of the side wall in the present embodiment can be 1.5～2.5 times of gate height.
The present invention obtains the big side wall of high voltage power device by making twice grid curb wall, has realized under self-registered technology the symmetry of leakage expansion area, source being widened, and has improved the withstand voltage degree of high voltage power device.Method of the present invention not only technology simple, with existing high-voltage CMOS technology compatibility fully mutually, and product batch with batch consistency fine.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of the side wall of a high voltage CMOS device comprises step:
Semiconductor substrate is provided, is formed with gate oxide, grid layer and grid on it successively and increases layer;
Gate patternsization and the area formation source outside described grid are leaked the expansion area;
At whole crystal column surface deposit first side wall layer;
Described first side wall layer of etching forms first side wall respectively in the both sides of described grid;
At whole crystal column surface deposit second side wall layer;
Described second side wall layer of etching forms second side wall respectively in the outside of described first side wall, and described first, second side wall constitutes the complete side wall of described high voltage CMOS device together.
2. the manufacture method of side wall according to claim 1 is characterized in that, described Semiconductor substrate is a silicon substrate.
3. the manufacture method of side wall according to claim 2 is characterized in that, described gate oxide and grid increase layer and be silicon dioxide, and described grid layer is a polysilicon.
4. the manufacture method of side wall according to claim 3 is characterized in that, described first side wall layer is a silicon dioxide, and described second side wall layer is a polysilicon.
5. the manufacture method of side wall according to claim 1 is characterized in that, the width of described side wall is 1.5～2.5 times of described gate height.
6. the manufacture method of side wall according to claim 2 is characterized in that, described silicon substrate is a N type silicon epitaxy layer substrate.
7. the side wall of a high voltage CMOS device, second side wall that comprises first side wall that lays respectively at the grid both sides and lay respectively at described first side wall outside, wherein said grid comprises that successively grid increases layer, grid layer and gate oxide, and described first, second side wall constitutes the complete side wall of described high voltage CMOS device together.
8. side wall according to claim 7 is characterized in that, described gate oxide and grid increase layer and be silicon dioxide, and described grid layer is a polysilicon.
9. side wall according to claim 8 is characterized in that, described first side wall is a silicon dioxide, and described second side wall is a polysilicon.
10. side wall according to claim 7 is characterized in that, the width of described side wall is 1.5～2.5 times of described gate height.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100872656A CN102184895A (en) | 2011-04-08 | 2011-04-08 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100872656A CN102184895A (en) | 2011-04-08 | 2011-04-08 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102184895A true CN102184895A (en) | 2011-09-14 |
Family
ID=44571048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100872656A Pending CN102184895A (en) | 2011-04-08 | 2011-04-08 | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102184895A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425383A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531366B1 (en) * | 2001-07-12 | 2003-03-11 | Cypress Semiconductor Corporation | Method and structure for high-voltage device with self-aligned graded junctions |
| CN1909233A (en) * | 2005-08-04 | 2007-02-07 | 联华电子股份有限公司 | Complementary metal-oxide-semiconductor transistor element and manufacturing method thereof |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN101840889A (en) * | 2009-03-19 | 2010-09-22 | 富士通微电子株式会社 | Manufacturing method of semiconductor device |
-
2011
- 2011-04-08 CN CN2011100872656A patent/CN102184895A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531366B1 (en) * | 2001-07-12 | 2003-03-11 | Cypress Semiconductor Corporation | Method and structure for high-voltage device with self-aligned graded junctions |
| CN1909233A (en) * | 2005-08-04 | 2007-02-07 | 联华电子股份有限公司 | Complementary metal-oxide-semiconductor transistor element and manufacturing method thereof |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN101840889A (en) * | 2009-03-19 | 2010-09-22 | 富士通微电子株式会社 | Manufacturing method of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425383A (en) * | 2013-09-09 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN104425383B (en) * | 2013-09-09 | 2017-07-11 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203205426U (en) | Lateral transistor | |
| CN107425046A (en) | A kind of LDMOS device and preparation method thereof | |
| KR101699585B1 (en) | High voltage semiconductor device and method of manufacturing the same | |
| CN107768423A (en) | Transverse diffusion metal oxide semiconductor field effect transistor with isolated area | |
| US20100163986A1 (en) | Semiconductor device and method for fabricating the same | |
| CN104779298A (en) | Super-junction MOSFET terminal structure and manufacturing method thereof | |
| JP6618615B2 (en) | Laterally diffused metal oxide semiconductor field effect transistor | |
| CN105845727B (en) | A kind of high voltage semiconductor device and its manufacturing method | |
| CN104124274A (en) | Super junction lateral double diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN203617299U (en) | A double diffused metal oxide semiconductor | |
| CN103035722A (en) | Radio frequency laterally diffused metal oxide semiconductor (LDMOS) component and manufacturing method thereof | |
| CN104282762A (en) | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof | |
| CN104779295B (en) | Half super node MOSFET structure of one kind and preparation method thereof | |
| CN107785423B (en) | An LDMOS transistor structure | |
| CN102263034B (en) | High pressure MOS transistor structure in BCD technology and manufacturing method thereof | |
| CN102184895A (en) | Side wall of high-voltage complementary metal-oxide-semiconductor transistor (CMOS) device and manufacturing method thereof | |
| CN117153888B (en) | Semiconductor device and method for manufacturing the same | |
| CN102315132B (en) | High voltage transistor and preparation method thereof | |
| CN104779297A (en) | High-voltage super junction MOSFET structure and manufacturing method thereof | |
| CN103594492B (en) | Ldmos transistor and forming method thereof | |
| CN112071909A (en) | Three-dimensional metal-oxide field effect transistor and preparation method thereof | |
| CN103187300B (en) | Fin formula field effect transistor and forming method thereof | |
| CN102184867A (en) | Manufacturing method of EDMOS (Extended Drain Metal Oxide Semiconductor) device | |
| CN101908485A (en) | Method for manufacturing vertical bipolar transistor by utilizing three mask plates | |
| US8569833B2 (en) | LDMOS device structure and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110914 |