CN102184268A - Automatic inspection method for rules of electro-static discharge resisting and latch up resisting protection circuit - Google Patents
Automatic inspection method for rules of electro-static discharge resisting and latch up resisting protection circuit Download PDFInfo
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- CN102184268A CN102184268A CN 201010504474 CN201010504474A CN102184268A CN 102184268 A CN102184268 A CN 102184268A CN 201010504474 CN201010504474 CN 201010504474 CN 201010504474 A CN201010504474 A CN 201010504474A CN 102184268 A CN102184268 A CN 102184268A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000007689 inspection Methods 0.000 title abstract description 13
- 238000012795 verification Methods 0.000 claims abstract description 10
- 238000012938 design process Methods 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 claims 2
- 238000004590 computer program Methods 0.000 abstract description 3
- 238000011161 development Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004429 Calibre Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
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Abstract
The invention relates to an automatic inspection method for rules of an electro-static discharge (ESD) resisting and latch up resisting protection circuit. The method is a special method for layout verification in the integrated circuit aided design software tool, and belongs to the field of layout verification in the integrated circuit aided design software tool. In the integrated circuit layout design process, accurate verification of the electrical rules and process rules on the protection circuit should be conducted for preventing the electro-static discharge and latch up from causing the internal circuit failure. The automatic inspection method for rules of the electro-static discharge (ESD) resisting and latch up protection circuit is generated automatically through the computer program for inspection, and can finish inspecting one compete chip in very short time, greatly improves development efficiency and ensure the accuracy of the circuit.
Description
Technical field
The automatic check method of anti-electrostatic-discharge (ESD) and anti-latch-up (Latch up) holding circuit rule is a kind of specific process of layout verification in the integrated circuit Autocad instrument.The invention belongs to layout verification field in the integrated circuit Autocad instrument.
Background technology
In the integrated circuit diagram design process, cause the inefficacy of internal circuit in order to prevent static discharge and latch-up, need add corresponding protection circuit in domain, the design of these holding circuits will be followed certain circuit theory and process rule.After circuit design finishes, need carry out the verification of correctness of electricity rule and process rule to holding circuit.The main contents of checking comprise:
● the protection ring inspection of ESD device guarantees device protection ring integrality, correctness on every side.
● the commonplace components type checking in the close region of ESD device guarantees the correct of polarity.
● at the very big MOS device of width, check the reasonable correctness of its peripheral region.
● whether the resistance value of check protection ring is enough little.
● check whether power lead, ground wire be enough little to the resistance value of protection ring.
● whether the inspection hole contact is reliable fully.
At present, industry member inspection method commonly used is: according to the original description of technical papers, by manually the holding circuit of layout design being analyzed and being checked, see that whether domain is consistent with the regulation of technical papers.
The method of manual analysis has two remarkable shortcomings, and at first, along with the complexity day by day of circuit design, chip-scale constantly increases, and the workload of manual analysis is very huge, has a strong impact on design efficiency.A chip area that typically comprises ESD and Latch up holding circuit approximately is 3000 microns of 3000 microns x; if minimum feature is 0.13 micron; then this circuit has comprised millions of to up to ten million components and parts; the number of wiring figure reaches more than one hundred million especially; manually get and check that sort circuit needs experienced slip-stick artist to spend the time in an about week, influences development efficiency greatly.Secondly, it is comprehensive that hand inspection is difficult to guarantee to test, because the people has little carelessness and mistake unavoidably in analysis, can cause implicit some mistake of layout file of designing undiscovered, finally causes the chip manufacture failure.
In order to overcome the defective of hand inspection ESD and Latch up circuit; the present invention proposes the automatic check method of a kind of anti-electrostatic-discharge (ESD) and anti-latch-up (Latch up) holding circuit rule; this method is generated automatically by computer program and checks; can finish the inspection of a complete chip in a short period of time; improve development efficiency greatly, guarantee the correctness of circuit.
Summary of the invention
The present invention proposes the automatic check method of anti-electrostatic-discharge (ESD) and anti-latch-up (Latch up) holding circuit rule, main contents are as follows:
1. at the original process supporting paper of ESD and Latchup rule, be configured to the rule file of self-verifying, natural language be converted into the understandable descriptive language of computing machine:
For example, the explanation of the original process of a typical ESD rule is:
An?N+nwell?contact?region?must?be?laid?out?between?internal?pgate?and?Nchtransistors?of?width＞＝200um
In order to make above-mentioned natural language be accepted by computer program, the present invention at first is converted to foregoing description a kind of rule file of standard, and file is called esd_strp1, and it is described below:
DRC?Check?Map?PGate_internal?GDS21 tmp?1_hier.gds?maximum?results?all
DRC?Check?Map?Nwell_contact GDS22 tmp?1_hier.gds?maximum?results?all
DRC?Check?Map?WideNGate GDS23 tmp?1_hier.gds?maximum?results?all
PGate_internal{
copy?PGate_internal
}
Nwell_contact{
copy?Nwell_contact
}
WideNGate{
copy?WideNGate
}
In the above-mentioned rule description, main meaning is: three graphics hierarchy PGate_internal of needs inspection,
Nwell_contact and WideNGate output among the interim data file tmp_hier1.gds.
2. the rule file that generates at the first step utilizes the order of main flow layout verification tool to generate the intermediate data file that is used to check ESD and Latch up rule, and this intermediate data file is the domain form gds2 of industry member standard.
Still the example with previous step is an example, at rule file esd_step1, and the layout verification of operation industry member main flow
Instrument Calibre, the method for operation is as follows:
Calibre-drc?esd_step1
Behind the end of run, can require according to the rule file of the first step to generate an interim layout file tmp1_hier.gds, for next step use.
3. the intermediate data file tmp1_hier.gds that generates at previous step searches the figure of violating ESD and Latch up rule, the self-verifying of implementation rule by this method self-defining order FindClosestRegion and corresponding automatic software instrument.
The mode of searching is to be defined as follows order:
X＝FindClosestRegion?LayerA?LayerB?distance
LayerA, LayerB are graph layers, and distance is a distance value.The figure of the nearest LayerB of all figures among this command lookup distance L ayerA, if the figure of the Graph Distance LayerA of the LayerB that finds in the distance of distance, just as a result of turns back to X to the zone between the figure of the LayerB of LayerA that finds and correspondence.As shown in Figure 1, wherein the heavy line figure is the figure of WideNGate, the LayerA above the representative, and the fine line figure is the figure of PGate_internal, representing the figure of LayerB, dashed region is the result of X.
After obtaining the result of X, in the X zone, check the figure that blocks of whether regular definition, if do not block figure then report an error.As shown in Figure 2, green figure is the Nwell_contact figure, is to block figure, do not need to report an error, and the gray area of Fig. 2 does not block, and need report an error.
Description of drawings
The tablet pattern of Fig. 1 custom command FindClosestRegion and output pattern diagram
The result's diagram that reports an error of Fig. 2 rule file
Embodiment:
The first step: at the original process supporting paper of ESD and Latch up rule, be configured to the rule file of self-verifying, natural language is converted into the understandable descriptive language of computing machine.
Second step: at the rule file that the first step generates, utilize the order of main flow layout verification tool to generate the intermediate data file that is used to check ESD and Latchup rule, this intermediate data file is the domain form gds2 of industry member standard.
The 3rd step: at the intermediate data file tmp1_hier.gds of second step generation, search the figure of violating ESD and Latch up rule, the self-verifying of implementation rule by this method self-defining order FindClosestRegion and corresponding automatic software instrument.
Adopt above-mentioned steps, layout file at 3000 microns of typical 3000 microns x, the Software tool rolling inspection time only needs about 10 minutes, and the time of going again to analyze the result that reports an error approximately needs half an hour, is far smaller than the time in a week of hand inspection T.T..
Claims (1)
1. the automatic check method of anti-electrostatic-discharge and anti-latch-up holding circuit rule, its basic meaning is: in the chip design process, in order to prevent that Electrostatic Discharge and latch-up (Latch up) from damaging internal circuit, need to increase the holding circuit that prevents ESD and Latch up effect, existing method is to rely on manual method that the domain of these holding circuits is checked, workload is big and can't cover comprehensive; In order to improve channel check efficient, the present invention proposes a kind of in the layout design process method of self-verifying ESD and Latch up effect.
Concrete steps are as follows:
(1) at the original process supporting paper of ESD and Latch up rule, be configured to the rule file of self-verifying, natural language is converted into the understandable descriptive language of computing machine:
(2) rule file that generates at (1) utilizes the part order of main flow layout verification tool to generate the intermediate data file that is used to check ESD and Latch up rule, and this intermediate data file is the domain form gds2 of industry member standard;
(3) intermediate data file that generates at (2) is searched the figure of violating ESD and Latch up rule, the self-verifying of implementation rule by this method self-defining order FindClosestRegion and corresponding automatic software instrument.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010504474 CN102184268A (en) | 2010-10-13 | 2010-10-13 | Automatic inspection method for rules of electro-static discharge resisting and latch up resisting protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010504474 CN102184268A (en) | 2010-10-13 | 2010-10-13 | Automatic inspection method for rules of electro-static discharge resisting and latch up resisting protection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106290A (en) * | 2011-11-15 | 2013-05-15 | 上海华虹Nec电子有限公司 | Method of checking integrity of protection rings |
| CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
| CN106681966A (en) * | 2016-12-26 | 2017-05-17 | 北京华大九天软件有限公司 | Data-driven flat panel display (FPD) map mark rule check (MRC) device and method |
| CN118898226A (en) * | 2024-10-08 | 2024-11-05 | 中茵微电子(南京)有限公司 | A CDM ESD risk analysis method, system and electronic device for SOC internal circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521830A (en) * | 2003-02-12 | 2004-08-18 | 上海芯华微电子有限公司 | A technical method for the integration of integrated circuit design, verification and testing |
| CN1836326A (en) * | 2003-08-19 | 2006-09-20 | 索尼株式会社 | Semiconductor device and method for making the same |
| US7558720B1 (en) * | 2005-09-19 | 2009-07-07 | National Semiconductor Corporation | Dynamic computation of ESD guidelines |
-
2010
- 2010-10-13 CN CN 201010504474 patent/CN102184268A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1521830A (en) * | 2003-02-12 | 2004-08-18 | 上海芯华微电子有限公司 | A technical method for the integration of integrated circuit design, verification and testing |
| CN1836326A (en) * | 2003-08-19 | 2006-09-20 | 索尼株式会社 | Semiconductor device and method for making the same |
| US7558720B1 (en) * | 2005-09-19 | 2009-07-07 | National Semiconductor Corporation | Dynamic computation of ESD guidelines |
Non-Patent Citations (2)
| Title |
|---|
| 《Calibre Verification User"s Manual》 20071230 Mentor Graphics Calibre nmDRC/nmDRC-H 30-39 1 , * |
| 《集成电路设计》 20061230 王志功 集成电路版图设计 109-124 1 , * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106290A (en) * | 2011-11-15 | 2013-05-15 | 上海华虹Nec电子有限公司 | Method of checking integrity of protection rings |
| CN103106290B (en) * | 2011-11-15 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Method of checking integrity of protection rings |
| CN105092994A (en) * | 2014-04-30 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | ESD detection method and device and ESD debugging method and device |
| CN106681966A (en) * | 2016-12-26 | 2017-05-17 | 北京华大九天软件有限公司 | Data-driven flat panel display (FPD) map mark rule check (MRC) device and method |
| CN106681966B (en) * | 2016-12-26 | 2019-09-13 | 北京华大九天软件有限公司 | A kind of the FPD domain marking convention check device and method of data-driven |
| CN118898226A (en) * | 2024-10-08 | 2024-11-05 | 中茵微电子(南京)有限公司 | A CDM ESD risk analysis method, system and electronic device for SOC internal circuit |
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Application publication date: 20110914 |