CN102176676A - Time-domain comparator based on linear PWM (pulse width modulation) - Google Patents
Time-domain comparator based on linear PWM (pulse width modulation) Download PDFInfo
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Abstract
本发明公开了一种基于线性脉冲宽度调制的时间域比较器，是采用以下技术手段实现的：包括：采样保持电路、放电电流源、过零检测电路和D触发器，采样保持电路中采样电容的上极板连接至过零检测电路和放电电流源构成线性脉冲宽度调制电路；待比较的两个输入信号通过两个相同的线性脉冲宽度调制电路分别输入到采用对称结构的D触发器的数据和时钟输入端，在相同大小电流源放电的情况下，存储电荷较多的电容会较晚发生翻转，从而对应较大脉冲宽度的输出数字信号。本发明中采用的电容和电阻都控制在合理范围内，保证整个时间域比较器的面积足够小。降低过零检测电路的电源电压能够有效减小功耗，并且该电源电压不会影响比较精度和输入范围。
The invention discloses a time-domain comparator based on linear pulse width modulation, which is realized by adopting the following technical means: comprising: a sampling and holding circuit, a discharge current source, a zero-crossing detection circuit and a D flip-flop, and a sampling capacitor in the sampling and holding circuit The upper plate is connected to the zero-crossing detection circuit and the discharge current source to form a linear pulse width modulation circuit; the two input signals to be compared are respectively input to the data of the D flip-flop with a symmetrical structure through two identical linear pulse width modulation circuits. And the clock input terminal, in the case of the discharge of the current source of the same size, the capacitor with more stored charges will flip over later, thus corresponding to the output digital signal with a larger pulse width. The capacitors and resistors used in the present invention are all controlled within a reasonable range to ensure that the area of the entire time domain comparator is small enough. Reducing the power supply voltage of the zero-crossing detection circuit can effectively reduce power consumption, and the power supply voltage will not affect the comparison accuracy and input range.
Description
Technical field
The invention relates to a kind of time-domain comparator based on the linear impulsive width modulated, this comparator is the important module of low-power consumption analog to digital converter under the modern advanced technologies.
Technical background
Comparator is the indispensable part of analog to digital converter.The tradition comparator mainly is made up of two parts: prime amplifier (pre-amplifier) and latch (latch).Latch is used for judging the magnitude relationship of two input voltages, exports (0 or 1) in binary mode.Because non-ideal factors such as technology coupling and random error cause latch can only correctly judge two voltages that deviation is enough big, and such comparison precision is receptible far from the high-precision adc design.Therefore adopt prime amplifier that less input deviation is amplified to the scope that latch can handle and solve this problem.
Along with the evolution of chip manufacturing process, chip operating voltage reduces, and the transistor intrinsic gain reduces, and therewith accordingly, signal swing (swing) reduces, and prime amplifier gain reduces, and this also allows the design of the comparator more difficult that becomes.For the design objective that reaches analog to digital converter often needs to increase the power consumption of comparator, this does not meet the design concept of low-power consumption again.In order to solve this contradiction, voltage transitions compared to time-domain becomes a kind of viable option.
D type flip flop (D flip-flop) is used for the time-domain comparator, plays the function of latch in traditional comparator.Because d type flip flop can be judged two precedence relationships of being separated by between the very near pulse signal,, therefore not only solved this design contradiction, and reduced power consumption so do not need to add prime amplifier.Moreover, d type flip flop is as typical digital circuit, and along with the evolution of chip manufacturing process, speed is faster, and power consumption is lower.The problem that needs to solve in the time-domain comparator is that voltage signal is transformed into time-domain, pulse width modulation just.
(a kind of representational way sees reference document Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati and Franco Maloberti, " A 9.4-ENOB 1V 3.8 μ W 100KS/s SAR ADC withTime Domain Comparator ", 2008 IEEE International Solid-State Circuits Conference) be by the capacitor discharge of voltage-controlled current source to storage fixed size electric charge, bigger voltage input just can produce bigger electric current, it is less that these electric charges have been put the needed time, produces the digital signal of corresponding pulses width with this.The shortcoming that this method exists is, because voltage-controlled current source is non-linear, so corresponding pulse width modulation also is non-linear, this is determining there is the problem that changes with process deviation aspect the input reference signal.The conversion of voltage-controlled current source makes the noiseproof feature of pulse modulated circuit relatively poor, can only be operated in (100KS/s) under the lower frequency, and owing to use big resistance (125K Ω) to cause chip area bigger.
Summary of the invention
The objective of the invention is to by a kind of time-domain comparator based on the linear impulsive width modulated is provided, voltage transitions is arrived under the prerequisite of time-domain, reduce design complexities, reduce chip area and reduce power consumption, and can be used in the comparison in deadline territory in the analog to digital converter.
A kind of time-domain comparator of the present invention based on the linear impulsive width modulated, be to adopt following technological means to realize: comprising: sampling hold circuit, discharging current source, zero cross detection circuit and d type flip flop, the top crown of sampling capacitance is connected to zero cross detection circuit and discharging current source formation linear impulsive width modulation circuit in the sampling hold circuit; Two input signals to be compared are input to the data and the input end of clock of d type flip flop respectively by two identical linear impulsive width modulation circuits, wherein:
The aforementioned sample holding circuit comprises a switch S 1, PMOS pipe M4, a NMOS pipe M5 and a capacitor C, and wherein: input signal is connected to the top crown of aforementioned capacitor C through aforementioned switches S1; Aforementioned PMOS pipe M4 and NMOS pipe M5 are connected to the top crown of aforementioned capacitor C as virtual switch;
Aforementioned discharging current source comprises a NMOS pipe M1, and grid is connected and fixed biasing, and source electrode is connected to ground, and drain electrode is connected to the top crown of aforementioned capacitor C;
Aforementioned zero cross detection circuit comprises two inverter N1, N2, PMOS pipe M3, a NMOS pipe M2 and a resistance R, wherein: the source electrode of aforementioned PMOS pipe M3 is connected to an end of resistance R, and grid is controlled by sampling clock, and drain electrode is connected to the drain electrode of aforementioned NMOS pipe M2; The other end of resistance R is connected to power supply; The grid of aforementioned NMOS pipe M2 is connected to the top crown of aforementioned capacitor C, and drain electrode is by aforesaid two inverter cascades output;
Aforesaid d type flip flop need adopt symmetrical structure.
A kind of time-domain comparator based on the linear impulsive width modulated of the present invention compared with prior art, has and followingly significantly also is and beneficial effect:
Because 1: 1 current mirror design is adopted in the discharging current source, so the bigger voltage of sampling hold circuit input just can be stored more electric charge on specified capacitance, under the situation of identical big or small current source discharge, the later upset of electric capacity meeting that stored charge is more, thereby the output digital signal of corresponding big pulse duration.The size of sampling capacitance is determined according to noiseproof feature by comparing precision.The matching precision of current mirror and sampling capacitance can determine the precision of time-domain comparator.
The threshold value of zero cross detection circuit is by the transistor threshold decision that is connected on the sampling capacitance.Though process deviation can cause the skew of transistor threshold absolute value, but because this threshold value and input signal are irrelevant, so just be equivalent to add a constant offset amount simultaneously, can't influence the difference or the magnitude relationship of two voltages to be compared to reference voltage and input voltage.The matching precision of transistor threshold also can determine the precision of time-domain comparator.
In addition, electric capacity that adopts among the present invention and resistance are all controlled in the reasonable scope, guarantee that the area of whole time-domain comparator is enough little.The supply voltage that reduces zero cross detection circuit can effectively reduce power consumption, and this supply voltage can not influence comparison precision and input range.
Description of drawings
Fig. 1 is traditional comparator configuration block diagram;
Fig. 2 is a time-domain comparator configuration block diagram;
The time-domain comparator circuit figure that Fig. 3 proposes for Agnes;
The time-domain comparator configuration block diagram that Fig. 4 proposes for the present invention
The linear impulsive width modulation circuit figure that Fig. 5 proposes for the present invention
The d type flip flop circuit diagram of Fig. 6 for adopting in the embodiment of the invention;
Fig. 7 is the pulse output simulation result of pulse width modulation circuit under different input voltages in the present embodiment;
Fig. 8 is the simulation result of pulse width modulation circuit respective pulses width under different input voltages in the present embodiment.
Symbol description
41: sampling hold circuit; 42: the discharging current source;
51: Redundanter schalter (dummy switch);
Specific implementation method
Linear impulsive width modulation circuit in the embodiment of the invention such as Fig. 4, shown in Figure 5.Comprise: sampling hold circuit, discharging current source and zero cross detection circuit.
Comprise: sampling hold circuit, discharging current source, zero cross detection circuit and d type flip flop, the top crown of sampling capacitance is connected to zero cross detection circuit and discharging current source formation linear impulsive width modulation circuit in the sampling hold circuit; Two input signals to be compared are input to the data and the input end of clock of d type flip flop respectively by two identical linear impulsive width modulation circuits, wherein:
The aforementioned sample holding circuit comprises a switch S 1, PMOS pipe M4, a NMOS pipe M5 and a capacitor C, and wherein: input signal is connected to the top crown of aforementioned capacitor C through aforementioned switches S1; Aforementioned PMOS pipe M4 and NMOS pipe M5 are connected to the top crown of aforementioned capacitor C as virtual switch;
Aforementioned discharging current source comprises a NMOS pipe M1, and grid is connected and fixed biasing, and source electrode is connected to ground, and drain electrode is connected to the top crown of aforementioned capacitor C;
Aforementioned zero cross detection circuit comprises two inverter N1, N2, PMOS pipe M3, a NMOS pipe M2 and a resistance R, wherein: the source electrode of aforementioned PMOS pipe M3 is connected to an end of aforementioned resistance R, and grid is controlled by sampling clock, and drain electrode is connected to the drain electrode of aforementioned NMOS pipe M2; The other end of aforementioned resistance R is connected to power supply; The grid of aforementioned NMOS pipe M2 is connected to the top crown of aforementioned capacitor C, and drain electrode is by aforesaid two inverter cascades output;
Aforesaid d type flip flop need adopt symmetrical structure.
Owing to do not use bottom crown Sampling techniques (bottom plate sampling) in an embodiment,, be used for offsetting the electric charge injection effect (charge injection) that produces when switch disconnects so behind sampling switch, added a pair of Redundanter schalter 51.The top crown of capacitor C is connected to sampling switch, and bottom crown is connected to ground, constitutes sampling hold circuit with this.
The discharging current source is put into ground with electric charge with fixing speed by the top crown that NMOS pipe M1 is connected to capacitor C.Vbias in all pulse width modulation circuits links together, and to use onesize M1 be identical with the modulation ratio that guarantees different units.In 0.18 micrometre CMOS process, the coupling of current source can reach 0.5%, satisfies the required precision of comparator.
Zero cross detection circuit is made up of the pull-up resistor R of NMOS pipe M2 and belt switch.In sampling process, M2 is in conducting state, at this moment its drain electrode output low level.In order to reduce power consumption, PMOS pipe M3 is placed on cut-off state by clock signal in this section process.In ensuing discharge process, M3 switches to conducting state, electric charge on the sampling capacitance reduces under the discharge of current source gradually, the also corresponding reduction of the grid voltage of M2, behind the threshold voltage that drops to M2, M2 switches to cut-off state, and at this moment pull-up resistor R can rise to supply voltage to the drain electrode of M2, digital output signal has also been finished upset, finishes the function of pulse width modulation.In order to reduce the rise and fall time of digital output signal, behind the buffer of forming through two inverters, be input to the d type flip flop of judging size again.
Adopted d type flip flop as shown in Figure 6 in an embodiment, because have the structure that piles, so be applicable to the time-domain comparator.Simulation result by Fig. 7 pulse width modulation circuit among the embodiment as can be seen can be operated in and surpasses under the frequency of 200 megahertzes; See to find out that the pulse width modulation circuit among the embodiment can be with the time-domain that is transformed into of voltage linear by the simulation result of Fig. 8.
In sum, the present invention has reached purpose of design by this embodiment, has realized having characteristics simple in structure, that area is little and low in energy consumption by the comparison of linear impulsive width modulation circuit in time-domain.The present invention is not limited to the foregoing description, can under the situation that does not depart from scope and spirit of the present invention it be made amendment and change.
Claims (2)
1. time-domain comparator based on the linear impulsive width modulated, comprise: sampling hold circuit, discharging current source, zero cross detection circuit and d type flip flop is characterized in that: the top crown of sampling capacitance is connected to zero cross detection circuit and discharging current source formation linear impulsive width modulation circuit in the sampling hold circuit; Two input signals to be compared are input to the data and the input end of clock of d type flip flop respectively by two identical linear impulsive width modulation circuits, wherein:
Described sampling hold circuit comprises a switch (S1), a PMOS pipe (M4), NMOS pipe (M5) and an electric capacity (C), and wherein: input signal is connected to the top crown of electric capacity (C) through described switch (S1); Described PMOS pipe (M4) and NMOS pipe (M5) are connected to the top crown of electric capacity (C) as virtual switch;
Described discharging current source comprises a NMOS pipe (M1), and grid is connected and fixed biasing, and source electrode is connected to ground, and drain electrode is connected to the top crown of electric capacity (C);
Described zero cross detection circuit comprises two inverters (N1), (N2), a PMOS pipe (M3), NMOS pipe (M2) and a resistance (R), wherein: the source electrode of PMOS pipe (M3) is connected to an end of resistance (R), grid is controlled by sampling clock, and drain electrode is connected to the drain electrode of NMOS pipe (M2); The other end of resistance (R) is connected to power supply; The grid of NMOS pipe (M2) is connected to the top crown of described electric capacity (C), and drain electrode is by described two inverter cascades output.
2. the time-domain comparator based on the linear impulsive width modulated as claimed in claim 1 is characterized in that: the d type flip flop that adopts symmetrical structure.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102647184A (en) * | 2012-04-28 | 2012-08-22 | 北京握奇数据系统有限公司 | Phase-locked loop, active radio frequency identification (RFID) label, double-interface card and control method of phase-locked loop |
| CN104092465A (en) * | 2014-03-24 | 2014-10-08 | 北京大学 | A Wide Input Swing Flash ADC Circuit Based on Time Domain Comparator |
| CN111030698A (en) * | 2019-12-08 | 2020-04-17 | 复旦大学 | Voltage-to-Time Converter with Discrete Gain |
| CN111669137A (en) * | 2020-04-27 | 2020-09-15 | 上海交通大学 | An adaptive variable gain delay amplifier |
| CN112147421A (en) * | 2019-06-27 | 2020-12-29 | 意法半导体股份有限公司 | Pulse width check circuit for laser diode pulse generator |
| CN113037275A (en) * | 2021-03-17 | 2021-06-25 | 东南大学 | Multi-input time domain analog signal width quantizer |
| CN113238204A (en) * | 2021-05-07 | 2021-08-10 | 上海嘉沃光电科技有限公司 | Laser pulse detection and measurement input stage circuit |
| CN119363092A (en) * | 2024-12-20 | 2025-01-24 | 成都电科星拓科技有限公司 | A novel time offset calibration circuit and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920471A (en) * | 1996-08-30 | 1999-07-06 | Sgs-Thomson Microelectronics, Srl | Method and apparatus for automatic average current mode controlled power factor correction without input voltage sensing |
| CN101231192A (en) * | 2007-01-23 | 2008-07-30 | Ulis股份公司 | Method for digitizing an analog quantity, digitizing device and electromagnetic radiation detector |
| CN101320975A (en) * | 2008-06-06 | 2008-12-10 | 清华大学 | Ultra-low power consumption comparer based on time domain |
| CN101500095A (en) * | 2008-01-29 | 2009-08-05 | 索尼株式会社 | Solid-state image sensing device, method for reading signal of solid-state image sensing device, and image pickup apparatus |
-
2011
- 2011-03-18 CN CN2011100663186A patent/CN102176676A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920471A (en) * | 1996-08-30 | 1999-07-06 | Sgs-Thomson Microelectronics, Srl | Method and apparatus for automatic average current mode controlled power factor correction without input voltage sensing |
| CN101231192A (en) * | 2007-01-23 | 2008-07-30 | Ulis股份公司 | Method for digitizing an analog quantity, digitizing device and electromagnetic radiation detector |
| CN101500095A (en) * | 2008-01-29 | 2009-08-05 | 索尼株式会社 | Solid-state image sensing device, method for reading signal of solid-state image sensing device, and image pickup apparatus |
| CN101320975A (en) * | 2008-06-06 | 2008-12-10 | 清华大学 | Ultra-low power consumption comparer based on time domain |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102647184A (en) * | 2012-04-28 | 2012-08-22 | 北京握奇数据系统有限公司 | Phase-locked loop, active radio frequency identification (RFID) label, double-interface card and control method of phase-locked loop |
| CN104092465A (en) * | 2014-03-24 | 2014-10-08 | 北京大学 | A Wide Input Swing Flash ADC Circuit Based on Time Domain Comparator |
| CN104092465B (en) * | 2014-03-24 | 2017-02-22 | 北京大学 | Wide-input-amplitude Flash ADC circuit based on time domain comparators |
| CN112147421A (en) * | 2019-06-27 | 2020-12-29 | 意法半导体股份有限公司 | Pulse width check circuit for laser diode pulse generator |
| CN111030698A (en) * | 2019-12-08 | 2020-04-17 | 复旦大学 | Voltage-to-Time Converter with Discrete Gain |
| CN111030698B (en) * | 2019-12-08 | 2023-04-07 | 复旦大学 | Voltage-to-time converter with discrete gain |
| CN111669137A (en) * | 2020-04-27 | 2020-09-15 | 上海交通大学 | An adaptive variable gain delay amplifier |
| CN111669137B (en) * | 2020-04-27 | 2022-02-11 | 上海交通大学 | Self-adaptive variable gain delay amplifier |
| CN113037275A (en) * | 2021-03-17 | 2021-06-25 | 东南大学 | Multi-input time domain analog signal width quantizer |
| CN113238204A (en) * | 2021-05-07 | 2021-08-10 | 上海嘉沃光电科技有限公司 | Laser pulse detection and measurement input stage circuit |
| CN119363092A (en) * | 2024-12-20 | 2025-01-24 | 成都电科星拓科技有限公司 | A novel time offset calibration circuit and method |
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Application publication date: 20110907 |