CN102176498A - Manufacturing method of LED chip - Google Patents
Manufacturing method of LED chip Download PDFInfo
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- CN102176498A CN102176498A CN 201110069891 CN201110069891A CN102176498A CN 102176498 A CN102176498 A CN 102176498A CN 201110069891 CN201110069891 CN 201110069891 CN 201110069891 A CN201110069891 A CN 201110069891A CN 102176498 A CN102176498 A CN 102176498A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims description 31
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 238000004513 sizing Methods 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 102220082690 rs863224215 Human genes 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 239000011810 insulating material Substances 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
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- 230000000873 masking effect Effects 0.000 description 9
- 229910052594 sapphire Inorganic materials 0.000 description 7
- 239000010980 sapphire Substances 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 6
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- 238000001259 photo etching Methods 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- 238000013461 design Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
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- 238000001704 evaporation Methods 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 238000001883 metal evaporation Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a manufacturing method of an LED chip, wherein a procedure of removing one part of an epitaxial layer comprises the following steps of: forming a first mask film layer on the epitaxial layer, wherein the first mask film layer comprises a plurality of mask film layer units isolated from one another, and a first clearance with a predetermined size is arranged among the mask film layer units; removing a second semiconductor layer, a lighting layer and one part of a first semiconductor layer from a region where the first clearance is located to form a groove; eliminating the first mask film layer; repeating the steps for N times to remove parts of the epitaxial layer and a buffer layer until reaching a substrate, reserving an Nth clearance with predetermined size among the mask film layer units, wherein the width of the Nth clearance is greater than that of a (N-1)th clearance; forming an isolating groove with N steps, wherein N is not smaller than 2. By applying the technical scheme of the invention, the isolating groove has smaller depth and greater width as well as a certain inclination degree, thereby being beneficial to the coverage of an insulating material and the adhesion of metal connection wires, and solving the problem of breakage probably caused when the metal connection wires cross a deeper groove.
Description
Technical field
The present invention relates to the manufacture method of light-emitting device array, in particular to a kind of manufacture method of led chip.
Background technology
With respect to high-power chip, the middle low power chip has good light efficiency and heat dispersion and higher reliability owing to adopt little current drives, uses very extensive in illumination and floor light field.In order to obtain enough brightness and illumination, just need abundant LED lamp pearl is welded on substrate or the printed circuit board (PCB) by series-parallel mode, i.e. encapsulation earlier, the back is integrated.Array high-voltage alternating led chip has a plurality of LED structure cells (sub-chip), and is to satisfy specific electrical demands, promptly earlier integrated according to the suitable serial or parallel connection of demand, the back encapsulation.
Good conductive ability in view of N type GaN, obtain discrete device, then the N type GaN between each structure cell must be removed and form the electric isolation groove, then between isolation channel and structure cell, form insulating barrier, on insulating barrier, form electricity at last and connect with each structure cell of electric insulation.Realize above-mentioned purpose, under the prior art condition, at first need to form the electrical isolation groove until Sapphire Substrate with the N type GaN that communicates with each other is partially-etched, do not damage P type GaN and transparency electrode on the luminous zone simultaneously.
Existing technological means, can realize the formation of isolation channel by the ICP etching, but need be with the GaN etching until Sapphire Substrate, etching depth just need reach (5-7 μ m) more than 5 microns, when carrying out the ICP etching, very high requirement has just been proposed masking layer like this, can adopt modes such as evaporation to form metal shadowing layers such as nickel, gold on the conventional art, carry out the ICP etching behind the lithography stripping.The forming process of considering masking layer is numerous and diverse, and the heat that produces of long-time plasma bombardment device surface and to the damage that device brings, and makes this method have many drawbacks in normal production process.
In addition, the metal interconnection line that forms by modes such as electron beam evaporation or chemical gildings ruptured when crossing over dark isolation channel easily, especially comparatively vertical sidewall, thus have influence on led chip connection to each other.General solution is adopt to electroplate, change means such as plating increase electric connection line thickness with fill up isolation channel cause can be complete cover on the sidewall.Too high electric connection line may cause coming off easily in follow-up attenuate cutting, has also increased production cost simultaneously, and complex procedures, reliability also can't ensure.
And for example brilliant first photoelectricity is 200810169439.1 in the patent No.＜make the method for light emitting array in described and can utilize insulating barrier growth speed on its horizontal direction when forming to seal isolation channel greater than this characteristic of vertical direction growth speed, prerequisite is the twice that the width of isolation channel is not more than thickness of insulating layer.According to understanding in its Figure of description, according to institute's qualification of above-mentioned " flakiness ratio ", then necessarily requiring can only be to form very narrow isolation channel, and perhaps extremely thick insulating barrier just might satisfy the qualification requirement of " flakiness ratio ".Narrow isolation channel has proposed great challenge to photoetching process, ICP lithographic technique and macking technique thereof, and the film that relies on the micron order thickness that methods such as vapour deposition, evaporation, sputter form is also often consuming time and be difficult to control, even set up time groove, the reliability of its technical enforcement difficulty and final products is not suitable for mass production yet.
Summary of the invention
The present invention aims to provide a kind of manufacture method of led chip, plasma bombards device surface and the heat that produces brings damage to device for a long time when forming isolation channel to solve the following technical problem that exists in the prior art: ICP, and masking layer is required high, generally need metal shadowing layers such as nickel, gold, the forming process of this masking layer is numerous and diverse; And the metal interconnection line ruptures when crossing over the isolation channel more deeply, especially have vertical sidewall comparatively easily, has influence on led chip technical problems such as connection to each other.
The manufacture method of led chip provided by the invention may further comprise the steps: step S10, substrate is provided, and form resilient coating on substrate; Step S20 forms epitaxial loayer on resilient coating, specifically may further comprise the steps: step S21, form first semiconductor layer on resilient coating, and step S22 forms luminescent layer on first semiconductor layer, and step S23, forms second semiconductor layer on luminescent layer; Step S30 removes part epitaxial loayer and resilient coating to substrate, forms isolation channel, and isolation channel is divided into a plurality of sub-chips with chip; And step S40, installing electrodes and finish interelectrode being electrically connected on epitaxial loayer; Wherein, step S30 removes the part epitaxial loayer and may further comprise the steps: step S31, on epitaxial loayer, form first mask layer, and first mask layer comprises a plurality of spaced mask layers unit, leaves first gap of pre-sizing between each mask layer unit; Step S32 removes second semiconductor layer of region, first gap, and luminescent layer and part first semiconductor layer are to form groove; Step S33 removes first mask layer; Repeating step S30N time removes the part epitaxial loayer to substrate, wherein among the step S31, leaves the N gap of pre-sizing between each mask layer unit, and the width in N gap forms the isolation channel with N step, N 〉=2 greater than the width in N-1 gap.
Preferably, N equals 3.
Further, the width of reserving first gap among the step S31 between each unit of first mask layer is 5～15 μ m.
Further, among the step S32, remove second semiconductor layer, the degree of depth of luminescent layer and part first semiconductor layer is 2～3 μ m.
Further, mask layer is by SiO
2, chromium, nickel or photoresist make.
Further, mask layer is made by photoresist.
Further, remove second mask layer after, on second semiconductor layer, form transparency conducting layer, on the sidewall of on the isolation channel and the transparency conducting layer edge, second semiconductor layer, luminescent layer and first semiconductor layer, form electric insulation layer.
Further, electric insulation layer is reserved with for finishing the through hole that the electric connection line that is electrically connected passes through.
Further, in installing electrodes on the epitaxial loayer and finish interelectrode being electrically connected specifically and may further comprise the steps: on first semiconductor layer, form first electrode; On second semiconductor layer, form second electrode; And finish being electrically connected between first electrode and second electrode between each unit.
Use technical scheme of the present invention, adopt the method for step-etching, cooperate photoresist as masking material, technology is simple relatively, realize easily, and the step isolation channel that forms possesses the more shallow degree of depth, bigger width, certain angle of inclination, help the covering of insulating material, adhering to of metal connecting line, solved the breakage problem that may cause when the metal interconnection line is crossed over darker groove.
Description of drawings
Figure of description is used to provide further understanding of the present invention, constitutes a part of the present invention, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, does not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 to Fig. 6 shows the manufacture method schematic diagram of led chip of the present invention; And
Fig. 7 shows the structural representation of two sub-chips of series LED.
Embodiment
Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the present invention can make up mutually.Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
The manufacture method of led chip provided by the invention may further comprise the steps:
As shown in Figure 1, provide substrate 10; Wherein substrate 10 is sapphire materials.Form resilient coating 20 on substrate 10, resilient coating 20 is made by plain gallium nitride simple substance.Form epitaxial loayer 30 on resilient coating 20, specifically may further comprise the steps: form first semiconductor layer 31 on resilient coating 20, form luminescent layer 32 on first semiconductor layer 31, and form second semiconductor layer 33 on luminescent layer 32.On the epitaxial loayer 30 after the process surface clean, form first mask layer, 41, the first mask layers 41 and comprise a plurality of spaced mask layers unit, leave first gap of pre-sizing between each mask layer unit.Need according to concrete design, the width of reserving first gap between first mask layer, 41 each unit is made as 5～15 μ m.Wherein, the material of mask layer can be SiO
2, chromium, nickel, photoresist or other mask materials, preferably, with photoresist as mask material.On the one hand, because photoresist itself also can be used as the masking material of ICP etching, the yield height is easily removed in easily processing; On the other hand, use other materials such as silica, need utilize photoresist to do the transfer of a figure, wet etching just, the present invention directly adopts photoresist convenient as mask material; Again on the one hand, the present invention is intended to solve the metal wire breakage problem that causes too deeply owing to isolation channel, and photoresist is easy to do in echelon, the inclined-plane that promptly has the gradient, like this through after the ICP etching, be easy to the sidewall of isolation channel is done aslope rather than vertical, so just more help adhering to and being connected of metal wire.
As shown in Figure 1, 2, process ICP removes second semiconductor layer 33, luminescent layer 21, part first semiconductor layer 31 of region, first gap, forms first groove of the degree of depth at 2-3 μ m on epitaxial loayer 30, removes first mask layer 41.
As shown in Figure 3, form on epitaxial loayer 30, form second masking layer 42, the size restrictions of this second mask layer 42 is in the profile scope of first mask layer 41 shown in Figure 1, and the 5-15 μ m that contracts in the edge is good.
Shown in Fig. 3,4, ICP etching for the second time, the degree of depth is 2-3 μ m, forms second groove, this moment first groove by further downwards etching reach the degree of depth of 4-6 μ m, form ladder between first groove and second groove, comprise first groove in second groove.Then, remove second mask layer 42.
As shown in Figure 5, form on epitaxial loayer 30, form the 3rd mask layer 43, through making first, second groove and part second semiconductor layer exposed after the technologies such as photoetching, chemical etching, promptly the 3rd mask layer 43 edges are than the 5-15 μ m that contracts in second mask layer 42.
Shown in Fig. 5,6, ICP etching for the third time, the degree of depth is 1.2-1.8 μ m, forms the 3rd groove, this moment, groove was etched to Sapphire Substrate, realized the electrical isolation of chip chamber.First groove, second groove and the 3rd groove three form the isolation channel with certain angle of inclination step; Remove the 3rd mask layer 43.
As shown in Figure 7, on second semiconductor layer 33, form transparency conducting layer 54, on the isolation channel, the transparency conducting layer edge 54 and first semiconductor layer 31, luminescent layer 32, second semiconductor layer, 33 sidewalls form electric insulation layer 60, electric insulation layer 60 thickness 5000-10000 dusts.Electric insulation layer 60 is reserved with for finishing the through hole that the electric connection line that is electrically connected passes through.On first semiconductor layer 31, form first electrode 51; On second semiconductor layer 33, form second electrode 52; Finish being electrically connected between first electrode and second electrode between each unit.
Further, form electrode and electric connection line by chemical vapour deposition technique, physical vaporous deposition, electron beam evaporation plating method, change plating or electro-plating method.
The isolation channel that adopts method provided by the invention to form has the more shallow degree of depth, bigger width, certain angle of inclination, helps adhering to of insulating barrier, and can guarantee that metal wire crosses over unlikely fracture; The present invention adopts the method for step-etching, cooperates photoresist as masking material, and technology is simple, and the device damage that can effectively avoid the long-time physical chemistry etching of chip to bring; Adopt thin metal material to form electrical cable, saved cost; The insulating barrier that the present invention does not need to form big thickness covers table top and sidewall, also can obtain the good insulation performance effect and unlikely short circuit; Adopt technical scheme of the present invention, can reduce production costs on the whole, improve the operability and the reliability of products of technology.
Embodiment one
Sapphire substrate is provided, forms resilient coating on substrate; On resilient coating, form epitaxial loayer, specifically may further comprise the steps: form first semiconductor layer on resilient coating, form luminescent layer on first semiconductor layer, and form second semiconductor layer on luminescent layer.Forming first mask layer on through the epitaxial loayer after the surface clean, is 10 μ m according to design with the width of reserving first gap between each unit of first mask layer.Wherein, the material of mask layer can be a photoresist.
Process ICP removes second semiconductor layer, luminescent layer, part first semiconductor layer of first interstitial site, forms first groove of the degree of depth at 2 μ m on the epitaxial loayer, removes first mask layer.
Form on epitaxial loayer, form second masking layer, the size restrictions of this second mask layer is in the profile scope of first mask layer, and the 5 μ m that contract in the edge.
ICP etching for the second time, the degree of depth is 2 μ m, forms second groove, this moment first groove by further downwards etching reach the degree of depth of 4 μ m, form ladder between first groove and second groove, comprise first groove in second groove.Then, remove second mask layer.
Form on epitaxial loayer, form the 3rd mask layer, through making first, second isolation channel and part second semiconductor layer exposed after the technologies such as photoetching, chemical etching, the 3rd mask layer edge is than the 5 μ m that contract in second mask layer.
ICP etching for the third time, the degree of depth is 1.2 μ m, forms the 3rd groove, this moment, groove was etched to Sapphire Substrate, realized the electrical isolation of chip chamber.First groove, second groove and the 3rd groove three form the isolation channel with certain angle of inclination step; Remove the 3rd mask layer.
Form transparency conducting layer on second semiconductor layer, on the isolation channel, the transparency conducting layer edge and first semiconductor layer, luminescent layer, the second semiconductor layer sidewall form electric insulation layer, electric insulation layer thickness 5000 dusts.Electric insulation layer is reserved with for finishing the through hole that the electric connection line that is electrically connected passes through.On first semiconductor layer, form first electrode; On second semiconductor layer, form second electrode; Finish being electrically connected between first electrode and second electrode between each unit.Form electrode and electric connection line by chemical vapour deposition technique.
Embodiment two
Sapphire substrate is provided; On substrate, form resilient coating, on resilient coating, form epitaxial loayer, specifically may further comprise the steps: form first semiconductor layer on resilient coating, form luminescent layer on first semiconductor layer, and form second semiconductor layer on luminescent layer.All the other methods of operation are with embodiment one, difference is, the width in first gap is 15 μ m, forms first groove of the degree of depth 3 μ m on the epitaxial loayer, and the second mask layer edge is than the 15 μ m that contract in first mask layer, ICP etching for the second time, the degree of depth is 3 μ m, and the 3rd mask layer edge is than 15 μ m, the ICP etching for the third time of contracting in second mask layer, the degree of depth is 1.5 μ m, and electric insulation layer thickness is 8000 dusts.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the manufacture method of a led chip may further comprise the steps:
Step S10 provides substrate, forms resilient coating on described substrate;
Step S20 forms epitaxial loayer on described resilient coating, specifically may further comprise the steps:
Step S21 forms first semiconductor layer on described resilient coating,
Step S22 forms luminescent layer on described first semiconductor layer, and
Step S23 forms second semiconductor layer on described luminescent layer;
Step S30 removes described epitaxial loayer of part and resilient coating to described substrate, forms isolation channel, and described isolation channel is divided into a plurality of sub-chips with described chip; And
Step S40, installing electrodes and finish interelectrode being electrically connected on described epitaxial loayer;
It is characterized in that described step S30 removes the described epitaxial loayer of part and may further comprise the steps:
Step S31 forms first mask layer on described epitaxial loayer, described first mask layer comprises a plurality of spaced mask layers unit, leaves first gap of pre-sizing between each mask layer unit;
Step S32 removes described second semiconductor layer of region, described first gap, and luminescent layer and part first semiconductor layer are to form groove;
Step S33 removes described first mask layer;
Repeating said steps S30N time removes described epitaxial loayer of part and resilient coating to described substrate, wherein among the step S31, leave the N gap of pre-sizing between each mask layer unit, the width in N gap forms the isolation channel with N step, N 〉=2 greater than the width in N-1 gap.
2. manufacture method according to claim 1 is characterized in that described N equals 3.
3. manufacture method according to claim 1 is characterized in that, the width in first gap is 5～15 μ m among the described step S31.
4. manufacture method according to claim 3 is characterized in that, among the described step S32, removes second semiconductor layer described first time, and the degree of depth of luminescent layer and part first semiconductor layer is 2～3 μ m.
5. according to each described manufacture method of claim 1-4, it is characterized in that described mask layer is by SiO
2, chromium, nickel or photoresist make.
6. manufacture method according to claim 5 is characterized in that described mask layer is made by photoresist.
7. manufacture method according to claim 1, it is characterized in that, after removing described N mask layer, on described second semiconductor layer, form transparency conducting layer, on the sidewall of on the described isolation channel and described transparency conducting layer edge, second semiconductor layer, luminescent layer and first semiconductor layer, form electric insulation layer.
8. manufacture method according to claim 7 is characterized in that, described electric insulation layer is reserved with for finishing the through hole that the electric connection line that is electrically connected passes through.
9. manufacture method according to claim 1 is characterized in that, described step S40 specifically may further comprise the steps:
Step S41 forms first electrode on each unit of described first semiconductor layer;
Step S42 forms second electrode on described second semiconductor layer; And
Step S43 finishes being electrically connected between first electrode and second electrode between each unit.
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| CN 201110069891 CN102176498B (en) | 2011-03-22 | 2011-03-22 | Manufacturing method of LED chip |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103700741A (en) * | 2012-09-28 | 2014-04-02 | 上海蓝光科技有限公司 | Low-voltage power-type LED (Light-emitting Diode) with large current density and manufacture method thereof |
| CN103730431A (en) * | 2014-01-07 | 2014-04-16 | 宝钢金属有限公司 | High-power array light-emitting diode (LED) chip surface radiating structure and manufacturing method |
| CN104037296A (en) * | 2013-03-07 | 2014-09-10 | 百士杰企业有限公司 | Light emitting element and manufacturing method thereof |
| CN105023932A (en) * | 2014-04-29 | 2015-11-04 | 新灯源科技有限公司 | Vertical LED array element integrated with LED package substrate by being combined with LED epitaxial structures |
| WO2015196340A1 (en) * | 2014-06-23 | 2015-12-30 | 华为技术有限公司 | Chip heat dissipation structure and terminal device |
| CN105633224A (en) * | 2016-01-04 | 2016-06-01 | 厦门市三安光电科技有限公司 | LED chip electrode, LED chip structure and fabrication methods of LED chip electrode and LED chip structure |
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| CN103066172B (en) * | 2011-10-24 | 2017-04-12 | Lg伊诺特有限公司 | Light emitting device |
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| WO2015196340A1 (en) * | 2014-06-23 | 2015-12-30 | 华为技术有限公司 | Chip heat dissipation structure and terminal device |
| CN105655450A (en) * | 2014-11-13 | 2016-06-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Passivation layer deposition method of high-voltage LED chip |
| CN105655450B (en) * | 2014-11-13 | 2019-01-18 | 北京北方华创微电子装备有限公司 | The passivation layer deposition method of high voltage LED chip |
| CN106206900A (en) * | 2015-05-08 | 2016-12-07 | 广东德力光电有限公司 | A kind of highlighted packed LED chip |
| CN105633224A (en) * | 2016-01-04 | 2016-06-01 | 厦门市三安光电科技有限公司 | LED chip electrode, LED chip structure and fabrication methods of LED chip electrode and LED chip structure |
| CN107768490A (en) * | 2017-10-26 | 2018-03-06 | 江苏新广联半导体有限公司 | A kind of preparation method for optimizing GaN base LED core piece performance |
| CN107768490B (en) * | 2017-10-26 | 2020-07-10 | 江苏新广联半导体有限公司 | Preparation method for optimizing performance of GaN-based L ED chip |
| CN111725251A (en) * | 2020-07-04 | 2020-09-29 | 厦门友来微电子有限公司 | High-resolution full-color MicroLED display |
| CN111725251B (en) * | 2020-07-04 | 2023-04-21 | 深圳市惠合显示有限公司 | High-resolution full-color MicroLED display |
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