CN102169861A

CN102169861A - Semiconductor structure with passive device structure and method of manufacturing the same

Info

Publication number: CN102169861A
Application number: CN2011100374824A
Authority: CN
Inventors: 施旭强; 李德章; 谢孟伟
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2011-02-01
Filing date: 2011-02-01
Publication date: 2011-08-31

Abstract

A semiconductor structure with a passive component structure and a manufacturing method thereof. The semiconductor structure includes an insulating substrate, a passive component structure layer, an electrical contact and a dielectric layer. The passive component structure layer is formed on the insulating substrate. The electrical contact is formed on the passive component structure layer. The dielectric layer covers a portion of the electrical contact, and another portion of the electrical contact is exposed from an opening of the dielectric layer.

Description

Semiconductor structure and manufacture method thereof with passive component structure

Technical field

The invention relates to a kind of semiconductor structure and manufacture method thereof, and particularly relevant for a kind of semiconductor structure and manufacture method thereof with passive component.

Background technology

Traditional interposer substrate (interposer) comprises a silicon substrate, an insulating barrier and a line layer.Insulating barrier is formed on the silicon substrate, and line layer is formed on the insulating barrier.Because silicon substrate do not have insulating properties, therefore need to isolate line layer and silicon substrate via insulating barrier, make line layer and unlikely the electrically conducting of silicon substrate and cause short circuit.

Yet derive at least one light shield technology cost of the formation of insulating barrier causes technology cost and process complexity to increase.

Summary of the invention

The present invention is relevant for a kind of semiconductor structure and manufacture method thereof, and semiconductor structure adopts the substrate of tool insulating properties, can reduce the formation of insulating barrier, to reduce manufacturing cost, to save the process time.

According to an aspect of the present invention, a kind of semiconductor structure is proposed.Semiconductor structure comprises an insulated substrate, a passive component structure layer, one first electrical contact and one first dielectric layer.The passive component structure layer is formed at insulated substrate.First electrical contact is formed at the passive component structure layer.First dielectric layer covers the part of first electrical contact, and wherein, first dielectric layer has one first perforate, and another part of first electrical contact exposes from first perforate.

A kind of manufacture method of semiconductor structure is proposed according to a further aspect in the invention.Manufacture method may further comprise the steps.One insulated substrate is provided; Form a passive component structure layer in insulated substrate; Form one first electrical contact in the passive component structure layer; And, form the part that one first dielectric layer covers first electrical contact, wherein first dielectric layer has one first perforate, and another part of first electrical contact exposes from first perforate.

For there is better understanding above-mentioned and other aspect of the present invention, at least one embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings

Figure 1A illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.

Figure 1B illustrates the enlarged diagram of local 1B ' among Figure 1A.

Fig. 2 illustrates the top view of resistance among Fig. 1, electric capacity and induction structure.

Fig. 3 illustrates the cutaway view according to the semiconductor structure of yet another embodiment of the invention.

Fig. 4 illustrates the cutaway view according to the semiconductor structure of other embodiment of the present invention.

Fig. 5 illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.

Fig. 6 A illustrates the cutaway view according to the semiconductor structure of further embodiment of this invention.

Fig. 6 B illustrates the enlarged diagram of local 6B ' among Fig. 6 A.

Fig. 7 A to 7G illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.

Fig. 8 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.

Fig. 9 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 4.

Figure 10 illustrates the top view of the circulus of Fig. 9.

Figure 11 illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 5.

Figure 12 A to 12D illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 6 A.

The primary clustering symbol description:

100,200,300,400,500: semiconductor structure

102,302: insulated substrate

102a, 112b, 302a: first

102b, 302b: second

104,204,304: the passive component structure layer

106,206,306: the first electrical contact

106a: the part of first electrical contact

106a1,106b1,108b: upper surface

106b: another part of first electrical contact

108,208,308: the first dielectric layers

108a: first perforate

110: the first line layers

110a: first conductive layer

110b: second conductive layer

110c: capacitance dielectric layer

110d: the 3rd conductive layer

112,312: the second dielectric layers

112a: second perforation

112c: the second perforation madial wall

114: the second Seed Layer

114a: another part of second Seed Layer

114s, 320s: side

116,216: the second line layers

116a, 216a: expose upper surface

116a1 a: part of exposing upper surface

116a2: the another part that exposes upper surface

122,124: the patterning photoresist layer

122a: form the district

302c: first perforation

302d: the first perforation madial wall

318: the second electrical contact

318a: the part of second electrical contact

318b: another part of second electrical contact

320: the first Seed Layer

326: support plate

428,528: circulus

530: organic polymer material

C: capacitance structure

L: induction structure

P: Cutting Road

R: electric resistance structure

RP: cellular zone

Embodiment

Used herein " vicinity " expression near or link together.Adjacent assembly can separated from each other or directly be connected to each other.In some instances, adjacent assembly can refer to be connected to each other or integrated to each other assembly.

Please refer to Figure 1A and Figure 1B, Figure 1A illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention, and Figure 1B illustrates the enlarged diagram of local 1B ' among Figure 1A.Shown in Figure 1A, semiconductor structure 100 comprises insulated substrate 102, passive component structure layer 104, first electrical contact 106 and first dielectric layer 108.

Insulated substrate 102 for example is that glass substrate, ceramic substrate or other possess the substrate of insulating properties.Because the insulation characterisitic of insulated substrate 102 so passive component structure layer 104 is formed directly on the insulated substrate 102, can reduces the technology cost, reduces the complex process degree and improve the technology yield.

The passive component structure layer is formed on the insulated substrate, and first electrical contact is formed on the passive component structure layer.For example, insulated substrate 102 has relative first 102a and second 102b.Passive component structure layer 104 is formed on first 102a of insulated substrate 102, and first electrical contact 106 is formed on the passive component structure layer 104.First 102a and second 102b are respectively the upper surface and the lower surface of insulated substrate 102 in the present embodiment.

First electrical contact 106 can be single layer structure or sandwich construction, and its material is comprising tin (immersion Sn), change silver (immersion Ag), chemical nickel and gold (ENIG), copper facing, plating iron, nickel plating or organic weldering film (OSP) at least; Perhaps, first electrical contact 106 also can be made up of the group that copper (Cu), nickel (Ni), palladium (Pd) and gold (Au) are constituted; Perhaps, and bump metal bottom first electrical contact 106 also can be (Under Bump Metallization, UBM).

First dielectric layer is suppressed first electrical contact, and first electrical contact firmly is formed on the passive component structure layer.For example, first dielectric layer 108 covers a part of 106a of first electrical contact 106, for example be the upper surface 106a1 that covers a part of 106a of first electrical contact 106, and another part 106b of first electrical contact 106 exposes.This part 106a of first dielectric layer, 108 compactings, first electrical contact 106 more securely is formed on the passive component structure layer 104 first electrical contact 106.

First dielectric layer 108 has at least one first perforate 108a, and another part 106b of first electrical contact 106 exposes from the first perforate 108a.Say further, first electrical contact 106 does not protrude in the upper surface 108b of first dielectric layer 108, but expose from the first perforate 108a, the upper surface 106b1 of another part 106b that makes the upper surface 108b of first dielectric layer 108 and first electrical contact 106 is at a distance of a distance.

The passive component structure layer comprises in resistance, inductance and the capacitance structure at least one.For example, please be simultaneously with reference to 1A, 1B and Fig. 2, Fig. 2 illustrates the top view of resistance among Fig. 1, electric capacity and induction structure, and the first conductive layer 110a, the second conductive layer 110b and the 3rd conductive layer 110d will be in follow-up (Fig. 5 A) explanations among Fig. 2.Shown in Figure 1A, passive component structure layer 104 comprises first line layer 110, second dielectric layer 112, second Seed Layer 114 and second line layer 116.First line layer 110 constitutes at least one electric resistance structure R and at least one capacitance structure C, and second line layer 116 constitutes at least one induction structure L.Specifically, first line layer 110 is formed on first 102a of insulated substrate 102, second dielectric layer 112 covers first line layer 110, wherein second dielectric layer 112 has at least one second perforation 112a, first 112b and the second perforation madial wall 112c, the second perforation 112a extends to first line layer 110 from first 112b, the second perforation madial wall 112c is corresponding to the second perforation 112a, and the part of first line layer 110 is exposed from the second perforation 112a.Second Seed Layer 114 is formed between second line layer 116 and second dielectric layer 112.

Second Seed Layer 114 has side 114s, and second Seed Layer 114 is covered fully by second line layer 116 only exposes its side 114s.

First electrical contact 106 is formed on second line layer 116 of passive component structure layer 104.First electrical contact 106 can be used as the electrode of the external electric connection of passive component structure layer 104.

First electrical contact only covers the part of second line layer.For example, second line layer 116 has an exposing surface, for example is to expose upper surface 116a.First electrical contact 106 only covers a part of 116a1 that exposes upper surface 116a of second line layer 116, and another part 116a2 that exposes upper surface 116a is not covered by first electrical contact 106.

Semiconductor structure can more comprise a circulus, and it defines Cutting Road, can avoid in the cutting technique, and the electric resistance structure of passive component structure layer, capacitance structure and induction structure are cut.For example, please refer to Fig. 3, it illustrates the cutaway view according to the semiconductor structure of yet another embodiment of the invention.Semiconductor structure 400 more comprises circulus 428, and first 102a of its contiguous insulated substrate 102 forms, and second dielectric layer 112 coats circulus 428.Circulus 428 is around electric resistance structure R, capacitance structure C and the induction structure L of passive component structure layer 104, and can not be electrically connected at any circuit unit.Again for example, please refer to Fig. 4, it illustrates the cutaway view according to the semiconductor structure of other embodiment of the present invention.The circulus 528 of semiconductor structure 500 comprises circulus 428 and organic polymer material 530, and first 102a of its contiguous insulated substrate 102 forms, and is positioned at outside second dielectric layer 112.Again for example, in the semiconductor structure 500 of an enforcement aspect, also can omit circulus 428.Perhaps, in the semiconductor structure 500 of another enforcement aspect, also can omit organic polymer material 530.

In addition,

circulus

428 and 528 material can be selected from the group that metal, organic polymer material (organicpolymer) and combination thereof are constituted.Wherein, metal for example is the single or multiple lift structure of electro-coppering, nickel, palladium or sputtering aluminum etc., and organic polymer material for example is polyimides (PI) or benzocyclobutene (BCB) or other organic polymer material.For example, the circulus 428 of Fig. 3 can be a metal.Again for example, the combination of circulus 528 circuluses 428 (can be metal) of Fig. 4 and organic polymer material 530.

In another embodiment, first electrical contact can cover whole second line layer, for example, please refer to Fig. 5, and it illustrates the cutaway view according to the semiconductor structure of another embodiment of the present invention.Semiconductor structure 200 comprises insulated substrate 102, passive component structure layer 204, first electrical contact 206 and first dielectric layer 208.The passive component structure layer 204 and first dielectric layer 208 hold this and repeat no more similar in appearance to the above-mentioned passive component structure layer 104 and first dielectric layer 108.First electrical contact 206 of semiconductor structure 200 covers the whole upper surface 216a that exposes of second line layer 216 fully.Wherein, the material of first electrical contact 206 is same as first electrical contact 106, holds this and repeats no more.In the semiconductor structure 200 of present embodiment, the part of first dielectric layer, 208 compactings, first electrical contact 206, this feature similarity first dielectric layer 108 in semiconductor structure 100 is suppressed feature on first electrical contact 106 with first electrical contact 106, holds this and repeats no more.

In addition, in the enforcement aspect, semiconductor structure 200 more comprises

circulus

428 or 528.

Above-mentioned semiconductor structure 100,200,400 and 500 one-sided structures with electrical contact, in the semiconductor structure of right another embodiment, many sides of semiconductor structure can have electrical contact respectively.For example, please refer to Fig. 6 A and 6B, Fig. 6 A illustrates the cutaway view according to the semiconductor structure of further embodiment of this invention, and Fig. 6 B illustrates the enlarged diagram of local 6B ' among Fig. 6 A.Semiconductor structure 300 comprises insulated substrate 302, passive component structure layer 304, first electrical contact 306, first dielectric layer 308, second electrical contact 318 and first Seed Layer 320.

The structure of first dielectric layer 308, first electrical contact 306 and passive component structure layer 304 and material are held this and are repeated no more respectively similar in appearance to said first dielectric layer 208, first electrical contact 206 and passive component structure layer 204.

First electrical contact 306 and second electrical contact 318 are respectively the electrical contact of relative two sides of semiconductor structure.Insulated substrate 302 has relative first 302a and second 302b.Passive component structure layer 304 is formed on first 302a, and first electrical contact 306 is formed on the passive component structure layer 304 electrically to be contacted with passive component structure layer 304, becomes the electrical contact of a side of semiconductor structure 300.Insulated substrate 302 has at least one first perforation 302c, and second electrical contact 318 is formed at the first perforation 302c and electrically is contacted with passive component structure layer 304, becomes the electrical contact of a relative side of semiconductor structure 300.

At least a portion of second electrical contact is formed in first perforation of insulated substrate, to be electrically connected at the passive component structure layer.For example, a part of 318a of second electrical contact 318 is positioned at the first perforation 302c, second 302b that another part 318b of second electrical contact 318 can be close to insulated substrate 302 forms, for example be to be formed on first Seed Layer 320 of contiguous second 302b, make another part 318b of second electrical contact 318 protrude in second 302b, to contact with the electrical electrical component in outside.

Shown in Fig. 6 B, insulated substrate 302 has more the first perforation madial wall 302d of the corresponding first perforation 302c.First Seed Layer 320 is formed between the first perforation madial wall 302d and second electrical contact 318 of insulated substrate 302.First line layer covers at least a portion of first Seed Layer, and for example, first Seed Layer 320 is covered by second electrical contact 318 fully and only exposes the side 320s of first Seed Layer 320.

In addition, in the enforcement aspect, semiconductor structure 300 more comprises

circulus

428 or 528.

Below explanation is according to the manufacture process of the semiconductor structure of one embodiment of the invention.Semiconductor structure 100 with Fig. 1 is the example explanation, please refer to Fig. 7 A to 7G, and it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 1.

At first, provide insulated substrate 102 shown in Fig. 7 A.

Then, form passive component structure layer 104 on first 102a of insulated substrate 102.In this step, there is several different methods to form passive component structure layer 104, below enumerates wherein a kind of explanation.

At first, shown in Fig. 7 A, form first line layer 110 on first 102a of insulated substrate 102.Wherein, first line layer 110 has at least one electricity group structure R and at least one capacitance structure C.

Form in the step of first line layer 110, any that can use several materials formation method forms an electric conducting material, for example is that the mode with chemical vapour deposition (CVD), electroless plating method (electroless plating), metallide (electrolyticplating), printing, spin coating, spraying, sputter (sputtering) or vacuum deposition method (vacuum deposition) forms electric conducting material; Then, form first line layer 110 in the application patterning techniques.Patterning techniques for example is lithography process (photolithography), chemical etching (chemical etching), laser drill (laserdrilling) or machine drilling (mechanical drilling).

The first line layer sandwich construction is to constitute passive component structure.For example, first line layer 110 comprises the first conductive layer 110a, the second conductive layer 110b, capacitance dielectric layer 110c and the 3rd conductive layer 110d, the first conductive layer 110a is formed on first 102a of insulated substrate 102, and the second conductive layer 110b is formed on the first conductive layer 110a, and capacitance dielectric layer 110c is between the second conductive layer 110b and the 3rd conductive layer 110d.

The first conductive layer 110a can be used as electric resistance structure.The material high resistance material of the first conductive layer 110a for example is tantalum nitride (TaN), PbTiO ₃, ruthenic oxide (RuO ₂), nickel phosphide (NiP), chromaking nickel (NiCr) and NCAlSi.

The second conductive layer 110b and the 3rd conductive layer 110d can be by the good materials of conductivity, for example be aluminium (Al) and copper (Cu) at least one form.

Then, shown in Fig. 7 B, form second dielectric layer 112 and cover first line layer 110.Wherein, second dielectric layer 112 has at least one second perforation 112a, first 112b and the second perforation madial wall 112c, and the second perforation 112a extends to first line layer, 110, the second perforation madial wall 112c corresponding to the second perforation 112a from first 112b.The part of first line layer 110 is exposed from the second perforation 112a, and wherein, this part that first line layer 110 exposes for example is at least one electrical contact, a plus or minus electrode among electricity group structure R and the capacitance structure C.

The material of second dielectric layer 112 is made up of polyimides (PI) or benzocyclobutene (BCB).The mode that forms second dielectric layer 112 comprises coating technique, for example is printing (printing), spin coating (spinning) or spraying (spraying).In addition, the generation type of second dielectric layer 112 also can comprise above-mentioned patterning techniques.

Then, form second Seed Layer in the second perforation madial wall and second dielectric layer.For example, shown in Fig. 7 C,, form whole first 112b that second Seed Layer 114 covers the whole second perforation madial wall 112c and second dielectric layer 112 with electroless plating method or sputtering method.

Then, shown in Fig. 7 D, electrically connect, form second line layer 116 on second Seed Layer 114 via the electrode (not illustrating) of second Seed Layer 114 with electroplating device.Second line layer 116 has induction structure L.So far, form passive component structure layer 104.Wherein, the material of second line layer 116 can be a metal, for example is that copper is formed.

Before forming second line layer 116, can form a patterning photoresist layer 122 on second Seed Layer 114.Wherein, patterning photoresist layer 122 for example is the eurymeric photoresistance, the formation district 122a (being the vacancy section of the patterning photoresist layer 122 of Fig. 7 D) of patterning photoresist layer 122 definition second line layer 116.Afterwards, use electro-plating method again and form second line layer 116 in forming district 122a.Above-mentioned exposing in upper surface 116a second line layer 116 from forming the surface that district 122a exposes.

The method that forms patterning photoresist layer 122 has several.For example, form a photoresist (not illustrating) with above-mentioned material formation method or coating process earlier, and then with above-mentioned patterning method, this photoresist of patterning is to form patterning photoresist layer 122.

After second line layer 116 forms,, remove patterning photoresist layer 122 for example to be to peel off (strip) or etching (etching) technology.

Then, shown in Fig. 7 E, form at least one first electrical contact 106 on passive component structure layer 104.Wherein, the formation of first electrical contact 106 for example to be electroplating technology, forms first electrical contact 106 via second Seed Layer 114 on second line layer 116.Say further, electrically connect with electroplating device via formed second Seed Layer 114 of preceding step, and form first electrical contact 106 shown in Fig. 7 E, so can shorten the process time, reduce cost and enhance productivity.

Before forming first electrical contact 106,, form a patterning photoresist layer 124 on second Seed Layer 114 with formation method similar in appearance to patterning photoresist layer 122.Wherein, patterning photoresist layer 124 for example is the eurymeric photoresistance, the formation district of patterning photoresist layer 124 definition first electrical contact 106.Afterwards, for example being that electroplating technology forms at least one first electrical contact 106 in this formation district.

After first electrical contact 106 forms,, remove patterning photoresist layer 124 for example to be to peel off or etching technique.

In the present embodiment, first electrical contact 106 is formed on the part of second line layer 116, for example is the part of exposing upper surface 116a of second line layer 116.

Then, shown in Fig. 7 F,, remove the part of second Seed Layer 114, keep another part 114a of second Seed Layer 114 for example to be etching technique.Wherein, the part that this part that is removed in second Seed Layer 114 is not covered by second line layer 116, and the part that another part 114a of second Seed Layer 114 is covered by second line layer 116.

After removing the step of this part of second Seed Layer 114, but application examples plasma process and acid cleaning process in this way remove or clean the residual patterning photoresist layer 124 and second Seed Layer 114.

Then, form a part of 106a of first dielectric layer, 108 coverings, first electrical contact 106 shown in Fig. 7 G.Wherein, first dielectric layer 108 has the first perforate 108a, and another part 106b of first electrical contact 106 exposes from the first perforate 108a.

The mode that forms first dielectric layer 108 is held this and is repeated no more similar in appearance to the mode that forms second dielectric layer 112.

Afterwards, shown in Fig. 7 G, but application examples cutter or laser cutting technique in this way cut first dielectric layer 108, second dielectric layer 112 and insulated substrate 102 at least, to form at least just like semiconductor structure shown in Figure 1 100.

The manufacture process of the semiconductor structure 400 of following key diagram 3.Please refer to Fig. 8, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.Form circulus 428, wherein circulus 428 is around the passive component (electric resistance structure R, capacitance structure C and induction structure L (induction structure L is illustrated in Fig. 7 F)) of passive component structure layer 104.Circulus 428 can form in same technology in the lump with first line layer 110, for example, and the part of circulus 428 first conductive layer 110a.So, circulus 428 also can form respectively with first line layer 110.Second dielectric layer 112 of follow-up formation can coat whole circulus 428, as shown in Figure 3.

The manufacture process of the semiconductor structure 500 of following key diagram 4.Please refer to Fig. 9, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 4.After second dielectric layer 112 forms, form circulus 528.The organic polymer material 530 of circulus 528 can form in same technology in the lump with second dielectric layer 112; Perhaps, the organic polymer material 530 and second dielectric layer 112 form respectively.Please refer to Figure 10 (illustrating a plurality of cellular zone RP), it illustrates the top view of the circulus of Fig. 9.Circulus 528 defines at least one Cutting Road P, therefore in cutting step, can avoid cutting to the passive component structure layer 104 that is positioned at cellular zone RP, for example is electric resistance structure R, capacitance structure C and induction structure L (not being illustrated in Figure 10).

The manufacture process of the semiconductor structure 200 of following key diagram 3.In the manufacture method of semiconductor structure 200, form step before first electrical contact 206, hold this and repeat no more, below begin explanation from the step that forms first electrical contact 206 haply similar in appearance to the manufacture method of semiconductor structure 100.

Please refer to Figure 11, it illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 3.Form first electrical contact 206 on passive component structure layer 204.For example, the whole of second line layer 216 of first electrical contact, 206 covering passive component structure layers 204 exposes on the upper surface 216a.Say further, in the step that forms first electrical contact 206, use to form the employed patterning photoresist layer 122 of second line layer 116 (as Fig. 7 D), therefore make first electrical contact 206 cover the whole upper surface 216a that exposes.In the case, the step that forms second line layer is used with light shield (being the patterning photoresist layer 124 that can omit Fig. 7 E in the manufacture process of semiconductor structure 200) with the step that forms first electrical contact, can save the technology cost, reduces the process time and improve process efficiency.

Forming after first electrical contact 206, can for example be to peel off or etching technique, removes the patterning photoresist layer 122 of Figure 11.

Below with the manufacture process of the semiconductor structure 300 of Figure 12 A to 12D key diagram 6A.Figure 12 A to 12D illustrates the manufacturing schematic diagram of the semiconductor structure of Fig. 6 A.In the manufacture method of semiconductor structure 300, form step before first dielectric layer, hold this and repeat no more, below after the step that forms first dielectric layer 308, begin explanation haply similar in appearance to the step of making semiconductor structure 100 or 200.

After the step that forms first dielectric layer 308, the passive component structure layer is set on support plate.For example, shown in Figure 12 A, passive component structure layer 304 is set on support plate 326, wherein, support plate 326 has adhesive layer (not illustrating), passive component structure layer 304 sticks on this adhesive layer, and second 302b that makes insulated substrate 302 for example is down toward the outer side, so this is non-in order to restriction the present invention, in other enforcement aspect, second 302b of insulated substrate 302 can for example be up towards the direction of convenient working.

Then, form at least one first perforation and run through insulated substrate.For example, shown in Figure 12 B,, form at least one first perforation 302c and run through insulated substrate 302 for example to be laser processing technology, Machining Technology or chemical etch technique.Wherein, the first perforation 302c extends to second 302b from first 302a of insulated substrate 302.After the first perforation 302c formed, insulated substrate 302 formed the first perforation madial wall 302d of the corresponding first perforation 302c.

In other enforcement aspect, form before the first perforation 302c, can be from second 302b grinding insulated substrate 302 of insulated substrate 302, to reduce the thickness of insulated substrate 302.

Then, form first Seed Layer second in the first perforation madial wall and insulated substrate.For example, shown in Figure 12 C,, form whole second 302b that first Seed Layer 320 covers whole first perforation madial wall 302d and insulated substrate 302 for example to be electroless plating (Electro-less) method or sputtering method.

Then, form second electrical contact in first perforation.For example, shown in Figure 12 D, form second electrical contact 318 on first Seed Layer 320, a part of 318a of second electrical contact 318 is positioned at the first perforation 302c, and second 302b of the contiguous insulated substrate 302 of another part 318b of second electrical contact 318 forms, and for example is to be formed on first Seed Layer 320 of contiguous second 302b.

Then, for example to be cutter or laser cutting technique, first dielectric layer 308, second dielectric layer 312 and the insulated substrate 302 of cutting drawing 12D at least are to form at least just like the semiconductor structure 300 shown in Fig. 6 A.

Semiconductor structure of the above embodiment of the present invention and manufacture method thereof have multinomial feature, and it is as follows to enumerate the part feature description:

(1). semiconductor structure adopts the substrate of tool insulating properties, can reduce the formation of insulating barrier, to reduce manufacturing cost, to save the process time.

(2). first dielectric layer is suppressed first electrical contact, and first electrical contact firmly is formed on the passive component structure layer.

(3). same patterning photoresist layer is shared in the formation of second line layer and first electrical contact, can save technology cost and time.

In sum, though the present invention discloses as above with several embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims

1. A semiconductor structure having a passive component structure, comprising:

an insulating substrate;

a passive component structure layer formed on the insulating substrate;

a first electrical contact formed on the passive device structural layer; and

A first dielectric layer covers a part of the first electrical contact, wherein the first dielectric layer has a first opening, and another part of the first electrical contact is exposed from the first opening.

2. The semiconductor structure according to claim 1, wherein the insulating substrate has a first through hole, and the semiconductor structure further comprises:

A second electrical contact is formed in the first through hole.

3. The semiconductor structure according to claim 2, wherein the insulating substrate has a first surface and a second surface opposite, the passive device structure layer is formed on the first surface of the insulating substrate, the second electrical A part of the contact is located in the first through hole, and another part of the second electrical contact is formed adjacent to the second surface of the insulating substrate.

4. The semiconductor structure of claim 2, further comprising:

A first seed layer is formed between the insulating substrate and the second electrical contact.

5. The semiconductor structure of claim 1, wherein the passive device structure layer comprises:

a first circuit layer formed on the insulating substrate;

A second dielectric layer covering the first wiring layer, wherein the second dielectric layer has a second through hole, a first surface and an inner sidewall of the second through hole, and the second through hole extends from the second through hole The first surface of the dielectric layer extends to the first circuit layer, the inner sidewall of the second through hole corresponds to the second through hole, and the first circuit layer is exposed from the second through hole;

a second circuit layer;

a second seed layer formed between the second wiring layer and the second dielectric layer; and

Wherein, the first electrical contact is formed on the second circuit layer of the passive component structure layer.

6. The semiconductor structure of claim 5, wherein the second circuit layer has an exposed surface, and the first electrical contact covers the entire exposed surface of the second circuit layer.

7. The semiconductor structure of claim 5, wherein the second wiring layer has an exposed surface, and the first electrical contact only covers a part of the exposed surface of the second wiring layer.

8. The semiconductor structure of claim 1, wherein the insulating substrate is a glass substrate or a ceramic substrate.

9. The semiconductor structure of claim 1, further comprising:

A ring structure surrounds the passive components of the passive component structural layer.

10. A method of manufacturing a semiconductor structure having a passive component structure, comprising:

providing an insulating substrate;

forming a passive component structure layer on the insulating substrate;

forming a first electrical contact on the passive device structure layer; and

A first dielectric layer is formed to cover a part of the first electrical contact, wherein the first dielectric layer has a first opening, and another part of the first electrical contact is exposed from the first opening.

11. The manufacturing method as claimed in claim 10, further comprising:

forming a first through hole through the insulating substrate; and

A second electrical contact is formed on the first through hole.

12. The manufacturing method according to claim 11, wherein in the step of providing the insulating substrate, the insulating substrate has a first face and a second face opposite to each other; in the step of forming the passive component structure layer , the passive component structure layer is formed on the first surface of the insulating substrate; in the step of forming the second electrical contact, a part of the second electrical contact is located in the first through hole, and the second electrical contact Another portion of the two electrical contacts is formed adjacent to the second surface of the insulating substrate.

13. The manufacturing method according to claim 11, wherein in the step of forming the first through hole, the insulating substrate has a first through hole inner wall corresponding to the first through hole, and in forming the second electrode Before the step of the sexual contact, the manufacturing method further includes:

forming a first seed layer on the inner wall of the first through hole;

In the step of forming the second electrical contact, the second electrical contact is formed on the first seed layer.

14. The manufacturing method as claimed in claim 13, further comprising:

A portion of the first seed layer is removed, wherein the portion of the first seed layer is not covered by the second electrical contact.

15. The manufacturing method according to claim 10, wherein in the step of forming the first electrical contact, the first electrical contact is composed of at least one of a nickel layer, a palladium layer, and a gold layer.

16. The manufacturing method as claimed in claim 10, wherein the step of forming the passive component structure layer comprises:

forming a first circuit layer on the insulating substrate;

A second dielectric layer is formed to cover the first wiring layer, wherein the second dielectric layer has a second through hole, a first surface and an inner sidewall of the second through hole, and the second through hole extends from the second The first surface of the dielectric layer extends to the first circuit layer, the inner sidewall of the second through hole corresponds to the second through hole, and the first circuit layer is exposed from the second through hole;

forming a second seed layer on the inner sidewall of the second through hole and the first surface of the second dielectric layer; and

forming a second circuit layer on the second seed layer; and the step of forming the first electrical contact further includes:

Through the second seed layer, the first electrical contact is formed on the second wiring layer.

17. The manufacturing method of claim 16, further comprising:

A part of the second seed layer is removed, wherein the part is not covered by the second circuit layer.

18. The manufacturing method as claimed in claim 16, wherein before the step of forming the second wiring layer, the manufacturing method further comprises:

forming a patterned photoresist layer on the second seed layer, wherein the patterned photoresist layer defines a formation area;

In the step of forming the second wiring layer, the second wiring layer is formed in the formation area of the patterned photoresist layer, and the second wiring layer has an exposed surface;

The step of forming the first electrical contact further includes:

The first electrical contact is formed in the formation area to cover the entire exposed surface of the second circuit layer.

19. The manufacturing method according to claim 16, wherein in the step of forming the second circuit layer, the second circuit layer has an exposed surface; in the step of forming the first electrical contact, further comprising :

The first electrical contact is formed to cover a part of the exposed surface of the second circuit layer.

20. The manufacturing method of claim 10, further comprising:

A ring structure is formed, wherein the ring structure surrounds the passive components of the passive component structure layer.