CN102164251B - Signal processing circuit and signal processing method for image sensor - Google Patents

Abstract

The invention relates to a signal processing circuit and a signal processing method of an image sensor. The signal processing circuit includes: at least two image capacitors configured to controllably acquire an image signal of at least one pixel; at least two reset capacitors configured to controllably acquire a reset signal of at least one pixel; a first switching unit configured causing at least one of the at least two image capacitors to be coupled to the at least one pixel to acquire an image signal in response to a control signal, and causing the at least two image capacitors to share the acquired image signal; and the second A switching unit configured to make at least one of the at least two reset capacitors coupled to the at least one pixel to obtain a reset signal in response to a control signal, and make the at least two reset capacitors share the obtained reset signal .

Description

Image sensor signal processing circuit and signal processing method

technical field

The present invention relates to the technical field of image sensors, and more specifically, the present invention relates to a signal processing circuit and a signal processing method of an image sensor.

Background technique

With the development of semiconductor technology, image sensors have been widely used in various fields requiring digital imaging, such as digital cameras, digital video cameras and other electronic products. According to different photoelectric conversion methods, image sensors can generally be divided into two categories: charge coupled device (Charge Coupled Device, CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Among them, the CMOS image sensor has the advantages of small size, low power consumption, and low production cost. Therefore, the CMOS image sensor is easy to be integrated in portable electronic devices such as mobile phones, notebook computers, and tablet computers, as a camera module that provides digital imaging functions. use.

With the advancement of the manufacturing process of the image sensor, in the prior art, the resolution of the image sensor has been greatly improved, usually reaching 5 million pixels or higher. However, for an image sensor with a higher resolution, the improvement of image resolution will inevitably lead to an increase in the amount of data to be processed, which will further increase the difficulty of subsequent image signal processing. For example, in the preview mode (Preview Mode), if the image resolution is kept unchanged, the frame rate (Frame Rate) of the image display in the preview mode will be too low, which will affect the preview effect.

In order to improve the frame rate of image display in the preview mode, an existing image signal processing method discards part of the signal in the image signal collected by the image sensor, for example, only acquires the image signals of all even-numbered lines, and omits all the image signals of odd-numbered lines. image signal. Although this image signal processing method can achieve the purpose of reducing the amount of image data processing, however, it often causes excessive loss of image information, thus significantly reducing the quality of image display.

Contents of the invention

It can be seen that it is necessary to provide an image processing circuit and an image processing method for an image sensor, which can avoid the degradation of image display quality as much as possible while reducing the amount of data processing and increasing the frame rate of image display.

In order to solve the above problem, in an embodiment according to one aspect of the present invention, a signal processing circuit of an image sensor is provided, including: at least two image capacitors configured to controllably acquire an image signal of at least one pixel; at least two a reset capacitor configured to controllably acquire a reset signal of at least one pixel; a first switch unit configured to couple at least one of the at least two image capacitors to the at least one pixel in response to a control signal acquiring an image signal, and causing the at least two image capacitors to share the acquired image signal; and a second switching unit configured to cause at least one of the at least two reset capacitors to be coupled to the at least two reset capacitors in response to a control signal At least one pixel obtains a reset signal, and the at least two reset capacitors share the obtained reset signal.

In an embodiment according to another aspect of the present invention, there is also provided a signal processing method for an image sensor, including the following steps: providing at least two image capacitors configured to controllably acquire an image signal of at least one pixel; providing at least two reset capacitors configured to controllably obtain a reset signal of at least one pixel; coupling at least one of the at least two image capacitors to the at least one pixel to obtain an image signal; connecting the at least At least one of the two reset capacitors is coupled to the at least one pixel to obtain a reset signal; the obtained image signal is shared between the at least two image capacitors; and the obtained image signal is shared between the at least two reference capacitors the reset signal.

Compared with the prior art, the signal processing circuit of the image sensor of the present invention adopts the mode of pixel merging (binning) to reduce the amount of data to be processed, because the signals from different pixels in the image sensor pixel array can be collected by different capacitors and Sharing, which avoids excessive loss of image information, thereby improving image display quality. In addition, the present invention can also be effectively compatible with the working mode of progressive readout of image signals.

The above and other characteristics of the present invention will be clearly illustrated in the Examples section hereinafter.

Description of drawings

The characteristics, objects and advantages of the present invention can be more readily understood by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein, the same or similar reference numerals represent the same or similar devices.

Fig. 1 shows a 4T pixel structure of an image sensor;

FIG. 2 shows a signal processing circuit of an image sensor according to an embodiment of the present invention;

FIG. 3 shows a signal processing circuit of an image sensor according to another embodiment of the present invention, which further shows a specific circuit structure of a first switching unit and a second switching unit;

Figure 4 shows a timing diagram for the control signals of the signal processing circuit of Figure 3;

Figure 5 shows another optional structure of the switching unit;

FIG. 6 shows a signal processing method of an image sensor according to an embodiment of the present invention.

Detailed ways

The making and using of the embodiments are discussed in detail below. It should be understood, however, that the specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

CMOS image sensors usually use a 3T or 4T pixel structure. The 3T pixel structure means that in each pixel of the CMOS image sensor pixel array, in addition to the photodiode used for light sensing, it also includes 3 transistors, namely a reset transistor, a source follower transistor and a row selection transistor. The 4T pixel structure further adds a transfer transistor on the basis of the 3T pixel structure. For the signal processing circuit and processing method of the present invention, it can not only process the signal of the 3T pixel structure image sensor, but also process the signal of the 4T pixel structure image sensor. In the following embodiments, only the 4T pixel structure This is described as an example, but it should be recognized that other types of image sensors including 3T pixel structures or other pixel structures also fall within the scope of the present invention.

FIG. 1 shows a 4T pixel structure of an image sensor, including a photodiode 101 , a transfer transistor 102 , a reset transistor 103 , a source follower transistor 104 and a row selection transistor 105 .

Wherein, the photodiode 101 is coupled between a first reference potential VSS (such as a common voltage terminal or a negative power supply terminal) and the source of the transfer transistor 102 for sensing light intensity changes to form corresponding charge signals.

The drain of the transfer transistor 102 is connected to the source of the reset transistor 103 and the gate of the source follower transistor 104. The gate of the transfer transistor 102 is used to receive the transfer control signal TX. Under the control of the transfer control signal TX, the transfer transistor 102 It is turned on or off accordingly, so that the charge signal induced by the photodiode 101 is read out to the drain of the transfer transistor 102, and the charge signal is stored by the drain.

The drain of the reset transistor 103 is connected to the second reference potential VDD (such as a positive power supply terminal), and its gate is used to receive the reset control signal RST. Under the control of the reset control signal RST, the reset transistor 103 is turned on or off accordingly. , thereby providing a reset signal to the gate of the source follower transistor 104 .

The drain of the source follower transistor 104 is connected to the second reference potential VDD, and the source thereof is connected to the drain of the row selection transistor 105 for converting the charge signal obtained by the transfer transistor 102 into a voltage signal. The source of the row selection transistor 105 is connected to the bit line BL, and its gate is used to receive the column selection signal RS. Under the control of the row selection signal RS, the row selection transistor 105 is opened or closed accordingly, so that the source follows the transistor 104 The drain is selectively coupled to the bit line BL, so that the signal converted by the source follower transistor 104 is output from the bit line BL.

FIG. 2 shows a signal processing circuit of an image sensor according to an embodiment of the present invention. FIG. 2 also shows some pixels in the image sensor pixel array, including the first pixel 211 and the second pixel 212 . In this embodiment, the first pixel 211 and the second pixel 212 are located in the same column of the image sensor pixel array, and their output terminals are commonly coupled to the same bit line BL. The signal processing circuit includes:

The first image capacitor 201 and the second image capacitor 202 are configured to controllably acquire an image signal of at least one pixel in the pixel array, such as an image signal of the first pixel 211 and/or the second pixel 212;

The first reset capacitor 203 and the second reset capacitor 204 are configured to controllably acquire a reset signal of at least one pixel in the pixel array, such as a reset signal of the first pixel 211 and/or the second pixel 212;

The first switching unit 205 is configured to couple at least one of the first image capacitor 201 and the second image capacitor 202 to at least one pixel in the pixel array in response to a control signal to obtain an image signal, and make the first The image capacitor 201 shares the acquired image signal with the second image capacitor 202; and

The second switching unit 206 is configured to couple at least one of the first reset capacitor 203 and the second reset capacitor 204 to at least one pixel in the pixel array in response to a control signal to obtain a reset signal, and make the first The reset capacitor 203 and the second reset capacitor 204 share the obtained reset signal.

It should be noted that in practical applications, the signal processing circuit may also include more than three image capacitors according to different specific needs, and these image capacitors can respectively acquire image signals of different pixels in the pixel array, and share the acquired similarly, the signal processing circuit may further include more than three reset capacitors, and these reset capacitors can respectively acquire reset signals of different pixels in the pixel array, and share the acquired reset signals. In this way, the signal processing circuit can combine the signals collected by more than three pixels, and reduce the image resolution to reduce the amount of data processing. It can be understood that, for more than 3 pixels, the signal combination method is similar to the signal combination of 2 pixels. Therefore, in the following embodiments, only a signal processing circuit or method for combining signals of two pixels is used for description. Correspondingly, the signal processing circuit has 2 image capacitors and 2 reset capacitors.

In addition, it should be noted that the two pixels referred to here are for one signal combining operation. In practical applications, the signal processing circuit processes each pixel in the pixel array periodically, for example, acquiring signals of each row in a row-by-row scanning manner. After the signal processing circuit completes a combination of the acquired signals, it will further amplify the signal and convert it into a digital signal of corresponding size through an analog-to-digital conversion circuit (A/D Converter); after that, the signal processing circuit will obtain another Signals of 2 pixels (for example, 2 pixels adjacent to the aforementioned 2 pixels) and combined the acquired signals.

In this context, the term "harvesting" refers to applying a potential difference between the two plates of a capacitor to charge the capacitor such that an amount of charge corresponding to said potential difference is stored in the capacitor.

In one embodiment, the signal processing circuit further includes an amplifying unit 207, configured to amplify the voltage difference between the shared image signal and the reset signal. Therefore, the first switching unit 205 is further configured to couple at least one of the first image capacitor 201 and the second image capacitor 202 to the amplifying unit 207 in response to the control signal to provide a shared image signal. Correspondingly, the second switching unit 206 is further configured to couple at least one of the first reset capacitor 203 and the second reset capacitor 204 to the amplifying unit 207 in response to a control signal to provide a shared reset signal.

Specifically, the first switching unit 205 and the second switching unit 206 may respectively include more than one switch, wherein each switch has a control terminal for receiving a control signal. Based on the received control signal, each switch is opened or closed respectively, so that each image capacitor or reset capacitor is coupled to the pixel array, and the corresponding image signal or reset signal is obtained through the bit line BL, or each The image capacitor or reset capacitor is coupled to the input terminal of the amplifying unit 207 to provide the amplifying unit 207 with a shared image signal and a reset signal. Wherein, the bit line BL is usually coupled to a column of pixels in the pixel array, and the signals provided by different rows of pixels in the column of pixels can be obtained according to the difference of the row selection signal RS.

Next, the working mode of the signal processing circuit will be described in detail.

First, the signal processing circuit collects the reset signal of the first pixel 211 . Specifically, based on the control of the row selection signal RS, the first pixel 211 is selected, and the row selection transistor 221 therein is turned on. Next, the reset control signal RST controls the reset transistor 222 to be turned on, and the first pixel 211 provides the first reset signal to the bit line BL. At the same time, the second switching unit 206 makes the first reset capacitor 203 and/or the second reset capacitor 204 coupled to the bit line BL in response to the control signal, so as to obtain the first reset signal, that is, the first reset capacitor 203 and/or Or the first reset charge Qref1 corresponding to the first reset signal is stored in the second reset capacitor 204 . It can be understood that, during the period of collecting the first reset signal, the second switching unit 206 should disconnect the connection between the first reset capacitor 203 and the second reset capacitor 204 and the amplifying unit 207 .

Next, the signal processing circuit collects the image signal of the first pixel 211 . Specifically, based on the control of the row selection signal RS, the first pixel 211 is still selected, and the row selection transistor 221 therein is still in an on state. The transfer control signal TX controls the transfer transistor 223 to be turned on, and the first pixel 211 provides the first image signal to the bit line BL. At the same time, the first switching unit 205 makes the first image capacitor 201 and/or the second image capacitor 202 coupled to the bit line BL in response to the control signal, so as to obtain the first image signal, that is, the first image capacitor 201 and/or Or the first image charge Q _sig1 corresponding to the first image signal is stored in the second image capacitor 202 . It can be understood that, during the acquisition of the first image signal, the first switching unit 205 should disconnect the connection between the first image capacitor 201 and the second image capacitor 202 and the amplification unit 207; and the first reset capacitor 203 and the second reset capacitor The capacitor 204 is disconnected from the bit line BL and the amplifying unit 207 .

Next, the signal processing circuit collects the reset signal of the second pixel 212 . Specifically, based on the control of the row selection signal RS, the second pixel 212 is selected, and the row selection transistor 226 therein is turned on. Next, the reset control signal RST controls the reset transistor 227 to be turned on, and the second pixel 212 provides the second reset signal to the bit line BL. At the same time, the first switch unit 205 couples the first reset capacitor 203 or the second reset capacitor 204 to the bit line BL in response to the control signal, so as to obtain the second reset signal. Wherein, if both the first reset capacitor 203 and the second reset capacitor 204 have obtained the first reset signal, any one of the first reset capacitor 203 or the second reset capacitor 204 can obtain the second reset signal. But if only one of the first reset capacitor 203 and the second reset capacitor 204 has obtained the first reset signal, then only the reset capacitor that has not obtained the first reset signal can obtain the second reset signal, so as to avoid the first reset signal lost. In this way, the first reset charge Q ref1 and the second reset charge Q _ref2 corresponding to the second reset signal are respectively stored in the first reset capacitor 203 and the second reset capacitor ₂₀₄ . It can be understood that during the period of collecting the second reset signal, the second switching unit 206 should disconnect the connection between the first reset capacitor 203 and the second reset capacitor 204 and the amplification unit 207, and the first image capacitor 201 and the second image The capacitor 202 is disconnected from the amplifying unit 207 and the bit line BL.

Afterwards, the signal processing circuit collects the image signal of the second pixel 212 . Specifically, based on the control of the row selection signal RS, the second pixel 212 is still selected, and the row selection transistor 226 therein is still in an on state. The transfer control signal TX controls the transfer transistor 228 to be turned on, and the second pixel 212 provides the second image signal to the bit line BL. At the same time, the second switching unit 206 makes the first image capacitor 201 and/or the second image capacitor 202 coupled to the bit line BL in response to the control signal, so as to obtain the second image signal. Wherein, if both the first image capacitor 201 and the second image capacitor 202 have obtained the first image signal, then any one of the first image capacitor 201 or the second image capacitor 202 can obtain the second image signal. But if only one of the first image capacitor 201 and the second image capacitor 202 has acquired the first image signal, then only the image capacitor that has not acquired the first image signal can acquire the second image signal, so as to avoid the first image signal lost. In this way, the first image charge Q sig1 and the second image charge Q _sig2 corresponding to the second image signal are respectively stored in the first image capacitor 201 and the second image capacitor ₂₀₂ . It can be understood that during the acquisition of the second image signal, the first switching unit 205 should disconnect the connection between the first image capacitor 201 and the second image capacitor 202 and the amplification unit 207, and the first reset capacitor 203 and the second reset capacitor The capacitor 204 is disconnected from the bit line BL and the amplifying unit 207 .

Through the above steps, the acquisition of each pixel image signal and reset signal is completed. Next, the first switch unit 205 connects the first image capacitor 201 and the second image capacitor 202 in parallel in response to the control signal, and the second switch unit 206 connects the first reset capacitor 203 to the second reset capacitor 204 in response to the control signal. connected in parallel.

In this way, the first image charge Q _sig1 and the second image charge Q _sig2 are shared between the first image capacitor 201 and the second image capacitor 202 , that is, redistributed according to the ratio of capacitance values, and form a new image signal. Take the first image capacitor 201 to obtain the second image signal and the second image capacitor 202 to obtain the first image signal as an example. After the image signal voltages are combined, the voltages of the image signals on the first image capacitor 201 and the second image capacitor 202 should be equal, specifically (C _sig1 U _sig2 +C _sig2 U _sig1 )/(C _sig1 +C _sig2 ), where C _sig1 represents the capacitance of the first image capacitor 201, C _sig2 represents the capacitance of the second image capacitor 202, U _sig1 represents the voltage of the first image signal, and U _sig2 represents the voltage of the second image signal.

In practical applications, the capacitance values of the first image capacitor 201 and the second image capacitor 202 may be different according to different application requirements, that is, the weights of the first image signal and the second image signal in signal combination are different. In an embodiment according to the present invention, the capacitance values of the first image capacitor 201 and the second image capacitor 202 may be equal, so that the voltage value of the combined image signal is (U _sig2 +U _sig1 )/2.

Similarly, the first reset charge Q _ref1 and the second reset charge Q _ref2 are shared between the first reset capacitor 203 and the second reset capacitor 204 to form a new reset signal. It can be understood that, during the charge sharing process, the first switching unit 205 and the second switching unit 206 should disconnect the connection between each capacitor, the amplification unit 207 and the pixels.

The combination of image signals corresponding to different pixels is realized through the sharing of charge signals in the capacitors. This combination of image signals not only avoids the degradation of image quality caused by traditional skipping image signals of one or more rows of pixels, such as severe jaggedness in the image, but also effectively reduces the amount of data for subsequent image signal processing. Therefore, the frame rate of image display can be improved, especially in application scenarios like a preview mode.

After the signal sharing (that is, merging) is completed, the shared image signal and reset signal can be further provided to the amplifying unit 207, specifically, the first switching unit 205 responds to the control signal to make the first image capacitor 201 and the second At least one of the image capacitors 202 is coupled to an input terminal of the amplifying unit 207 to provide a shared image signal; and the second switching unit 206 responds to the control signal to make the first reset capacitor 203 and the second reset capacitor 204 At least one of them is coupled to the other input end of the amplifying unit 208 to provide a shared image signal. Among them, compared to the readout method of coupling two image capacitors (and two reset capacitors) to the amplifying unit, the readout method of only coupling one of the image capacitors (and one reset capacitor) to the amplifying unit 207 is equivalent. This reduces the capacitance value of the input terminal of the amplifying unit 207, thereby reducing the amplification gain. In particular, in a preferred embodiment, the capacitance values of the image capacitor and the reset capacitor are equal. In this case, only one image/reset capacitor is coupled to the amplification gain of the readout method to only couple two images/ 1/2 of the amplification gain of the reset capacitance readout method. When the external light intensity is high, the reduction of amplification gain can avoid image overexposure, thereby improving image quality.

In this embodiment, the signal processing circuit is used to complete signal combination between different pixel signals, different image capacitors are configured to acquire image signals of different pixels, and different reset capacitors are configured to acquire reset signals of different pixels. However, in practical applications, the signal processing circuit can still be compatible with the working mode without signal combination, for example, in the photo shooting mode.

In addition, since the signal processing circuit has multiple controllable image/reset capacitors to acquire signals, it can read out signals in a more flexible manner.

Specifically, when signal acquisition is performed on a pixel, two image/reset capacitors can be coupled to the pixel to obtain the corresponding signal. In this case, when the signal is read out, the two image/reset capacitors can be Both reset capacitors are coupled to the amplifying unit 207, or only one image/reset capacitor is coupled to the amplifying unit 207, wherein the amplification gain of the former readout mode is twice that of the latter. On the other hand, it is also possible to couple only one image/reset capacitor to the pixel to acquire the signal. In this case, when the signal is read out, the acquired signal can be shared between the two image/reset capacitors, and the two Each image/reset capacitor is coupled to the amplifying unit 207. Since the other image/reset capacitor does not collect a signal, the voltage value of the shared signal is reduced by half, and the amplification gain is correspondingly reduced.

Generally, in an image sensor, the charge signals induced by the pixels in the pixel array are selected and acquired row by row. Therefore, for the above-mentioned first pixel and second pixel, they are located in the same row of pixels in the pixel array. Columns of two pixels. In one embodiment of the present invention, the image sensor is a black and white image sensor, and the first pixel and the second pixel are two pixels in two adjacent rows of pixels in the pixel array. In another embodiment, the image sensor is a color image sensor, such as a Bayer RGB (Bayer RGB) image sensor, then the first pixel and the second pixel are adjacent pixels belonging to the same hue in the same column of the pixel array, For example two adjacent red (R) pixels in the same column.

It should be noted that at least two pixels in the foregoing embodiments are pixels located in the same column in the pixel array, and they share the same bit line to provide signals to an amplifying unit. For the signal combination between two or more pixels located in different columns, since it uses different bit lines to provide signals to different amplifying units, and different amplifying units have different image/reset capacitors to capture and store Therefore, for pixels located in different columns, when reading signals, the corresponding bit lines can be connected to each other, so that the corresponding image/reset capacitors can be connected in parallel to share the signal, and the combination of signals can be realized.

FIG. 3 shows a signal processing circuit of an image sensor according to another embodiment of the present invention, which further shows a specific circuit structure of a first switching unit and a second switching unit. As explained before, the first switching unit and the second switching unit may include a plurality of controllable switches connected in series and/or in parallel, and the image/reset capacitors are coupled to different nodes by changing the conduction state of the switches. superior. In practical applications, the control signal received by the controllable switch can be provided by an independent control module, such as a micro control unit (MCU).

Specifically, the signal processing circuit includes a first image capacitor 301 , a second image capacitor 302 , a first reset capacitor 303 , a second reset capacitor 304 , a first switching unit 312 and a second switching unit 313 .

Wherein, the first switching unit 312 is coupled between the input end and the first output end, and includes a first switch 305, a second switch 306, and a third switch 307 connected in series; between the first switch 305 and the second switch 306 There is a first intermediate node 361, the first image capacitor 301 is coupled between the first intermediate node 361 and the first reference potential VSS; there is a second intermediate node 362 between the second switch 306 and the third switch 307, the second The two image capacitors 302 are coupled between the second intermediate node 362 and the first reference potential VSS. The first reference potential VSS is, for example, a common potential terminal or a negative power supply terminal.

The second switching unit 312 is coupled between the input end and the second output end, and includes a fourth switch 308, a fifth switch 309, and a sixth switch 310 connected in series; Three intermediate nodes 363, the first reset capacitor 303 is coupled between the third intermediate node 363 and the first reference potential VSS; there is a fourth intermediate node 364 between the fifth switch 309 and the sixth switch 310, the second reset The capacitor 304 is coupled between the fourth intermediate node 364 and the first reference potential VSS.

It can be understood that, for more than 3 image capacitors, the first switching unit 312 may connect more than 4 switches in series, and make each image capacitor be coupled between the intermediate node and the first reference potential VSS. Similarly, for more than 3 reset capacitors, the second switching unit 313 can connect more than 4 switches in series, and make each reset capacitor be coupled between the intermediate node and the first reference potential respectively.

In a specific embodiment, the first switch 305, the second switch 306, the third switch 307, the fourth switch 308, the fifth switch 309 and the sixth switch 310 can all use MOS transistor switches, such as NMOS transistor switches or PMOS transistors The gate of the MOS transistor is used as a control terminal for receiving control signals, and the source and drain of the MOS transistor are used for transmitting signals.

FIG. 4 shows a timing diagram of control signals for the signal processing circuit of FIG. 3 . Next, the operation of the image sensor and its signal processing circuit according to an embodiment of the present invention will be further described with reference to FIG. 3 and FIG. 4 .

Each control signal in FIG. 4 is respectively applied to the control terminals of the corresponding switches or transistors. Specifically, the row selection signal RS is loaded on the gate of the row selection transistor of each pixel in the pixel array; the reset signal RST is loaded on the gate of the reset transistor of each pixel; the transfer control signal TX is loaded on the transfer transistor of each pixel The first control signal SHR is loaded on the control terminal of the fourth switch 308; the second control signal SHS is loaded on the control terminal of the first switch 305; the third control signal EQ is loaded on the second switch 306 and the second switch 308 The control terminal of the fifth switch 309 ; the fourth control signal SEL is loaded on the control terminals of the third switch 307 and the sixth switch 310 .

Firstly, in the first period T1, the first reset signal V _{ref1 and the first image signal V sig1 of} the first pixel 321 are respectively obtained by the second image capacitor 302 and the second reset capacitor 304 .

Specifically, keep the third control signal EQ valid, which makes the second switch 306 and the fifth switch 309 keep on, the first image capacitor 301 and the second image capacitor 302 are connected in parallel, the first reset capacitor 303 and the second reset capacitor 303 are connected in parallel The capacitors 304 are connected in parallel; at the same time, the row selection signal RS corresponding to the first pixel 321 is kept active, which turns on the row selection transistor 345 of the first pixel 321 , thereby connecting the first pixel 321 to the bit line BL. In this case, the reset signal RST, the first control signal SHR, the transfer control signal TX and the second control signal SHS are successively set to be effective, thereby turning on the reset transistor 343, the fourth switch 308, the transfer transistor 342 and the second A switch 305 .

Under the above timing control, the turn-on of the reset transistor 343 causes the bit line BL to receive the first reset signal. Immediately afterwards, the turn-on of the fourth switch 308 and the fifth switch 309 makes the first reset capacitor 303 and the second reset capacitor 304 obtain the first reset signal V _ref1 at the same time, and the second reset capacitor 304 is stored based on the first reset signal. The first reset charge Q _ref1 generated by V _ref1 is C _ref2 V _ref1 , where C _ref2 represents the capacitance of the second reset capacitor 304 . Afterwards, the turn-on of the transfer transistor 342 makes the bit line BL receive the first image signal V _sig1 . Immediately afterwards, the conduction of the first switch 305 and the second switch 306 enables the first image capacitor 301 and the second image capacitor 302 to obtain the first image signal V _sig1 at the same time, and the second image capacitor 302 is stored based on the first image signal. The first image charge Q _sig1 generated by V _sig1 is C _sig2 V _sig1 , wherein C _sig2 represents the capacitance value of the second image capacitor 302 .

Afterwards, in the second period T2, the second reset signal V ref2 and the first image signal V _sig2 are respectively obtained by the first image capacitor ₃₀₁ and the first reset capacitor 303 .

Specifically, keep the third control signal EQ invalid, which makes the second switch 306 and the fifth switch 309 keep off, the first image capacitor 301 is disconnected from the second image capacitor 302, and the first reset capacitor 303 is connected to the second reset capacitor. The capacitor 304 is disconnected; at the same time, the row selection signal RS corresponding to the second pixel 322 is kept active, which makes the row selection transistor 350 of the second pixel 322 turn on, thereby connecting the second pixel 322 to the bit line BL. In this case, the reset signal RST, the first control signal SHR, the transfer control signal TX and the second control signal SHS are successively set to be effective, thereby turning on the reset transistor 348, the fourth switch 308, the transfer transistor 347 and the second A switch 305 .

Under the above timing control, the turn-on of the reset transistor 348 makes the bit line BL receive the second reset signal V _ref2 . Next, the fourth switch 308 is turned on so that the first reset capacitor 303 obtains the second reset signal V _ref2 , and the first reset capacitor 303 can store the second reset charge Q _ref2 generated based on the second reset signal V _ref2 , that is, C _ref1 V _ref2 , where C _ref1 represents the capacitance of the second reset capacitor 303 . Afterwards, the turn-on of the transfer transistor 347 makes the bit line BL correspondingly obtain the second image signal V _sig2 of the second pixel 322 . Next, the conduction of the first switch 305 makes the first image capacitor 301 obtain the second image signal V _sig2 , and the first image capacitor 301 can store the second image charge Q _sig2 generated based on the second image signal V _sig2 , namely C _sig1 V _sig2 , where C _sig1 represents the capacitance of the first image capacitor 301 .

It can be seen that after the first period T1 and the second period T2, the first image capacitor 301 and the second image capacitor 302 obtain the second image generated based on the second image signal V _sig2 and the first image signal V _sig1 respectively. The image charge Q _sig2 and the first image charge Q _sig1 , and the first reset capacitor 303 and the second reset capacitor 304 respectively obtain the second reset signal V _ref2 and the second reset charge Q _ref2 generated based on the first reset signal V _ref1 with the first reset charge Q _ref1 . These charges respectively reflect the magnitude of the image signal and the reset signal of the first pixel 321 and the second pixel 322 .

Next, in the third stage T3 , charge sharing is performed on the first image capacitor 301 and the second image capacitor 302 , and the first reset capacitor 303 and the second reset capacitor 304 respectively.

Specifically, only the third control signal EQ is set to be effective, which makes the first image capacitor 301 and the second image capacitor 302 connected in parallel, and the obtained first image charge Q _sig1 and second image charge Q _sig2 are redistributed therebetween , and finally make the voltage values between the two plates of the first image capacitor 301 and the second image capacitor 302 equal. Similarly, the second image capacitor 303 and the second reset capacitor 304 are also connected in parallel, and the obtained first reset charge Q _ref1 and second reset charge Q _ref2 are redistributed therebetween, and finally the first reset capacitor 303 and the second reset capacitor 303 are connected in parallel. The voltage values between the two plates of the second reset capacitor 304 are equal.

Next, in the fourth stage T4, the fourth control signal SEL is valid column by column, so that the combined image/reset signals of each column are sequentially read out. The fourth control signal SEL is set to be valid so that the corresponding third switch 307 and the sixth switch 310 are turned on, and the third control signal EQ is set to be valid to make the second switch 306 and the fifth switch be turned on, so that the first The image capacitor 301 and the second image capacitor 302 are connected to one input end of the amplifying unit 314, and the first reset capacitor 303 and the second reset capacitor 304 are connected to the other input end of the amplifying unit 314, and then the reset signal thereon is combined with The image signals are respectively supplied to the amplification unit 314 . The amplifying unit 314 further amplifies the voltage difference between the image signal and the reset signal, and provides the amplified output voltage to a subsequent signal processing circuit.

Optionally, in the fourth stage T4, the third control signal EQ can also be set to be invalid (not shown in the figure) so that the second switch 306 and the fifth switch 309 are disconnected, so that the second image capacitor 302 and the The second reset capacitor 304 is respectively connected to two input terminals of the amplifying unit 314 and provides the obtained reset signal and image signal.

As mentioned above, if signals of pixels in different columns need to be combined, the fourth control signal corresponding to the column to be combined can be made valid at the same time during readout. In this way, the image/reset capacitors corresponding to each column are connected in parallel to the input end of the amplifying unit, so as to realize the combination of signals.

It should be understood that the structure of the first switching unit and the second switching unit in the present invention is only an example, and any other switching circuit structures that enable each capacitor to be connected to different pixels of the pixel array and obtain an image/reset signal belong to the present invention scope. FIG. 5 shows another optional structure of the switching unit, and the two capacitors connected to it are respectively controlled by a corresponding switch. The working mode of the signal processing circuit of the switch unit adopting this structure is basically the same as that of the foregoing embodiments, and will not be repeated here.

Referring to FIG. 6, a signal processing method of an image sensor according to an embodiment of the present invention is shown, including the following steps:

Executing step S602, providing at least two image capacitors configured to controllably acquire an image signal of at least one pixel;

Execute step S604, providing at least two reset capacitors configured to controllably acquire a reset signal of at least one pixel;

Execute step S606, coupling at least one of the at least two image capacitors to the at least one pixel to obtain an image signal;

Execute step S608, coupling at least one of the at least two reset capacitors to the at least one pixel to obtain a reset signal;

Executing step S610, sharing the acquired image signal between the at least two image capacitors; and

Step S612 is executed to share the obtained reset signal between the at least two reference capacitors.

In one embodiment of the present invention, after steps S610 and S610, it further includes: coupling at least one of the two image capacitors to the amplifying unit to provide a shared image signal; and resetting the two At least one of the capacitors is coupled to the amplifying unit to provide a shared reset signal.

In one embodiment of the present invention, the step S606 further includes: coupling the at least two image capacitors to different pixels to obtain corresponding image signals; correspondingly, the step S608 further includes: connecting the At least two image capacitors are coupled to different pixels to obtain corresponding image signals.

In one embodiment of the present invention, the pixels are located in the same column of the pixel array of the image sensor.

In one embodiment of the present invention, the pixels are pixels of the same hue in the pixel array of the image sensor.

In one embodiment of the present invention, the step of obtaining the reset signal is performed before the step of obtaining the image signal.

In an embodiment of the present invention, the capacitance values of the at least two image capacitors are equal.

In an embodiment of the present invention, the reset capacitor and the image capacitor have the same capacitance.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the invention is not limited to the foregoing embodiments.

Other changes to the disclosed embodiments can be understood and effected by those of ordinary skill in the art by studying the specification, disclosure, drawings and appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. In the actual application of the invention, one component may perform the functions of multiple technical features cited in the claims. Any reference signs in the claims should not be construed as limiting the scope.

Claims (16)

1. a signal processing circuit for imageing sensor, comprising:

At least two image electric capacity, are configured to controllably obtain respectively the picture signal of at least two different pixels;

At least two reset capacitance, are configured to controllably obtain respectively the reset signal of at least two different pixels;

The first switch unit, described in being configured to make in response to control signal at least two image electric capacity be couple to described at least two different pixels to obtain corresponding picture signal, and the picture signal at least two image electric capacity is redistributed according to the capacitance ratio of described at least two image electric capacity described in making, to form new picture signal; And

The second switch unit, described in being configured to make in response to control signal at least two reset capacitance be couple to described at least two different pixels to obtain corresponding reset signal, and the reset signal at least two reset capacitance is redistributed according to the capacitance ratio of described at least two reset capacitance described in making, to form new reset signal;

Wherein, described at least two different pixels are positioned at the same row of image sensor pixel array.

2. signal processing circuit according to claim 1, is characterized in that, also comprises amplifying unit, for amplifying the voltage difference of described new picture signal and described new reset signal.

3. signal processing circuit according to claim 2, it is characterized in that, at least one described in described the first switch unit is also configured to make in response to control signal at least two image electric capacity is couple to described amplifying unit so that described new picture signal to be provided.

4. signal processing circuit according to claim 2, it is characterized in that, at least one described in described the second switch unit is also configured to make in response to control signal at least two reset capacitance is couple to described amplifying unit so that described new reset signal to be provided.

5. signal processing circuit according to claim 1, it is characterized in that, described the first switch unit comprises at least three switches that are connected in series that are coupled between input node and the first output node, the wherein said switch being connected in series has at least two intermediate nodes that are positioned at switch room, and each in described at least two image electric capacity is respectively coupled between described intermediate node and reference potential.

6. signal processing circuit according to claim 1, it is characterized in that, described the second switch unit comprises at least three switches that are connected in series that are coupled between input node and the second output node, the wherein said switch being connected in series has at least two intermediate nodes that are positioned at switch room, and each in described at least two reset capacitance is respectively coupled between described intermediate node and reference potential.

7. signal processing circuit according to claim 1, is characterized in that, described at least two different pixels are pixels of same tone in image sensor pixel array.

8. signal processing circuit according to claim 1, is characterized in that, the capacitance of described at least two image electric capacity equates.

9. signal processing circuit according to claim 8, is characterized in that, described reset capacitance equates with the capacitance of described image electric capacity.

10. an imageing sensor, comprises pel array, and according to the signal processing circuit described in any one in claim 1 to 9.

The signal processing method of 11. 1 kinds of imageing sensors, comprises the steps:

At least two image electric capacity are provided, and it is configured to controllably obtain respectively the picture signal of at least two different pixels;

At least two reset capacitance are provided, and it is configured to controllably obtain respectively the reset signal of at least two different pixels;

Described in described at least two image electric capacity are coupled to, at least two different pixels are to obtain corresponding picture signal;

Described in described at least two reset capacitance are coupled to, at least two different pixels are to obtain corresponding reset signal;

According to the capacitance ratio of described at least two image electric capacity, the picture signal in described at least two image electric capacity is redistributed, to form new picture signal; And

According to the capacitance ratio of described at least two reset capacitance, the reset signal in described at least two reset capacitance is redistributed, to form new reset signal;

Wherein, described at least two different pixels are positioned at the same row of image sensor pixel array.

12. signal processing methods according to claim 11, is characterized in that, after forming the step of described new picture signal and described new reset signal, also comprise:

At least one in described two image electric capacity is couple to amplifying unit so that described new picture signal to be provided; And

At least one in described two reset capacitance is couple to amplifying unit so that described new reset signal to be provided.

13. signal processing methods according to claim 11, is characterized in that, described at least two different pixels are pixels of same tone in image sensor pixel array.

14. signal processing methods according to claim 11, is characterized in that, the step of obtaining described reset signal is to carry out before obtaining the step of described picture signal.

15. signal processing methods according to claim 11, is characterized in that, the capacitance of described at least two image electric capacity equates.

16. signal processing methods according to claim 15, is characterized in that, described reset capacitance equates with the capacitance of described image electric capacity.

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