CN102164232B - Data communication method between two cameras and realization method thereof - Google Patents

Abstract

The invention provides a method for data communication between two cameras, comprising: setting one of the cameras as the master chip, setting the other camera as the slave chip; setting the working status of the master chip and the slave chip so that the master chip works In the state of blanking, the slave chip works in the row valid state, and when the master chip works in the row valid state, the slave chip works in the row blanking state; the slave chip outputs image data in the row valid state, and the master chip Receive the digital signal from the chip in the hidden state. At the same time, a set of dual-camera device for realizing the data communication method between the dual-cameras is proposed. The present invention utilizes the time-division multiplexing processing unit and interface of dual cameras to realize cooperative work, saves the external communication interface and processing unit of the slave chip, reduces the required pins, makes the chip area smaller, and reduces the cost of dual cameras. The implementation cost of the solution is reduced, and the installation space of the dual cameras is reduced at the same time.

Description

A method of data communication between two cameras and its realization device

technical field

The invention relates to the field of image processing, in particular to a data communication method between dual cameras and a dual camera device for realizing the method.

Background technique

As an image acquisition tool, a camera is currently widely used in digital products such as mobile phones, PDAs, and tablet computers. In order to improve the user experience of the device and enhance individual functions, more and more digital products adopt a dual-camera image acquisition solution, which is placed in different parts of the device (generally divided into front camera and rear camera) to achieve multi-angle image acquisition. In the existing dual-camera solutions, the dual-cameras usually communicate with the main chip of the system (usually the baseband chip): for example, the most commonly used cameras communicate with the upper-level system in the form of a DVP (Digital Video Port) interface. For communication, this mode generally requires each camera to have its own image processing part and data output pins connected to the upper system. This dual-camera connection mode requires a relatively high space for equipment placement, and at the same time, the cost of a solution in which both cameras have an image processing device is relatively high.

The Chinese patent application with the publication number CN101877760A proposes a dual-camera structure based on the same DVP data bus. Specifically, it relates to a connection scheme for dual-cameras in a mobile phone based on the same DVP data bus. Using this scheme, it is possible to On the advanced data processing chip (DSP) platform, it realizes the control and support of the main and secondary dual cameras, and can complete the configuration, use, switching, body sleep and other functions of the dual cameras. However, this solution uses an external single data processing chip to coordinate the work between the main and secondary cameras. It only improves the way the camera communicates with the upper system, and does not improve the camera itself. Each camera still needs to be equipped with its own Functional unit, dual camera installation space and cost control are limited.

Contents of the invention

The problem solved by the present invention is to solve the problem that in the existing dual camera solution, the chip area of the main camera is limited, and there is no place to place enough data input/output pins, so that the implementation cost of the dual camera is relatively high.

In order to solve the above problems, the present invention proposes a method for data communication between dual cameras, including:

Provide a dual-camera device, set one of the cameras as the master chip, and set the other camera as the slave chip;

Set the working state of the master chip and the slave chip so that when the master chip works in the line blanking state, the slave chip works in the line valid state, and when the master chip works in the line valid state, the slave chip works in the line blanking state;

Make the slave chip output image data in the line active state, and the master chip receive the digital signal from the slave chip in the line blank state.

At the same time, a set of dual-camera device for realizing the data communication method between the dual-cameras is proposed, including a master chip and a slave chip, wherein:

The slave chip includes:

a photosensitive unit for acquiring an image signal;

The readout unit is used to read the image signal in the photosensitive unit;

a digitizing unit, for converting the analog image signal into a digital signal;

and an output unit, including an output interface, for outputting digital signals;

The main chip includes:

a photosensitive unit for acquiring an image signal;

The readout unit is used to read the image signal of the photosensitive unit;

a digitizing unit, for converting the analog image signal into a digital signal;

a processing unit, configured to process the digital signal to form image data;

The input and output unit includes a data interface, which is used to output image data to the upper system; and in the master-slave mode, receives the digital signal from the slave chip during the line blanking time of the master chip.

Preferably, when the master chip works in the row blanking state, the slave chip works in the row active state, and when the master chip works in the row valid state, the slave chip works in the row blanking state.

Preferably, when the slave chip is working, the data pins connected to the master chip on the slave chip are in an output state during the blanking time of the master chip, and the data pins connected to the slave chip on the master chip are in an input state. It is used for the master chip to receive the digital signal from the slave chip; during the effective transmission time of the master chip, the data pin connected to the master chip on the slave chip is in a high-impedance state, and the data pin connected to the slave chip on the master chip is in a high-impedance state. The pin is in the output state, and the image data is output to the upper system through the data pin of the main chip.

Compared with the prior art, the present invention has the following advantages: the present invention utilizes the dual-camera time-division multiplexing processing unit and interface to realize cooperative work, saves the image processing unit of the slave chip, and reduces the pins required for the communication of the master chip , so that the area of the master/slave chip can be made smaller, which reduces the implementation cost of the dual-camera solution and reduces the installation space of the dual-camera.

Description of drawings

FIG. 1 is a schematic diagram of the basic components of a camera in the prior art of the present invention.

FIG. 2 is a schematic diagram of the basic structure of the dual-camera device of the present invention.

Fig. 3 is a working state diagram of the communication method between the dual cameras of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the existing dual-camera image processing device, please refer to FIG. 1 , the internal structure of each camera is basically the same, including: a photosensitive unit 101 for acquiring image signals; a readout unit 102 for reading the image of the photosensitive unit Signal; digitization unit 103, used to convert analog signal into digital signal; processing unit 104, used to process digital signal, complete functions such as noise removal, interpolation, edge enhancement, grayscale correction, color correction and other image processing ; The input and output unit 105 includes a data interface for outputting image signals to the upper system.

The inventor found through research that when the camera device is in the working state, the data output interface is not in the data output state for a part of the time. Using this part of the time, the image signal transmitted by other camera devices can be received for processing. This part of the time can be defined as Free time for camera work. Specifically, during the scanning process in which the camera device converts optical signals into electrical signals, the scanning always starts from the upper left corner of the image and moves forward horizontally, while the scanning point also moves downward at a slower rate. When the scanning point reaches the right edge of the image, the scanning point quickly returns to the left, and restarts to scan the second line below the starting point of the first line. The scanning time of each line is called the line effective (horizontal effective) time. The time consumed by the return process between the line and the line is called the line blanking (horizontal blanking) time. During this period of line blanking, the camera device stops outputting data, and the data interface of its input and output unit is in an idle state. Therefore, it is a kind of idle time for camera work.

As mentioned above, when the camera device works in the line blanking state, the data interface of the input and output unit can be used to receive data, process external data at the same time, and output the processed image signal during the line effective time. Based on this principle, the image processing device of one camera in the dual-camera device can be omitted, and the data processing unit of the other camera and the communication interface with the upper system can be used for data processing, thereby reducing the implementation cost of the dual-camera solution in the prior art , while reducing the installation space of the dual cameras, while ensuring the quality of signal processing. To achieve this goal, the inventor proposes a method for data communication between dual cameras, including:

Provide a dual-camera device, set one of the cameras as the master chip, and set the other camera as the slave chip;

Set the working state of the master chip and the slave chip so that when the master chip works in the line blanking state, the slave chip works in the line valid state, and when the master chip works in the line valid state, the slave chip works in the line blanking state;

Make the slave chip output the image signal in the line active state, and the master chip receive the digital signal from the slave chip in the line blank state.

At the same time, a set of dual-camera device for implementing this method is proposed, please refer to Figure 2, including:

Including master chip 100 and slave chip 200, wherein,

The slave chip 200 includes:

a photosensitive unit 201, configured to acquire an image signal;

The readout unit 202 is used to read the image signal in the photosensitive unit;

A digitization unit 203, configured to convert the analog image signal into a digital signal;

And an output unit 204, including an output interface, for outputting digital signals;

The main chip 100 includes:

A photosensitive unit 101, configured to acquire an image signal;

The readout unit 102 is used to read the image signal of the photosensitive unit;

A digitization unit 103, configured to convert the analog image signal into a digital signal;

a processing unit 104, configured to process the digital signal to form image data;

The I/O unit 105 includes a data interface for outputting image data to the upper system; and receives digital signals from the slave chip 200 during the line blanking time of the master chip 100 in the master-slave mode.

The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing and embodiment:

First, a dual-camera device including a master chip 100 and a slave chip 200 is provided, and one of the cameras is set as the master chip 100 , and the other camera is set as the slave chip 200 . Please continue to refer to FIG. 2 , wherein the slave chip 200 includes: a photosensitive unit 201 for acquiring an image signal; a readout unit 202 for reading the image signal in the photosensitive unit; a digitization unit 203 for converting an analog image The signal is converted into a digital signal; and the output unit 204 includes an output interface, the output interface is connected with the data interface of the main chip input and output unit 105, and is used to output a digital signal to the main chip 100; the main chip 100 includes: photosensitive The unit 101 is used to acquire the image signal; the readout unit 102 is used to read the image signal of the photosensitive unit 101; the digitization unit 103 is used to convert the analog image signal into a digital signal; the processing unit 104 is used to process the digital signal Process and form image data; input and output unit 105 includes a data interface for outputting image data to the upper layer system; and in the master-slave mode, receive digital signals from the slave chip 200 during the line blanking time of the master chip 100 .

According to the first embodiment of the present invention, the master chip 100 communicates with the upper system in the DVP parallel port mode, and the data interface pins of the slave chip output unit 204 include a clock output pin and a data output pin and other pins, the master chip 100 includes 8 data output pins and other pins; one of the data output pins of the master chip 100 is used as a clock input pin, connected to the clock output pin of the slave chip 200 Any one of the other data output pins of the master chip 100 is connected to the data output pin of the slave chip 200.

According to a variation of the first embodiment of the present invention, the master chip 100 communicates with the upper system in the DVP parallel port mode, and the data interface pins of the slave chip output unit 204 include 1 clock output pin, 2 data Output pins and other pins, the master chip 100 includes 8 data output pins and other pins; use one of the data output pins of the master chip 100 as a clock input pin, connected to the slave chip 200 Clock output pins; any two of the other data output pins of the master chip 100 are connected to the data output pins of the slave chip 200 .

According to another variation of the first embodiment of the present invention, the master chip 100 communicates with the upper system in the DVP parallel port mode, and the data interface pins of the slave chip output unit 204 include 1 clock output pin, 3 Data output pins and other pins, the master chip 100 includes 8 data output pins and other pins; one of the data output pins of the master chip 100 is used as a clock input pin, connected to the slave chip 200 Any three of the other data output pins of the master chip 100 are connected to the data output pins of the slave chip 200 .

According to another variation of the first embodiment of the present invention, the master chip 100 communicates with the upper system in the DVP parallel port mode, and the data interface pins of the slave chip output unit 204 include 1 clock output pin, 4 Data output pins and other pins, the master chip 100 includes 8 data output pins and other pins; one of the data output pins of the master chip 100 is used as a clock input pin, connected to the slave chip 200 Any 4 of the other data output pins of the master chip 100 are connected to the data output pins of the slave chip 200 .

According to the second embodiment of the present invention, the master chip 100 communicates with the upper system in the SPI serial port mode, and the data interface pins of the slave chip output unit 204 include a clock output pin and a data output pin and other pins, the main chip 100 includes 8 data output pins and other pins; wherein, the main chip 100 uses any one of the 8 data output pins as the SPI data pin for communication with the upper system; Take one of the remaining data output pins of the main chip 100 as a clock input pin, and connect to the clock output pin of the slave chip 200; thereafter, select any one of the remaining main chip 100 data output pins, and connect to The data output pin of the slave chip 200.

According to a variation of the second embodiment of the present invention, the master chip 100 communicates with the upper system in the SPI serial port mode, and the data interface pins of the slave chip output unit 204 include 1 clock output pin, 4 Data output pins and other pins, the main chip 100 includes 8 data output pins and other pins; wherein, the main chip 100 uses any one of the 8 data output pins as an SPI for communication with the upper system Data pin; 1 of the remaining data output pins of the main chip 100 is used as a clock input pin, connected to the clock output pin of the slave chip 200; thereafter, select any 4 of the remaining main chip 100 data output pins One, connected to the data output pin of the slave chip 200.

According to another variation of the second embodiment of the present invention, the master chip 100 communicates with the upper system in the SPI serial port mode, and the data interface pins of the slave chip output unit 204 include 1 clock output pin, 2 Data output pins and other pins, the main chip 100 includes 8 data output pins and other pins; wherein, the main chip 100 uses any 2 of the 8 data output pins as the SPI for communication with the upper system Data pins; use 1 of the remaining data output pins of the main chip 100 as a clock input pin to be connected to the clock output pin of the slave chip 200; thereafter, select any 2 of the remaining main chip 100 data output pins One, connected to the data output pin of the slave chip 200.

According to another variation of the second embodiment of the present invention, the master chip 100 communicates with the upper system in the SPI serial port mode, and the data interface pins of the slave chip output unit 204 include a clock output pin, a Data output pins and other pins, the main chip 100 includes 8 data output pins and other pins; wherein, the main chip 100 uses any 4 of the 8 data output pins as the SPI for communication with the upper system Data pins; use one of the remaining data output pins of the master chip 100 as a clock input pin to be connected to the clock output pin of the slave chip 200; thereafter, select any one of the remaining master chip 100 data output pins One, connected to the data output pin of the slave chip 200.

Secondly, set the operating state of master chip 100 and slave chip 200, when making master chip 100 work in the state of row blanking, slave chip 200 works in row valid state, when master chip 100 works in row valid state, slave chip 200 works in the state of line blanking. Referring to Fig. 3, the operating clock frequency of the main chip 100 and the slave chip 200 can be set to the same frequency, so that when the main chip works in the effective state of the line, the slave chip works in the line blanking state; the main chip works in the line blanking In the state, the slave chip works in the active state.

Secondly, make the slave chip 200 output image data in the line active state, and the master chip 100 receive the image signal from the slave chip 200 in the line blank state.

According to the first embodiment of the present invention and its variations, the operating mode of the dual camera device includes a master-slave mode in which the master chip 100 works independently and the master-slave chip works simultaneously, and the master chip 100 and the upper system use a DVP parallel port mode communication. More specifically, during the master-slave mode of operation: obtain the image signal from the photosensitive unit 201 of the chip 200; read the image signal from the chip readout unit 202 and transmit the image signal to the digitization unit 203; the digitization unit 203 processes the The above image signal forms a digital signal, and in the time when 100 lines of the main chip are blanked and 200 lines of the slave chip are valid, the digital signal is input to the main chip input and output unit 105 through the DVP interface; the main chip processing unit 104 processes the input digital signal Process and form image data, and send the image data to the upper system through the DVP interface during the time when 100 lines of the master chip are active and 200 lines of the slave chip are blank. Wherein, the communication mode between the slave chip 200 and the master chip 100 can be serial port communication or parallel port communication. Preferably, the communication mode between the master chip and the master chip 100 can be a serial port communication mode with packet header. The transmitted data can be any bit, and has a flag bit, which is used for identifying and locating the main chip 100 . Further specifically, when the slave chip 200 is working, the data pins connected to the master chip 100 on the slave chip 200 are in the output state during the blanking time of the master chip 100 lines, and the data pins connected to the slave chip 200 on the master chip 100 are in the output state. The data pin is in the input state, and is used for the master chip 100 to receive digital signals from the slave chip 200; during the effective transmission time of the master chip 100 lines, the data pin connected to the master chip 100 on the slave chip 200 is in a high-impedance state , the data pins on the master chip 100 connected to the slave chips 200 are in an output state, and the image data is output to the upper layer system through the data pins of the master chip 100 . When the main chip 100 works alone: the photosensitive unit of the main chip acquires an image signal; the readout unit reads out the acquired image signal and transmits the image signal to the processing unit 104; the processing unit 104 processes the image signal to form an image The data is sent to the I/O unit 105; the I/O unit 105 outputs the image data to the upper system.

According to the second embodiment of the present invention and its variations, the operating modes of the dual camera device include a master-slave mode in which the master chip 100 works independently and the master-slave chip works simultaneously, and the master chip 100 and the upper system use an SPI interface. mode communication. Further specifically, during the master-slave working mode: the image signal is obtained from the photosensitive unit 201 of the chip 200; the image signal is read out from the chip readout unit 202 and the image signal is transmitted to the digitization unit 203; the digitization unit processes the The image signal forms a digital signal. Since the output pins of the slave chip 200 and the output pins of the main chip 100 use different main chip pins, no matter whether the 100 lines of the main chip are blanked or the 100 lines of the main chip are valid Here, the digital signal can be input to the main chip input and output unit 105; the main chip processing unit 104 processes the input digital signal to form image data, and in the time when 100 lines of the main chip are valid and 200 lines of the slave chip are blanked The image data is sent to the upper system through the SPI pin. Wherein, the communication mode between the slave chip 200 and the master chip 100 can be serial port communication or parallel port communication. Preferably, the communication mode between the master chip and the master chip 100 can be a serial port communication mode with packet header. The transmitted data can be any bit, and has a flag bit, which is used for identifying and locating the main chip 100 . When the main chip 100 works alone: the photosensitive unit 101 of the main chip 100 acquires an image signal; the readout unit 102 reads out the acquired image signal and transmits the image signal to the digitization unit 103 to form a digital signal, and the digital signal enters the processing unit 104 The processing unit 104 processes the digital signal to form image data, and sends it to the input and output unit 105; the input and output unit 105 outputs the image data to the upper system.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (2)

1. A method for data communication between two cameras, characterized in that: Provide a dual-camera device, set one of the cameras as the master chip, and set the other camera as the slave chip, wherein the master chip includes: a photosensitive unit for obtaining image signals; a readout unit for reading the photosensitive unit The image signal of the image; the digitization unit is used to convert the analog image signal into a digital signal; the processing unit is used to process the digital signal to form image data; the input and output unit includes a data interface and is used to output the image data to the upper system, and In the master-slave mode, during the line blanking time of the master chip, the digital signal from the slave chip is received; the slave chip includes a photosensitive unit for obtaining image signals; a readout unit is used for reading the photosensitive unit The image signal of the image; the digitization unit is used to convert the analog image signal into a digital signal; and the output unit includes an output interface, the output interface is connected with the data interface of the main chip input and output unit, and is used to output the digital signal to the main chip ; Set the working state of the master chip and the slave chip so that when the master chip works in the line blanking state, the slave chip works in the line valid state, and when the master chip works in the line valid state, the slave chip works in the line blanking state; Make the slave chip output digital signals in the active state of the row, and the master chip receives the digital signal from the slave chip in the blank state of the row. 2. A dual-camera processing device that realizes the method described in claim 1 is characterized in that, when working from the chip, in the time when the main chip line is blanked, the data pin connected with the main chip on the chip is output state, the data pin connected to the slave chip on the master chip is in the input state, and is used for the master chip to receive the digital signal from the slave chip; The pins are in a high-impedance state, and the data pins connected to the slave chip on the master chip are in an output state, and the image data is output to the upper system through the data pins of the master chip.

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