CN102157524B - Semiconductor integrated circuit - Google Patents

Abstract

A semiconductor integrated circuit (5) is provided with an internal circuit (4) in its center, and along the four sides of the semiconductor integrated circuit, I/O circuits (1, 2) and pads ( 3). The I/O circuit (2) is an I/O circuit for level 1 with one pad, and the I/O circuit (1) is for level 2 with two pads provided in a zigzag shape toward the internal circuit. In the I/O circuit, two types of I/O are provided as a whole, and the number of pads provided is equal to the number of required pads. The I/O circuit (2) for level 1 and the I/O circuit (1) for level 2 have power supply wiring for supplying power thereto, and these power supply wiring is a ring running in the direction in which the I/O circuits (1, 2) are arranged. Shaped, the power supply wiring transfer area (A) for transferring the power supply wiring between the first-level and second-level I/O circuits (1, 2) is provided at the four corners (C) of the semiconductor integrated circuit. Therefore, even in a semiconductor integrated circuit having a large number of pads, the area can be effectively reduced.

Description

semiconductor integrated circuit

This application is a divisional application of the application with the application number "200710165891.6", the application date is November 7, 2007, and the invention title is "semiconductor integrated circuit and multi-chip module".

technical field

The present invention relates to a semiconductor integrated circuit having I/O circuits and pads, which are interfaces with the outside, on the peripheral portion, and more particularly to a semiconductor integrated circuit whose number of pads is relatively small relative to the scale of the internal circuit. Many semiconductor integrated circuits.

Background technique

Conventionally, in a semiconductor integrated circuit as a semiconductor chip, as shown in FIG.

In recent years, in response to the miniaturization of the process, more functions than before can be provided in one semiconductor integrated circuit, and the number of I/O circuits and pads provided as an interface with the outside is also increasing. However, low-voltage transistors used in memory circuits and logic circuits, and high-voltage transistors used in analog circuits and I/O circuits, etc., have different effects of area reduction due to miniaturization. Compared with a memory circuit or a logic circuit whose area is greatly reduced due to miniaturization of processing, the area of an analog circuit or an I/O circuit is hardly reduced. The unbalanced area reduction effect leads to an increase in the proportion of the area occupied by the analog circuit or the I/O circuit. For example, as shown in FIG. 25, if the internal circuit 3 including a memory circuit or a logic circuit, etc., is provided with a number of I/O circuits and pads necessary for a semiconductor integrated circuit on the periphery, then the I/O circuit 1 and the pad 2 The outer peripheral frame formed by the arrangement becomes larger than the internal circuit 3, a large space is generated between the internal circuit 3, the I/O circuit 1 and the pad 2, and an ineffective area is generated. Therefore, even if the manufacturing process is miniaturized, the There is a disadvantage that the area cannot be reduced.

Therefore, a pad arrangement method has previously been proposed, such as shown in FIG. 26, by arranging the pads in two levels so that the area of the internal circuit 3 is the same as the outer circumference formed by the arrangement of the I/O circuit 1 and the pads 2. The balance between the frames is good, so that even if many pads are provided, the area of the semiconductor integrated circuit can be effectively reduced compared with the case where the pads are arranged in a single-stage arrangement. This proposal is disclosed in Patent Document 1, for example.

[Patent Document 1] JP-A-45723 Gazette

However, when the pads are provided in two stages as described above, the two-stage pad I/O circuit is set to have a width and a height corresponding to the size and arrangement pitch of a plurality of provided pads. In addition, in order to supply power to each of the plurality of I/O circuits arranged on the outer periphery, power supply wiring extending in the direction in which the I/O circuits are arranged is formed inside. When the I/O circuits are arranged adjacently, The internal power supply lines are connected to each other and are generally formed in a ring shape. According to this, even the I/O circuit for pads of the second stage can be formed in a shape whose width and height are limited to one type, similarly to the I/O circuit for pads of the first stage.

According to this fact, in the above-mentioned conventional semiconductor integrated circuit in which the pads are provided in two stages, even if it is hardly necessary to set the number of pads in two stages in all sides of the semiconductor integrated circuit, the Since the pads are arranged in two levels over the entire periphery, redundant pads that are not used for input and output of signals are generated. With regard to such redundant pads, the power supply was previously distributed and used to strengthen the power supply for the purpose of IR reduction.

However, in the above-mentioned conventional semiconductor integrated circuit in which pads are provided in two stages, as shown in FIG. In a semiconductor integrated circuit in which pads are set to two levels, for example, when there are 5 redundant pads, if 5 redundant pads 2 are provided, as shown by the dotted line in FIG. 26, the area will increase accordingly. The area required for the arrangement of five redundant pads 2 weakens the area reduction effect.

Contents of the invention

The present invention focuses on the above-mentioned problems, and an object of the present invention is to reduce the number of redundant pads in a semiconductor integrated circuit provided with multi-level pads on the outer periphery, and to further enhance the area reduction effect.

In order to achieve the above object, the I/O circuit is not limited to one in the present invention, but uses two kinds of I/O circuits in the I/O circuit for the 1-level pad or the I/O circuit for the multi-level pad. Number of pads.

At this time, when at least two types of I/O circuits are used, when two different types of I/O circuits are arranged side by side, it is assumed that the internal power supply wiring between these two I/O circuits is not well connected with each other. Therefore, it is necessary to arrange a region for well connecting the power supply wiring between these two I/O circuits, but it takes effort to arrange this region so that the effect of reducing the area is not reduced.

That is, the semiconductor integrated circuit of the invention according to claim 1 has: an internal circuit; , and a plurality of I/O circuits that can be provided with pads above, the above-mentioned multiple I/O circuits pass through: in the direction toward the above-mentioned internal circuit, the above-mentioned pads are provided with n-level n (n is an integer greater than 1) level I/O circuit; and an I/O circuit for m stages in which the pads are arranged in m (m is an integer > n) stages in the direction toward the internal circuit, and the heights in the direction toward the internal circuit are different. At least two I/O circuits are formed.

The invention described in Claim 2 is the semiconductor integrated circuit according to Claim 1 above, wherein the plurality of I/O circuits include an I/O circuit for the n-stage and an I/O circuit for the m-stage, respectively. The power supply wiring extending in the direction in which the I/O circuits are arranged, and at least one of the power supply wirings has a different height position from the outer end; between the n-level I/O circuits and the m-level I/O circuits arranged in a row, a There is a power supply wiring transit area in which power supply wiring for connecting the power supply wiring of the n-stage I/O circuit and the m-stage I/O circuit is formed.

The invention according to claim 3 is the semiconductor integrated circuit according to claim 2, wherein the n-stage I/O circuit and the m-stage I/O circuit are located at corners forming the semiconductor integrated circuit. The ends of the two sides; the above-mentioned power supply wiring transition area is formed at the above-mentioned corner.

The invention according to Claim 4 is the semiconductor integrated circuit according to Claim 1 above, wherein the plurality of I/O circuits each have an I/O circuit for the n-stage and an I/O circuit for the m-stage Power supply wiring extending in the direction in which the I/O circuits are arranged, and at least one of the power supply wirings has a different height from the outer end; between adjacent n-level I/O circuits and m-level I/O circuits spaced apart by a given distance.

The invention according to Claim 5 is the semiconductor integrated circuit according to Claim 1 above, wherein the plurality of I/O circuits include an I/O circuit for the n-stage and an I/O circuit for the m-stage, respectively. Power supply wiring extending in the direction in which the I/O circuits are arranged, and at least one of the power supply wirings has a different height from the outer end; between adjacent n-level I/O circuits and m-level I/O circuits There is a protective circuit for electrostatic discharge protection.

The invention according to Claim 6 is the semiconductor integrated circuit according to any one of Claims 2 to 5, wherein the power supply wiring of the I/O circuit for the n-stage is not connected to the I/O circuit for the m-stage. The number of power supply wires included in the circuit differs from one another.

The invention according to Claim 7 is the semiconductor integrated circuit according to any one of Claims 2 to 6, wherein the power wiring of the I/O circuit for the n-stage is connected to the I/O circuit for the m-stage. The power wiring of the circuit has different wiring widths.

The invention according to Claim 8 is the semiconductor integrated circuit according to any one of Claims 2 to 7, wherein the power wiring of the I/O circuit for the n-stage is connected to the I/O circuit for the m-stage. The power supply wiring included in the circuit is formed on different wiring layers.

The invention according to Claim 9 is the semiconductor integrated circuit according to any one of Claims 2 to 8, wherein the power supply wiring of the I/O circuit for the n-stage is connected to the I/O circuit for the m-stage. The power supply wiring included in the O circuit has a different number of wiring layers.

The invention according to Claim 10 is the semiconductor integrated circuit according to any one of Claims 1 to 9, wherein the semiconductor integrated circuit is a rectangle having four sides; The same type of I/O circuits for n-level or m-level is installed on the two sides of one group; one of the two sides of the other group is provided with the n-level circuit set on the two sides of the above-mentioned one group. I/O circuits with different stages of I/O circuits for use or m levels.

The invention according to claim 11 is the semiconductor integrated circuit according to any one of the above-mentioned claims 1 to 10, characterized in that: on one side of the semiconductor integrated circuit, a plurality of n-level I/O circuits are arranged in a row; The arrangement pitch of the plurality of I/O circuits for n stages arranged on one side is set in consideration of the arrangement pitch of the plurality of I/O circuits arranged on one side of another semiconductor integrated circuit.

The multi-chip module of the invention according to claim 12 has a semiconductor chip constituting the semiconductor integrated circuit according to any one of the above-mentioned claims 1 to 11, and a semiconductor chip constituting another semiconductor integrated circuit, and is provided in the above-mentioned claim 11. The plurality of I/O circuits for n stages on the above-mentioned one side of the semiconductor integrated circuit and the plurality of I/O circuits provided on one side of the other semiconductor integrated circuit are opposed to each other and connected by inter-chip wiring. .

In an embodiment of the present invention, in the semiconductor integrated circuit, the plurality of n-level I/O circuits and the plurality of m-level I/O circuits are arranged in a row, and the plurality of n-level I/O circuits arranged in a row In the entirety of the I/O circuits for the m-level and the m-level, the number of pads provided in the direction toward the internal circuit is plural, and the plurality of pads provided in the above-mentioned plurality of I/O circuits for the n-stage are staggered from each other in a zigzag pattern. The plurality of pads provided in the plurality of m-level I/O circuits are also arranged in a zigzag shape, offset from each other.

The invention according to Claim 14 is the semiconductor integrated circuit according to any one of Claims 1 to 13 above, characterized in that all of the I/O circuits for n-stages and the I/O circuits for m-stages provided are , the total number of pads located at a given level and the total number of pads located at a level one level higher than the above-mentioned given level are different from each other.

The invention according to Claim 15 is the semiconductor integrated circuit according to any one of Claims 1 to 14, wherein the width of the arrangement direction of the n-stage I/O circuit and the m-stage I/O circuit is different from each other.

The invention according to Claim 16 is the semiconductor integrated circuit according to any one of Claims 1 to 15, wherein the I/O circuit for the n-stage and the I/O circuit for the m-stage are separated from each other by drain The total gate width of the transistors with poles directly connected to the pads is equal.

The invention according to claim 17 is the semiconductor integrated circuit according to claim 16, wherein in the I/O circuit for the n-stage and the I/O circuit for the m-stage, the drain is directly connected to the same pad. The conduction type transistor has a multi-finger structure; each of the above-mentioned multi-finger structures has the same gate width as each other.

The invention according to Claim 18 is the semiconductor integrated circuit according to any one of Claims 1 to 17, wherein the I/O circuit for the n-stage and the I/O circuit for the m-stage are mutually realized. Transistors of the same function have the same gate length.

The invention according to Claim 19 is the semiconductor integrated circuit according to any one of Claims 1 to 17, wherein the I/O circuit for the n-stage and the I/O circuit for the m-stage are mutually realized. Transistors of the same function have the same gate width.

The invention according to Claim 20 is the semiconductor integrated circuit according to any one of Claims 1 to 19, wherein the width of the arrangement direction of the n-stage I/O circuits is larger than that of the m-stage I/O circuits. The width of the O circuit in the arrangement direction is large; the height of the I/O circuit for the n-stage toward the internal circuit is lower than the height of the I/O circuit for the m-stage toward the internal circuit.

As described above, in the inventions described in claims 1 to 15, since at least two stages of I/O circuits with different numbers of pad stages arranged in the direction toward the internal circuit are used, for example, in the previous FIG. 26 In the semiconductor integrated circuit, if I/O circuits for pads of the second level are arranged on the top, bottom, and left sides, and I/O circuits for pads of the first level are arranged on the right, the area on the right side of the dotted line shown in the figure can be reduced. , so that the area of the semiconductor integrated circuit can be further reduced.

In addition, the data of the I/O circuit can be reused as a component library. That is, in the past, corresponding to the size of the internal circuit or the number of required pads, the number of stages of pads or the height and width of the I/O circuit were independently set to reduce the area of the semiconductor integrated circuit. However, since it is a dedicated I/O circuit, Therefore, it is difficult to reuse it for new semiconductor integrated circuits. However, in the present invention, since the area of the semiconductor integrated circuit is reduced by combining the I/O circuit for the n-stage and the I/O circuit for the m-stage, it is not necessary to provide these I/O circuits for the n-stage and m-stage. Dedicated to specific semiconductor integrated circuits. Therefore, only by combining existing n-level and m-level I/O circuits, it is possible to cope with various new semiconductor integrated circuits.

In particular, in the invention described in claim 3, since the power supply wiring transfer region is formed at the corner of the semiconductor integrated circuit, the corner can be effectively used, and it can also be provided on each side of the semiconductor integrated circuit except the corner. , only configure multiple I/O circuits and pads.

In addition, in the invention described in claim 6, two I/O circuits of mutually different numbers of stages are located adjacent to each other on two sides constituting the corner portion of the semiconductor integrated circuit. Therefore, if these two I/O circuits are pads for example for level 2, 4 pads are densely located near this corner, so when mounted into a semiconductor package, these pads are connected by leads It becomes difficult to connect to each pad of the semiconductor package, but for example, when the I/O circuit for the 2nd-level pad is adjacent to the I/O circuit for the 1st-level pad, only 3 pads are located near the corner, Therefore, the connection of the above-mentioned lead wires becomes relatively easy.

Furthermore, in the inventions described in claims 7 to 10, since the types of the I/O circuit for the n-stage and the I/O circuit for the m-stage are different from each other, the number or wiring width of the power supply wiring arranged inside can be independently set. , or the configured wiring layers and their number of wiring layers, and make them different from each other.

In addition, in the inventions described in claims 11 and 12, in a multi-chip module including both a semiconductor chip having this semiconductor integrated circuit and a semiconductor chip having another semiconductor integrated circuit, one side of this semiconductor integrated circuit is connected to the above-mentioned When the sides of other semiconductor integrated circuits are facing each other, and the pads of the multi-I/O circuits provided on each side are connected by wires, since the arrangement pitches of the I/O circuits of these semiconductor integrated circuits are almost equal , so it is possible to make the lengths of the leads connecting the pads equal to each other and shorter. Therefore, not only the ease of assembly can be improved, but also the variation in characteristics between pads that input and output different signals can be suppressed, and high-speed interface characteristics can be obtained.

In addition, in the inventions described in claims 16 to 20, since the electrical characteristics of the respective I/O circuits are equal to each other among the various I/O circuits having different numbers of stages, when these I/O circuits are mixed and mounted on the In the case of one semiconductor integrated circuit, there is no need to consider which stages of I/O circuits are allocated to each signal terminal of these semiconductor integrated circuits, and the degree of freedom in the arrangement of signal terminals is improved.

As described above, according to the inventions described in technical solutions 1 to 15, since at least two types of I/O circuits with different numbers of pad stages are used, the area of the semiconductor integrated circuit can be further reduced, and the I/O circuits can be further reduced. The effect of reusing the data of the O circuit as a component database.

In particular, according to the invention described in claim 3, since the power supply wiring transfer region is formed at the corner of the semiconductor integrated circuit, the corner can be effectively used to prevent the semiconductor integrated circuit from being damaged due to the presence of the power supply wiring transfer region. Reduced area reduction effect.

In addition, according to the invention described in claim 6, it is possible to prevent the pads located at the corners of the semiconductor integrated circuit from being densely packed, and to easily mount these pads in the semiconductor package.

Furthermore, according to the inventions described in claims 7 to 10, the number of power supply wirings and wiring widths arranged inside can be independently set for the n-stage I/O circuit and the m-stage I/O circuit, or The configured wiring layer and the number of the wiring layer.

In addition, according to the inventions described in claims 11 and 12, when this semiconductor integrated circuit is combined with other semiconductor integrated circuits as a multi-chip module, in addition to the ease of combination, it is also possible to suppress the signal between pads. Deviations in characteristics are propagated, and high-speed interface characteristics are obtained.

In addition, according to the inventions described in claims 16 to 20, the electrical characteristics of the various I/O circuits with different numbers of stages are equal to each other, so even if these I/O circuits are mixed and mounted on In the case of one semiconductor integrated circuit, there is no need to consider which stage of I/O circuits each signal terminal of these semiconductor integrated circuits is allocated to, and it is possible to improve the degree of freedom in arrangement of the signal terminals.

Description of drawings

FIG. 1 is a schematic diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a modified example of the semiconductor integrated circuit of the first embodiment.

3( a ) is a diagram showing the state of power supply wiring in the first-stage I/O circuit included in the semiconductor integrated circuit of FIG. 1 , and FIG. This is a diagram showing how the power supply wiring in the I/O circuit is used.

FIG. 4 is a diagram showing a power supply wiring transit area provided in the semiconductor integrated circuit.

FIG. 5 is a diagram showing a semiconductor integrated circuit provided with the power supply wiring transition region.

FIG. 6 is a diagram showing a layout in which the I/O circuit for the first level and the I/O circuit for the second level are separated by a given distance when the power supply wiring of the I/O circuit of the semiconductor integrated circuit is not in a ring shape. picture.

7 is a diagram showing an ESD protection circuit provided between the first-level I/O circuit and the second-level I/O circuit when the power supply wiring of the I/O circuit of the semiconductor integrated circuit is not looped.

FIG. 8 is a diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 9 is a diagram showing the layout of power supply wiring in a power supply wiring transit region included in the semiconductor integrated circuit.

FIG. 10 is a diagram showing a modified example of the semiconductor integrated circuit.

FIG. 11 is a diagram showing another modified example of the semiconductor integrated circuit of the second embodiment.

FIG. 12 is a diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 13 is a diagram showing pads removed from the structure of the semiconductor integrated circuit in FIG. 12 .

FIG. 14 is a diagram showing a first modified example of the semiconductor integrated circuit.

FIG. 15 is a diagram showing a second modified example of the semiconductor integrated circuit.

FIG. 16 is a diagram showing a third modified example of the semiconductor integrated circuit.

FIG. 17 is a diagram showing a fourth modification example of the semiconductor integrated circuit.

FIG. 18 is a diagram showing a fifth modified example of the semiconductor integrated circuit.

19( a ) is a diagram showing the layout of the power supply wiring in the first-stage I/O circuit in the semiconductor integrated circuit according to the fourth embodiment of the present invention, and FIG. It is a diagram of the layout of the power supply wiring in the I/O circuit for the stage.

20( a ) is a diagram showing another layout of the power supply wiring in the I/O circuit for the first stage in the semiconductor integrated circuit of the fourth embodiment, and FIG. 20( b ) is a diagram showing the second stage in the semiconductor integrated circuit. Figure 20(c) is a sectional view of line B-B in FIG. 20(a), and FIG. 20(d) is a sectional view of line A-A in FIG. 20(b).

21( a ) is a layout diagram showing a wiring for supplying a potential to a pad of a first-stage I/O circuit in a semiconductor integrated circuit according to the fourth embodiment of the present invention, and FIG. 21( b ) is a layout diagram of FIG. 21( a ). The cross-sectional view of line c-c, FIG. 21(c) is a layout diagram showing the wiring for supplying potentials to the pads of the 2-level I/O circuit in this semiconductor integrated circuit, and FIG. 21(d) is d-d of FIG. 21(c) Line Profile.

FIG. 22( a ) is a diagram showing a multi-chip module according to a fifth embodiment of the present invention, and FIG. 22( b ) is an enlarged view of a portion surrounded by a dotted line in FIG. 22( a ).

FIG. 23 is a diagram showing the structure of a multi-chip module compared with the multi-chip module of the fifth embodiment.

FIG. 24 is a diagram showing a conventional semiconductor integrated circuit.

FIG. 25 is a diagram showing an increase in the number of required pads in the semiconductor integrated circuit.

FIG. 26 is a diagram showing a semiconductor integrated circuit in which disadvantages of an increase in the number of necessary pads are reduced.

27 is a circuit diagram showing an I/O circuit of a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 28 is a layout diagram in a case where the I/O circuit is constituted by two-stage I/O circuits.

FIG. 29 is a layout diagram in a case where the I/O circuit is constituted by a first-stage I/O circuit.

In the figure: 1...I/O circuit for level 2, 2...I/O circuit for level 1, 3...pad, 4...internal circuit, 5...semiconductor integrated circuit, 6 ...I/O circuits for level 3, 10a, 10b, 10c...VDD power supply wiring, 11a, 11b, 11c...VSS power supply wiring, A, A'...power supply wiring transition area, 13. ..ESD protection circuit, C...corner, 16, 17...wiring for supplying potential to pad, 20, 21...semiconductor chip, 25...wiring between chips, 31...pre-buffer circuit, 32...output transistor, 33...ESD protection transistor, 34...input circuit, 35...pad, MFp, MFn, MFp1, MFp2, MFn1, MFn2...multi-finger structure.

Detailed ways

Embodiments of the present invention will be described below with reference to the accompanying drawings.

(first embodiment)

FIG. 1 shows the semiconductor integrated circuit of this embodiment.

A semiconductor integrated circuit 5 serving as a semiconductor chip in the figure has a rectangular shape, and an internal circuit 4 is provided in the center. On the outside of the above-mentioned internal circuit 4, a plurality of I/O circuits 1, 2 are provided along the four sides of the outer periphery. These I/O circuits are used to output signals of the internal circuit 4 to the outside or input external signals to the internal circuit 4, and the pads 3 are provided thereon.

There are two kinds of the above-mentioned plurality of I/O circuits. The I/O circuit 1 is an I/O circuit for m (m=2) stages in which two pads 3 can be arranged in a direction facing the above-mentioned internal circuit 4. The O circuit 2 is an I/O circuit for n (n=1 (n<m)) stages in which one pad 3 can be provided in a direction facing the above-mentioned internal circuit 4 . In the arrayed plurality of I/O circuits 1 for secondary use, the plurality of pads 3 are arranged in a zigzag shape, shifted in the direction facing the internal circuit 4 and in the edge direction of the semiconductor integrated circuit 5 . The pads 3 provided in the I/O circuit 1 for the first level and the I/O circuit 1 for the second level have the same shape. In the I/O circuit 1 for the second stage, since the pads are arranged in a zigzag shape, it is also set such that the width W2 of the I/O circuit 1 for the second stage is larger than that of the I/O circuit 2 for the first stage. The width W1 is narrow, and the height H2 toward the internal circuit 4 is higher than the height H1 of the first-stage I/O circuit 2 . In addition, the total number of first-level pads 3 located on the outside is 22 in the figure, the total number of pads 3 for second-level located on the inside is 11, and the total number of pads 3 located on the outside is large.

Another semiconductor integrated circuit of this embodiment is illustrated in FIG. 2 . The semiconductor integrated circuit 5 shown in the figure is different from the type of I/O circuit of the semiconductor integrated circuit shown in FIG. O circuit.

In the I/O circuits 1 and 6 where the number of stages of pads is more than that of stage 1, when mounting a semiconductor package, the length of the lead wire connected is longer than that of the inner pads, so it is allocated for low-speed interface, stage 1 The I/O circuit 2 is assigned as a high-speed interface.

1 and 2 exemplify a semiconductor integrated circuit having two types of I/O circuits, but of course, the present invention may provide I/O circuits having three or more stages of pads. In addition, the number of stages in which pads 3 are provided is not limited to 1st, 2nd, and 3rd.

As described above, in this embodiment, at least two types of I/O circuits 1 , 2 , and 6 having different numbers of stages of pads are provided. Therefore, for example, comparing FIG. 1 with the previous FIG. 26, it can be found that in FIG. Compared with the structure for two stages, the area can be reduced in the region on the right side of the dotted line shown in FIG. 26 .

FIG. 3 shows the layout of power supply lines (power supply rails) provided in the first-level I/O circuit 2 and the second-level I/O circuit 1 included in the semiconductor integrated circuit of FIG. 1 . The power supply wiring is arranged in a ring shape along four sides of the semiconductor integrated circuit in the I/O circuit as a power supply for the I/O circuit. In the I/O circuit 2 for the first stage shown in FIG. (horizontal in the figure) upper extension setting. In the I/O circuit 2 for two stages shown in FIG. In Figure 3(a) and (b), ESDp is the ESDp protection area where multiple p-channel transistors of the unit capacitance for electrostatic discharge (ESD) are arranged in a row, and ESDn is the n-channel transistor of the unit capacitance for electrostatic discharge (ESD). The ESDn protection area is formed by arranging multiple transistors, and the areas of the two protection areas are almost the same. In order to effectively protect these protection areas from ESD, the ESDp protection area ESDp is provided directly under the VDD power supply wirings 10a, 10b, and the ESDn protection area ESDn is provided immediately below the above-mentioned VSS power supply wirings 11a, 11b. The I/O circuit 2 for level 1 in FIG. 3(a) has a large width W1, and the I/O circuit 1 for level 2 in FIG. The guard regions ESDp, ESDn in the I/O circuit 1 have a shape extending in the height direction compared with the guard regions ESDp, ESDn in the I/O circuit 2 for the first stage. Therefore, the number of power supply wirings 10b and 11b in the I/O circuit 1 for the second stage is also arranged more in the direction of the height H2, and the number of the power supply wirings 10a and 11a in the I/O circuit 2 for the first stage (3 lines) ) compared to 6. As a result, in the I/O circuit 2 for the first stage and the I/O circuit 1 for the second stage, the VDD power supply lines 10a, 10b and the VSS power supply lines 11a, 11b are connected from the outer end of the I/O circuit ( In Fig. 3 (a), (b), the height positions from the lower end) are different. In this way, since the height positions of the power wiring between the first-level and second-level I/O circuits 1 and 2 are different, when the first-level I/O circuit 2 and the second-level I/O circuit 1 are adjacent to each other, It is necessary to set up a power wiring transition area for connecting the power wiring of the two.

FIG. 4 is a diagram showing such a power supply wiring transfer region. In the figure, there is a space between the adjacent I/O circuits 2 for level 1 and I/O circuits 1 for level 2. In this space, a power supply wiring transition area A is set. In this power supply wiring transition area A is provided with a transition VDD power supply wiring 10c connected to the VDD power supply wirings 10a and 10b, and a transition VDD power supply wiring 11c connected to the VSS power supply wirings 11a and 11b.

FIG. 5 shows an example of a semiconductor integrated circuit provided with the above-mentioned power supply wiring transit region A. As shown in FIG. In the figure, the power wiring transition area A is located on two sides of the semiconductor integrated circuit 5, and is respectively arranged in the middle of each side.

In addition, when it is not necessary to arrange the power supply wiring for the I/O circuit in a ring shape as described above, as shown in FIG. Open the given distance D to set it. The given distance D is a distance that satisfies design rules in the manufacturing process of semiconductor integrated circuits. In addition, as shown in FIG. 7, the VSS power supply wiring 11a of the I/O circuit 2 for the first stage and the VSS power supply wiring 11b of the I/O circuit 1 for the second stage may be connected through the ESD protection circuit 13 using a diode element. Ensure ESD withstand voltage. In this case, the VDD power supply lines 10a and 10b are not connected.

(second embodiment)

Next, a second embodiment of the present invention will be described.

FIG. 8 shows the semiconductor integrated circuit of this embodiment. In this semiconductor integrated circuit, the I/O circuit 1 for the second stage is provided on the upper side, the lower side, and the left side, and the I/O circuit 2 for the first stage is provided on the right side. At the corners C of the lower right part and the upper right part of the semiconductor integrated circuit 5, there are provided power supply wirings for switching the power supply wiring between the I/O circuit 2 for the first stage and the I/O circuit 1 for the second stage. Transit area A. That is, in other words, the present embodiment adopts a structure in which the same type of I/O circuits are provided on each side of the semiconductor integrated circuit 5, and does not change the type of I/O circuits from one side to two levels on one side. For level use or from level 2 use to level 1 use, change the number of stages where pads are provided on the corners. To illustrate the specific situation of the installation on the corner C at the lower right, the internal configuration of the above-mentioned power wiring transition area A is as shown in FIG. 9 .

In this way, if the power wiring transition area A is provided on the corner portion C, the following effects are produced. That is, the shape of the power supply wiring transit area A is not a quadrilateral because the power supply wiring 10c, 11c therein has portions extending in an oblique direction as shown in FIG. As shown in FIG. 5 of the above-mentioned first embodiment, if it is placed in the middle of one side of the semiconductor integrated circuit 5, it can be seen from FIG. 5 that the area for installing the internal circuit 4 has a complex shape instead of a quadrangle. Therefore, the arrangement and wiring processing of the signal wiring in the internal circuit 4 are complicated, and the area protruding from the rectangle becomes a useless area in various cases. On the other hand, in this embodiment, as shown in FIG. 8 , the area where the internal circuit 4 is provided can be kept in a rectangular shape. In the present embodiment, the corners of the semiconductor integrated circuit are used only for the purpose of connecting power rails or arranging markings required for assembly, and the corners are effectively utilized.

FIG. 10 shows a modified example of the present embodiment, in which instead of providing the I/O circuit 1 for the second stage on the lower side as in FIG. 8 described above, the I/O circuit 2 for the first stage is provided. Accompanying this change, the power supply wiring transit area A is provided in the lower left corner C instead of the lower right corner C.

Another modified example is shown in FIG. 11 . In the figure, the I/O circuits 1 for the second stage are arranged on the right and the bottom, and the I/O circuits 6 for the third stage are arranged on the upper and left sides. Therefore, the power supply wiring transition area A' is set at the two corners of the upper right and the lower left.

(third embodiment)

Next, a third embodiment of the present invention will be described.

FIG. 12 shows the semiconductor integrated circuit of this embodiment. FIG. 13 shows a view after the pad 3 is removed from the structure of the semiconductor integrated circuit of FIG. 12 . This embodiment takes into account the ease of wire connection when the semiconductor integrated circuit is mounted in a semiconductor package.

In the semiconductor integrated circuit 5 in the figure, the I/O circuits 2 for the first stage are arrayed on the opposite sides of the upper and lower sides, and the I/O circuits 1 for the second stage are arrayed on the opposite sides of the left and right sides. . Therefore, the power wiring transition area A is provided on all four corners. In other words, at each corner, the first-level I/O circuit 2 and the second-level I/O circuit 1 are adjacent to each other, and the second-level I/O circuits 1 are not adjacent to each other.

Therefore, in this embodiment, the I/O circuit 2 for the first stage and the I/O circuit 1 for the second stage are adjacent to each other in the vicinity of each corner, so compared with the case where the I/O circuits 1 for the second stage are adjacent to each other, The arrangement density of pads 3 near the corners is reduced. Therefore, it is possible to work well and simply when connecting the respective lands at these corners to the respective pins of the semiconductor package with wires for mounting, or when touching the respective lands with a probe during wafer inspection. In general, the higher the arrangement density of the pads in the corners, the greater the encirclement of the wiring in the semiconductor package and the longer the wiring length, making it possible to equalize the length of each wiring, resulting in deterioration of signal propagation characteristics, but this embodiment This situation can be alleviated in a way.

FIG. 14 shows a modified example of the semiconductor integrated circuit shown in FIG. 12. On the two facing sides of the upper and lower sides, 2-stage I/O circuits 1 are arranged in a row, and on the two facing sides of the left and right, The IO circuits 6 for three stages are arranged in a row. FIG. 15 shows a structure in which the arrangement density of the pads 3 is further reduced by deleting some of the pads 3 provided near the corners in the semiconductor integrated circuit of FIG. 14 .

Another modified example is shown in FIG. 16 . In the semiconductor integrated circuit 5 in the figure, the I/O circuits 2 for the first stage are arranged in a row on the left and the right sides facing each other, the I/O circuits 1 for the second stage are arranged in a row on the upper side, and the I/O circuits 1 for the second stage are arranged in a row on the lower side. Level with 1/O circuit 2. Therefore, in this modified example, since the I/O circuit 2 for the first stage is adjacent to the I/O circuit 1 for the second stage only in the upper left corner and the upper right corner, it is possible to set two kinds of I/O circuits for the number of stages. In the case of the /O circuit, the arrangement density of the pads 3 at the corner is the lowest. The structure of FIG. 17 is: In the semiconductor integrated circuit of FIG. 16, the I/O circuit 2 for the first stage is changed to the I/O circuit 1 for the second stage, and the I/O circuit 1 for the second stage is changed to the third stage. With I/O circuit 6. In the semiconductor integrated circuit of FIG. 18 , on the opposite sides of the upper and lower sides, three-stage I/O circuits 6 are arranged in a row, on the right side, two-stage I/O circuits 1 are arranged in a row, and on the left side, three-stage I/O circuits 1 are arranged in a row. Use 1/O circuit 6. Therefore, in the two corners of the upper right part and the lower right part in this modified example, the I/O circuit 1 for the second stage and the I/O circuit 6 for the third stage are adjacent to each other, thereby reducing the stress on the pad 3 near the corners. Configuration density.

(fourth embodiment)

A fourth embodiment of the present invention is shown in FIG. 19 .

The figure shows the layout structure of power supply lines provided inside the first-level I/O circuit 2 and the second-level I/O circuit 1 included in the semiconductor integrated circuit of FIG. 1 .

The I/O circuit 2 for level 1 shown in FIG. 19(a) is a different I/O circuit from the I/O circuit 1 for level 2 shown in FIG. 19(b). The shapes and numbers of 10a, 10b and VSS power supply lines 11a, 11b can also be individually set. Therefore, between the I/O circuit 2 for the first stage and the I/O circuit 1 for the second stage, the number of VDD power supply lines 10a and 10b is individually set to 3 and 5, and the wiring widths are also different from each other. , set the wiring width in the I/O circuit 2 for level 1 to be narrow.

A modified example of this embodiment is shown in FIG. 20 . The I/O circuit 2 for the first stage in FIG. 20(a) and the I/O circuit 1 for the second stage in FIG. 20(b) are mutually provided as interconnections with the VDD power supply wiring 10a, 10b and the VSS power supply wiring 11a, 11b. The width is the same, but in Figure 20(c) and (d) showing the c-c line section and the d-d line section of Figure 20(a) and (b), the first-stage I/O in this Figure 20(c) The VDD power supply wiring 10 a and the VSS power supply wiring 11 a of the circuit 2 are wired on the second wiring layer, and the signal wiring 15 in the I/O circuit 2 is wired on the first and third wiring layers. In addition, the VDD power supply wiring 10b and the VSS power supply wiring 11b of the I/O circuit 1 for the second stage in FIG. 20(d) are wired on the third wiring layer, and the I/O circuit 2 is wired on the first and second wiring layers. within the signal wiring 15. In this way, in this modified example, the wiring layers of the power supply wiring provided inside may be different between the first-stage I/O circuit 2 and the second-stage I/O circuit 1 .

Another modified example of this embodiment is shown in FIG. 21 . In the I/O circuit 2 for level 1 in FIG. 21(a), the wiring 16 that supplies the potential to the internal circuit 4 (upper in FIG. 21 ) is on the same wiring as the pad 3 as shown in FIG. 21(b) layer towards pad 3. On the other hand, in the I/O circuit 1 for two stages shown in FIG. 21 (d) as shown in FIG. 21 (d), wiring through a plurality of via holes 18 in In the wiring layer below layer 1. As a result, in the I/O circuit 2 for level 1, the wiring layer where the pad potential supply wiring 17 of the I/O circuit 1 for level 2 is wired becomes free. The VDD power supply wiring 10a and the sub-VDD power supply wiring 10a' of the VSS power supply wiring 11a and the sub-VSS power supply wiring 11a' are provided with vias 19 connecting the two wirings.

Therefore, in this modified example, in the I/O circuit 1 for the first stage, the power supply wiring is wired on two wiring layers, and in the I/O circuit 1 for the second stage, it is wired on one wiring layer. Between the I/O circuits 1 and 2 for the stage and the stage 2, the number of wiring layers of the power supply wiring is different. Such a configuration can be adopted because the I/O circuits 1 and 2 for the first stage and the second stage can be independently designed by different circuits.

(fifth embodiment)

Next, a fifth embodiment of the present invention will be described.

FIG. 22 shows a configuration example in the case where the present semiconductor integrated circuit is included in a multi-chip module.

In FIG. 22(a), 20 is a semiconductor chip constituted by a system LSI as this semiconductor integrated circuit. Reference numeral 21 is a semiconductor chip formed of a memory chip or an analog LSI which is another semiconductor integrated circuit, and is mounted on the semiconductor chip 20 formed of this semiconductor integrated circuit. These two semiconductor chips constitute a multi-chip module, which is mounted in a semiconductor package (System-in Package).

As shown in FIG. 22(b), in a semiconductor chip 21 of another semiconductor integrated circuit, a plurality of first-level I/O circuits 2 having one pad 3 are generally arranged on one side. In addition, in the case where the structure in which the semiconductor chip 20 of this semiconductor integrated circuit is connected to the first-stage I/O circuit 2 of the semiconductor chip 21 of the above-mentioned other semiconductor integrated circuit is known in advance, it is considered that the pads 3 of the I/O circuit 2 are arranged as an array. The arrangement pitch of the I/O circuits 2 for the first stage of the semiconductor chip 21 of the above-mentioned other semiconductor integrated circuit of the I/O circuit on the side is set at an arrangement pitch almost equal to the arrangement pitch of the I/O circuits 2 for the first stage. It is provided facing the I/O circuit 2 of the semiconductor chip 21 of the above-mentioned other semiconductor integrated circuit. Furthermore, the above-mentioned plurality of I/O circuits 2 for the first stage of both semiconductor chips 20 and 21 are connected by inter-chip wires 25 , respectively.

Therefore, in the present embodiment, the arrangement of the first-level I/O circuits 2 of this semiconductor integrated circuit is set so that the arrangement pitches between the first-level I/O circuits 2 of both semiconductor chips 20 and 21 are equal. Therefore, the plurality of inter-chip wires 25 are almost equal in length to each other and are all relatively short, which improves the assembly property. As a result, for example, as shown in FIG. 23 , with respect to the arrangement pitch of a plurality of I/O circuits 2 for the first stage provided on one side of the semiconductor chip 21 of another semiconductor integrated circuit, the I/O circuit 1 for the second stage is provided. In the case of an I/O circuit provided on one side of the semiconductor chip 20 as this semiconductor integrated circuit, the isolation between a group of pads connected to each other is different in each group, and a plurality of pads connected to each group are connected to each other. The lengths of the inter-chip wires 26 are different from each other, resulting in different signal characteristics for each of the pads of the groups. However, in this embodiment, if the two-stage I/O circuit 1 is used, the area of the semiconductor integrated circuit can be effectively reduced, and the arrangement pitch of the I/O circuits of the other semiconductor integrated circuits to be connected can also be considered. Even if the area reduction effect is somewhat sacrificed, since the I/O circuit 2 for the first stage is used with a large arrangement pitch, it is possible to suppress the variation in signal characteristics between the pads of each group by the equal-length and short inter-chip wiring 25, Furthermore, high-speed interface characteristics can be obtained, which is particularly effective in a DDR (Double-Data-Rate) high-speed DRAM interface, for example.

(sixth embodiment)

Further, a sixth embodiment of the present invention will be described.

In this embodiment, the number of stages is different between the I/O circuit for the first stage and the I/O circuit for the second stage, and between the I/O circuit for the second stage and the I/O circuit for the third stage. Between the I/O circuits, have the same electrical characteristics as their I/O functions. The following describes the I/O circuit for level 1 and the I/O circuit for level 2 as examples.

FIG. 27 shows a circuit diagram of an I/O circuit for level 1 or level 2. In the figure, 35 is a pad provided above the I/O circuit, 36 is an internal signal input terminal for inputting an internal signal from the internal circuit 4 shown in FIG. 1 , and 37 is a terminal for outputting an internal signal to the internal circuit 4 above. Internal signal output terminal. The internal signal input to the internal signal input terminal 36 passes through the pre-buffer circuit 31 and the output transistor 32 , and then passes through the ESD protection transistor 33 to the pad 35 and is output from the pad 35 to the outside. In addition, a signal input from the outside to the pad 35 is transmitted to the internal signal output terminal 37 via the input circuit 34 , and output to the internal circuit 4 from the internal signal output terminal 37 .

The above-mentioned pre-buffer circuit 31 is constituted by: a first P-type transistor 38 having a gate width W=Wppb1 and a gate length L=Lppb1 and an N-type transistor 39 having a gate width W=Wnpb1 and a gate length L=Lnpb1. Inverting circuit IV1, the second inverter composed of P-type transistor 40 with gate width W=Wppb2 and gate length L=Lppb2 and N-type transistor 41 with gate width W=Wnpb2 and gate length L=Lnpb2 The circuit IV2 is connected in parallel to the above-mentioned internal signal input terminal 36 .

In addition, the above-mentioned output transistor 32 is composed of a P-type transistor 42 receiving the output signal of the above-mentioned first inverter circuit IV1 at the gate terminal and having a gate width W=Wpout and a gate length L=Lpout, and a P-type transistor 42 receiving the above-mentioned second inverter circuit IV at the gate terminal. The output signal of the phase circuit IV2 is composed of a third inverter circuit IV3 composed of an N-type transistor 43 having a gate width W=Wnout and a gate length L=Lnout.

Furthermore, the above-mentioned ESD protection transistor 33 is constituted as: a P-type transistor 44 whose gate terminal is always loaded with power supply voltage and gate width W=Wpesd gate length L=Lpesd, and a gate terminal grounded and gate width W=Wnesd gate N-type transistor 45 with length L=Lnesd is connected in series between power supply and ground.

In addition, the above-mentioned input circuit 34 is constituted by a P-type transistor 46 having a gate width W=Wpi1 and a gate length L=Lpi1 and an N-type transistor 47 having a gate width W=Wni1 and a gate length L=Lni1. The 4th inverter circuit IV4, and the 5th that the P-type transistor 48 of gate width W=Wpi2 and gate length L=Lpi2 and the N-type transistor 49 of gate width W=Wni2 and gate length L=Lni2 constitute The inverter circuit IV5 is connected in series.

The two transistors 42 and 43 of the output transistor 32 and the two transistors 44 and 45 of the ESD protection transistor 33 are transistors whose respective drains are directly connected to the pad 35 .

28 and 29 show layout configurations of the first-level I/O circuit 2 and the second-level I/O circuit 1 for realizing the I/O circuit shown in FIG. 27 described above.

FIG. 28 shows the layout structure of the I/O circuit 1 for the second stage, and FIG. 29 shows the layout structure of the I/O circuit 2 for the first stage. In the figure, in I/O circuit 2 for level 1, width W=W1, height H=H1, in I/O circuit 1 for level 2, width W=W2 (W2<W1), height H=H2 (H2> H1). For example, when W1=2·W2, H1=H2/2.

In the above-mentioned I/O circuits 1 and 2 for the second stage and the first stage, the upper side in the figure is the internal circuit 4 side in FIG. 1 , and the lower side in the figure is the outer end side of the semiconductor integrated circuit 5 . In each I/O circuit 1, 2, each N-type transistor part 32b, 33b of the output transistor 32 and the ESD protection transistor 33 is formed on the lower side in the figure, and each P-type transistor part 32a, 33a is formed on the upper side in the figure. Furthermore, a pre-buffer unit 31 and an input circuit 34 are formed on the upper side in the figure.

Comparing the I/O circuits 1 and 2 for 2-stage and 1-stage shown in FIG. 28 and FIG. 29 , the gate widths W of the P-type transistors 42 constituting a part of the output transistor 32 are unified to W=2Wpout, and The gate widths W of the P-type transistors 44 constituting a part of the ESD protection transistor 33 are also unified to W=4Wpesd (=Wpout). Therefore, these P-type transistors 42, 44 (that is, the P-type transistors whose drains are directly connected to the pad 35), their total gate widths are unified to equal widths between the first and the second I/O circuits 1, 2 ( 2Wpout+4Wpesd).

Similarly, comparing the first and second I/O circuits 1 and 2, the gate widths W of the N-type transistors 43 constituting a part of the output transistor 32 are unified to W=2Wnout, and the N-type transistors constituting a part of the ESD protection transistor 33 The gate widths W of the type transistors 45 are also unified to W=6Wnesd. Therefore, these N-type transistors 43, 45 (that is, the N-type transistors whose drains are directly connected to the pad 35), their total gate widths are unified into equal widths between the first and the second I/O circuits 1, 2 ( 2Wnout+6Wnesd).

As a result, in all the P-type and N-type transistors 42, 43, 44, and 45 whose drains are directly connected to the pad 35, the total gate widths between the first and second I/O circuits 1 and 2 are unified to be equal. The width of (2Wpout+4Wpesd+2Wnout+6Wnesd).

Furthermore, in the I/O circuit 1 for two stages shown in FIG. 28, the P-type transistors 42 and 44 whose drains are directly connected to the pad 35 are, as a whole, formed so that 6 transistors are provided at predetermined intervals in one diffusion region. One multi-finger structure MFp with root gate electrodes (two for the P-type transistor 42 and four for the P-type transistor 44), and the N-type transistors 43 and 45 whose drains are directly connected to the pad 35, as a whole, One multifinger structure MFn is formed in which eight gate electrodes (two for the N-type transistor 43 and six for the N-type transistor 45 ) are provided at predetermined intervals in one diffusion region.

In addition, in the first-stage I/O circuit 2 of FIG. 29 , the P-type transistors 42 and 44 whose drains are directly connected to the pad 35 as a whole form two multi-finger structures MFp1 and MFp2 in parallel in the width W1 direction. The multi-finger structures MFp1 and MFp2 are structures in which three gate electrodes (one for the P-type transistor 42 and two for the P-type transistor 44) are provided at predetermined intervals in one diffusion region, and the drain The N-type transistors 43 and 45 whose poles are directly connected to the pad 35, as a whole, form two multi-finger structures MFn1 and MFn2 juxtaposed in the width W1 direction. Four gate electrodes (one for the N-type transistor 43 and three for the N-type transistor 45 ) are provided at intervals.

In this way, among the three multi-finger structures MFp, MFp1, and MFp2 forming P-type transistors in the I/O circuits 1 and 2 for the first and second stages, the gate widths W thereof are all uniformly set by Wpout (=Wpesd). is equal. Similarly, in the three multi-finger structures MFn, MFn1, and MFn2 forming N-type transistors, the gate widths W thereof are collectively set to be equal by Wnout (=Wnesd).

28 and FIG. 29, it can be seen that between the I/O circuits 1 and 2 for the first stage and the second stage, the P-type transistors 42 that realize the same function as the P-type transistor of the output transistor 32 are mutually connected. The gate length L=Lpout and the width W=Wpout are set to be equal, and the N-type transistor 43 that realizes the same function as the N-type transistor of the output transistor 32 is also set to have the same gate length. L=Lnout and equal width W=Wnout.

28 and FIG. 29, it can be seen that the P-type transistors 44 that realize the same function as the P-type transistors of the ESD protection transistor 33 between the first-level and second-level I/O circuits 1 and 2, Be set to equal gate length L=Lpesd and equal width W=Wpesd, and realize the N-type transistor 45 of the same function as the N-type transistor of ESD protection transistor 33, also be set to equal gate. Pole length L=Lnesd and equal width W=Wnesd.

Furthermore, in the above-mentioned pre-buffer 31 and the input circuit 34, the transistors that realize the same function between the first and second I/O circuits 1 and 2 are set to have the same gate length and the same gate width as described below. . Specifically, in the pre-buffer 31 between the first-stage and second-stage I/O circuits 1 and 2, the P-type transistors 38 are set to have the same gate length L=Lppb1 and the same gate width Wppb1. , N-type transistors 39 are set to equal gate length L=Lnpb1 and equal gate width Wnpb1, and P-type transistors 40 are set to equal gate length L=Lppb2 and equal gate width Wppb2, N Type transistors 41 are set to have the same gate length L=Lnpb2 and the same gate width Wnpb2. Similarly, in the input circuit 34 between the I/O circuits 1 and 2 for the first and second stages, the P-type transistors 46 are set to have the same gate length L=Lpi1 and the same gate width Wpi1. Transistors 47 are set to equal gate length L=Lni1 and equal gate width Wni1, P-type transistors 48 are set to equal gate length L=Lpi2 and equal gate width Wpi2, N-type transistor 49 The gate length L=Lni2 and the gate width Wni2 are equal to each other.

In addition, in the I/O circuit 1 for two stages of FIG. 28 , the distance Dp from the well boundary between the P-type transistor and the N-type transistor to the diffusion region of the multi-finger structure MFp of the P-type transistor is set to Dp=WPD , and the distance Dn from the well boundary to the diffusion region of the multi-finger structure MFn of the N-type transistor is set as Dn=WND. In contrast, in the first-stage I/O circuit 2 of FIG. 29 , the distance Dp from the well boundary between the P-type transistor and the N-type transistor to the respective diffusion regions of the multi-finger structures MFp1 and MFp2 of the P-type transistor is set by It is assumed that DP=WPD, and the distance Dn from the well boundary to the diffusion regions of the multi-finger structures MFn1 and MFn2 of N-type transistors is Dn=WND.

Therefore, in the present embodiment, when these I/O circuits are mixed and mounted on one semiconductor integrated circuit 5 between the I/O circuit 1 for the second stage and the I/O circuit 2 for the first stage, due to these Since the electrical characteristics of the I/O circuits are equal, it is possible to determine which I/O circuit is provided for the first level or the second level only by considering the chip area of the semiconductor integrated circuit 5 . Furthermore, even if there is inconvenience that a specific signal terminal cannot be connected to, for example, a first-stage I/O circuit when the electrical characteristics are different between I/O circuits with different numbers of stages, in this embodiment, there is no need to Replace the arrangement position of the specific signal terminal with another signal terminal that can be connected to the first-level I/O circuit.

Claims (27)

1. A semiconductor integrated circuit, comprising: an internal circuit; and arranged outside the above-mentioned internal circuit, the signal of the above-mentioned internal circuit is output to the outside or the signal of the outside is input into the above-mentioned internal circuit, and a solder Multiple I/O circuits of the disk, The plurality of I/O circuits are composed of at least two types of I/O circuits having different heights toward the internal circuit, such as an I/O circuit for n stages and an I/O circuit for m stages. The I/O circuit is configured such that the pads are arranged in n stages toward the internal circuit, where n is an integer greater than or equal to 1, and the I/O circuit for m stages is configured such that the pads face toward the internal circuit. The direction of is set to m levels, where m is an integer greater than n, The above-mentioned plurality of I/O circuits each have a power supply wiring extending in the direction in which the I/O circuits are arranged for the n-stage I/O circuit and the m-stage I/O circuit, and the I/O circuits for the n-stage The power wiring and the power wiring of the above-mentioned I/O circuit for class m are different in height from the outer end of the I/O circuit; The adjacent I/O circuits for the n-stage and the I/O circuits for the m-stage arranged in a row are separated by a predetermined distance. 2. The semiconductor integrated circuit according to claim 1, characterized in that: The I/O circuit for the n-stage and the I/O circuit for the m-stage are located at the ends of two sides forming the corners of the semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The number of power supply wires included in the n-stage I/O circuit and the number of power supply wires included in the m-stage I/O circuit are different from each other. 4. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit have different wiring widths. 5. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit are formed on different wiring layers. 6. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The number of wiring layers formed between the power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit is different from each other. 7. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The above-mentioned semiconductor integrated circuit is a rectangle with four sides; Install the same type of I/O circuits for n-level or m-level on the two sides of one of the two sets of two sides facing each other; One of the two sides of the other set is provided with an I/O circuit having a different number of stages from the I/O circuits for n-stage or m-stage provided on the two sides of the above-mentioned one set. 8. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: On one side of a semiconductor integrated circuit, a plurality of n-level I/O circuits are arranged in an array; The arrangement pitch of the plurality of I/O circuits for n stages arranged on one side is set in consideration of the arrangement pitch of the plurality of I/O circuits arranged on one side of another semiconductor integrated circuit. 9. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: A plurality of the above-mentioned I/O circuits for the n-level and a plurality of the above-mentioned I/O circuits for the m-level are arranged in an array, In the whole of the plurality of n-level and m-level I/O circuits arranged in a row, the number of pads provided in the direction of the internal circuit is multiple, and the number of pads provided in the above-mentioned plurality of n-level I/O circuits The plurality of pads are arranged in a zigzag manner, and the plurality of pads provided in the plurality of I/O circuits for m-levels are also arranged in a zigzag manner, offset from each other. 10. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The I/O circuits for the n-stage and the I/O circuits for the m-stage have different widths in the arrangement direction of the I/O circuits. 11. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, the total gate widths of the transistors whose drains are directly connected to the pads are equal. 12. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, Transistors that perform the same function have equal gate lengths. 13. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, Transistors that perform the same function have equal gate widths. 14. The semiconductor integrated circuit according to claim 1 or 2, characterized in that: The width of the arrangement direction of the I/O circuits for the n-level is larger than the width of the arrangement direction of the I/O circuits for the m-level; The height of the n-stage I/O circuit toward the internal circuit is lower than the height of the m-stage I/O circuit toward the internal circuit. 15. A semiconductor integrated circuit comprising: an internal circuit; and arranged outside the internal circuit, outputting a signal from the internal circuit to the outside or inputting an external signal into the internal circuit, and having a soldering circuit on the top. Multiple I/O circuits of the disk, The plurality of I/O circuits are composed of at least two types of I/O circuits having different heights toward the internal circuit, such as an I/O circuit for n stages and an I/O circuit for m stages. The I/O circuit is configured such that the pads are arranged in n stages toward the internal circuit, where n is an integer greater than or equal to 1, and the I/O circuit for m stages is configured such that the pads face toward the internal circuit. The direction of is set to m levels, where m is an integer greater than n, The above-mentioned plurality of I/O circuits each have a power supply wiring extending in the direction in which the I/O circuits are arranged for the n-stage I/O circuit and the m-stage I/O circuit, and the I/O circuits for the n-stage The power wiring and the power wiring of the above-mentioned I/O circuit for class m are different in height from the outer end of the I/O circuit; A protective circuit for electrostatic discharge protection is provided between the adjacent n-stage I/O circuits and the m-stage I/O circuits arranged side by side. 16. The semiconductor integrated circuit according to claim 15, characterized in that: The number of power supply wires included in the n-stage I/O circuit and the number of power supply wires included in the m-stage I/O circuit are different from each other. 17. The semiconductor integrated circuit according to claim 15, characterized in that: The power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit have different wiring widths. 18. The semiconductor integrated circuit according to claim 15, characterized in that: The power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit are formed on different wiring layers. 19. The semiconductor integrated circuit according to claim 15, characterized in that: The number of wiring layers formed between the power supply wiring of the n-stage I/O circuit and the power supply wiring of the m-stage I/O circuit is different from each other. 20. The semiconductor integrated circuit according to claim 15, characterized in that: The above-mentioned semiconductor integrated circuit is a rectangle with four sides; Install the same type of I/O circuits for n-level or m-level on the two sides of one of the two sets of two sides facing each other; One of the two sides of the other set is provided with an I/O circuit having a different number of stages from the I/O circuits for n-stage or m-stage provided on the two sides of the above-mentioned one set. 21. The semiconductor integrated circuit according to claim 15, characterized in that: On one side of a semiconductor integrated circuit, a plurality of n-level I/O circuits are arranged in an array; The arrangement pitch of the plurality of I/O circuits for n stages arranged on one side is set in consideration of the arrangement pitch of the plurality of I/O circuits arranged on one side of another semiconductor integrated circuit. 22. The semiconductor integrated circuit according to claim 15, characterized in that: A plurality of the above-mentioned I/O circuits for the n-level and a plurality of the above-mentioned I/O circuits for the m-level are arranged in an array, In the whole of the plurality of n-level and m-level I/O circuits arranged in a row, the number of pads provided in the direction of the internal circuit is multiple, and the number of pads provided in the above-mentioned plurality of n-level I/O circuits The plurality of pads are arranged in a zigzag manner, and the plurality of pads provided in the plurality of I/O circuits for m-levels are also arranged in a zigzag manner, offset from each other. 23. The semiconductor integrated circuit according to claim 15, characterized in that: The I/O circuits for the n-stage and the I/O circuits for the m-stage have different widths in the arrangement direction of the I/O circuits. 24. The semiconductor integrated circuit according to claim 15, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, the total gate widths of the transistors whose drains are directly connected to the pads are equal. 25. The semiconductor integrated circuit according to claim 15, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, Transistors that perform the same function have equal gate lengths. 26. The semiconductor integrated circuit according to claim 15, characterized in that: Between the I/O circuit for the n-stage and the I/O circuit for the m-stage, Transistors that perform the same function have equal gate widths. 27. The semiconductor integrated circuit according to claim 15, wherein: The width of the arrangement direction of the I/O circuits for the n-level is larger than the width of the arrangement direction of the I/O circuits for the m-level; The height of the n-stage I/O circuit toward the internal circuit is lower than the height of the m-stage I/O circuit toward the internal circuit.

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