CN102157371B - Method for producing monocrystalline silicon nanometer structure - Google Patents

Abstract

The invention discloses a method for making a single crystal silicon nanostructure. Firstly, according to the pattern of the single crystal silicon nanostructure, photolithography is carried out on a silicon substrate to define a mask pattern with a micron-level line width; and then ion implantation is performed on the mask pattern A heavily doped region is formed outside; followed by high temperature annealing to diffuse the implanted ions into the silicon material under the mask pattern to form a moderately doped region, reducing the line width of the low doping concentration region under the mask pattern to nanometers level; finally, the silicon in the moderately doped region is selectively etched away with HNA solution to obtain a single crystal silicon nanostructure with low doping concentration. The method of the present invention not only has the advantages of good compatibility between MEMS technology and IC technology, convenient operation, low cost, and convenience for large-scale production, but also has better line width controllability.

Description

A method of making single crystal silicon nanostructure

technical field

The present invention relates to the field of micro-nano electromechanical systems, in particular to a method for manufacturing single-crystal silicon nanostructures, which is a simple method for producing single-crystal silicon nanostructures in large quantities at low cost by using traditional MEMS manufacturing techniques, so that The size of the fabricated single crystal silicon nanostructure is basically controllable.

Background technique

As an important part of nano-silicon devices, single crystal silicon nanostructures have many excellent properties in terms of quantum confinement and surface activity, so they have a wide range of applications. For example, combined with MOSFET to detect biological macromolecules such as protein and DNA; as the basic structure and device for photonic crystal research or nano-spin device research, etc.

The traditional fabrication method of silicon nanowires (SiNWs) mainly adopts nanofabrication process. The nanofabrication process is a bottom-up "assembly" of nanowires, mainly including laser ablation (Laserablation), porous alumina template method and so on. The laser ablation method mainly uses the Vapor-liquid-solid method (Vapor-liquid-solid method, VLS). When the saturated gaseous silicon continuously diffuses into the alloy droplets of silicon and metal catalyst, the solid silicon will continue to flow out of the liquid. The droplets are precipitated to grow nanowires at the liquid-solid interface. The porous alumina template method uses nanoporous aluminum as a template, and silane gas synthesizes silicon in nanopores under the action of catalysts such as gold (Au) and silver (Ag), and finally removes porous aluminum to obtain nanowires. Although these nanofabrication processes have the advantages of low cost and uniform size, they are harsh, difficult to operate, poor in compatibility, and easily contaminated by catalysts.

In recent years, with the advancement of lithography technology, scanning probe lithography (Scanning Probe Lithograph, SPL) and electron beam lithography (EBL) are also increasingly used in the fabrication of single crystal silicon nanostructures. However, these methods are time-consuming and expensive, and are difficult to be used for large-scale production of single-crystal silicon nanostructures.

Compared with the above methods, the method of preparing nanostructures based on micromachining technology has the advantages of being compatible with IC technology, low cost, and convenient for large-scale production. The reported methods are mainly Sidewall Masking Technique and Photoresist Ashing Technique. Both of these two methods first use deposited materials or silicided photoresist to form sidewalls, and then use this as a mask to etch to obtain nanowires, but the controllability of the line width is not high.

It can be seen that in related technical fields, a large-scale, economical and effective method for manufacturing single crystal silicon nanostructures is needed, and micromachining technology is a hot spot of concern.

Contents of the invention

The object of the present invention is to provide a low-cost, large-scale, and controllable line width method for manufacturing single-crystal silicon nanostructures based on micromachining technology. Further, the fabricated single crystal silicon nanostructures are used to mass produce single crystal silicon nanostructure sensors, nanometer quantum devices and the like with predetermined line widths.

Technical scheme of the present invention is as follows:

A method for making a single crystal silicon nanostructure, comprising the steps of:

1) Select a silicon substrate with a low doping concentration below 10 ¹² cm ^-3 ;

2) According to the pattern of the monocrystalline silicon nanostructure to be fabricated, photolithography is performed on the silicon substrate to define a mask pattern with a micron-scale line width;

3) Ion implantation is performed to form a heavily doped region outside the mask pattern with a micron-scale line width, and the doping concentration is greater than 10 ¹⁹ cm ^-3 ;

4) Perform high-temperature annealing on the silicon substrate, and the implanted ions will diffuse into the silicon material under the mask pattern to form a moderately doped region with a doping concentration of 10 ¹⁷ ~ 10 ¹⁹ cm ^-3 , making the mask pattern The line width of the low doping concentration region is reduced to the nanometer level;

5) Using HNA solution to selectively etch away the silicon in the moderately doped region to obtain a single crystal silicon nanostructure with low doping concentration.

Further, before the above step 2), one layer of _SiO2 layer can be formed on the silicon substrate by thermal oxidation method, and this _SiO2 layer will be used as the ion implantation protective layer for subsequent implantation; in step 5) selectively use HNA solution Before etching silicon, first use buffered hydrofluoric acid (BHF) solution (HF:NH ₄ F = 1:4 (volume ratio)) to etch away the SiO ₂ layer and the natural oxide layer that may be formed during annealing.

The above-mentioned step 1) generally selects an ordinary silicon substrate or an SOI silicon substrate as the substrate, and the doping concentration of the silicon substrate is about 1011 cm ⁻³ .

The line width of the above step 2) mask pattern is less than 2 μm, preferably less than 1 μm.

The type of ion implantation in the above step 3) is generally equivalent to the type of substrate used, that is, group III ions are implanted into p-type substrates, and group V ions are implanted into n-type substrates. The ion implantation concentration should be as large as possible to ensure that the doping concentration of the heavily doped region formed after implantation is higher than 10 ¹⁹ cm ^-3 . If necessary, the photoresist should be baked prior to implantation to ensure that the photoresist does not crack during high-dose implants.

The above step 4) the annealing temperature is between 950°C and 1050°C. The annealing time is determined by the size of the mask pattern and the size of the required nanostructure. It can be theoretically estimated by combining the designed size and specific process parameters or using the simulation results of related software. , generally 3-10 hours. During annealing, the implanted ions will diffuse in all directions of the substrate, including lateral diffusion parallel to the substrate surface. Using the diffusion of implanted ions, some moderately doped regions are formed in the silicon substrate,

The HNA solution used in the above step 5) is preferably a solution of HNO ₃ :HF:HAc=3:1:8 (volume ratio). Since HNA solution etches silicon substrates with a doping concentration above 10 ¹⁷ cm ^-3 at about 1-2 μm/min, much faster than lightly doped silicon substrates, the etching selectivity ratio is about 160:1. Therefore, lightly doped single-crystal silicon nanostructures will remain after the selective removal of moderately doped regions using HNA solution. When HNA solution etches the silicon substrate, HNO ₃ will be reduced to HNO ₂ in the etching solution. As the HNA solution corrodes the silicon substrate, the concentration of HNO ₂ will increase. Higher concentration of _HNO2 will affect the selectivity of HNA solution. In this case, you can add an appropriate amount of oxidant (such as H ₂ O ₂ ) to oxidize HNO ₂ into HNO ₃ to eliminate the influence of HNO ₂ ; you can also add an appropriate amount of reducing agent NaN ₃ to remove HNO ₂ . In view of the fast corrosion rate of the HNA solution, and HNO ₂ that affects the selectivity will be generated during the corrosion process, the corrosion time of the HNA solution should not be too long. The specific time can be determined through preliminary experiments according to the line width of the nanostructure to be prepared.

The invention adopts the HNA selective etching technology to manufacture single crystal silicon nanostructures on the silicon substrate, which overcomes the problems of harsh conditions, difficult operation, poor compatibility and easy contamination by catalysts of the nano-processing technology, and scanning probe photolithography ( SPL) and electron beam lithography (EBL) techniques are time-consuming and costly. The method of the present invention not only has the advantages of the preparation method based on the traditional MEMS process, such as good compatibility, convenient operation, low cost, and convenient mass production, etc. Have better line width controllability.

The invention adopts simple and repeatable procedures, can manufacture highly integrated monocrystalline silicon nano-devices, and is not limited by the minimum size of lithography, can replace time-consuming and expensive electron beam lithography, and is difficult to control and has poor compatibility vapor-liquid-solid phase method. The single crystal silicon nanostructure produced by the method of the present invention can be applied to the preparation of various micro-nano electromechanical devices, for example, it can produce Bio-MEMS sensors for detecting biologically active molecules, and important devices for studying nano-spintronics.

Description of drawings

Fig. 1 (a)-(d) is the process flow schematic diagram of the embodiment of the present invention making monocrystalline silicon nanowire, wherein: (a) has shown the step of forming photoresist mask on silicon oxide buffer layer; (b) The step of high-concentration ion implantation is shown; (c) shows the step of annealing to form a moderately ion-doped region; (d) shows the step of HNA selectively etching silicon to form a nanostructure.

Fig. 2 is a scanning electron micrograph of two single crystal silicon nanostructures fabricated by the method of the present invention.

Detailed ways

The method for fabricating single-crystal silicon nanostructures by the HNA selective etching method will be further described in detail below with reference to the accompanying drawings.

As shown in Figure 1, a single crystal silicon nanostructure is produced according to the following steps:

1. Select ordinary silicon wafer or SOI silicon wafer as the substrate 1, and the doping concentration of the silicon substrate is about 10 ¹¹ cm ^-3 .

2. Form a layer of SiO ₂ layer 2 on the silicon substrate 1 by thermal oxidation, and the SiO ₂ layer will be used as a protective layer for ion implantation; then according to the layout design, photolithography defines a mask pattern with a micron-scale line width, A photoresist ion implantation mask 3 is formed, see FIG. 1( a ).

3. Perform ion implantation to form a heavily doped region 4 outside the mask pattern on the silicon substrate, see FIG. 1(b).

4. High-temperature annealing, the implanted ions will diffuse to all directions of the substrate 1 during high-temperature annealing, including lateral diffusion parallel to the substrate surface. Due to the diffusion of implanted ions, some ions will be formed on the silicon substrate 1. In the moderately doped region 5, the doping concentration is about 10 ¹⁷ to 10 ¹⁹ cm ^-3 , and the line width of the low doping concentration region under the mask pattern will also be reduced to the nanometer level, as shown in Figure 1(c). The annealing temperature is 1000° C., and the annealing time is more than 3 hours.

5. Corrode the SiO ₂ ion implantation protective layer 2 with buffered hydrofluoric acid (BHF) solution (HF:NH ₄ F=1:4 (volume ratio)), and then use HNA solution (HNO _{3 :} HF:HAc=3: 1:8) to selectively etch away the moderately doped region 5 to obtain a single crystal silicon nanostructure 6 with a low doping concentration on the silicon substrate, as shown in FIG. 1( d ).

The above method utilizes the HNA selective etching method to fabricate the single crystal silicon nanostructure, and the line width of the nanostructure can be adjusted through the layout design of the mask pattern and the annealing time.

Fig. 2 is the scanning electron micrograph of the monocrystalline silicon nanowire that utilizes the inventive method to make, and wherein Fig. 2 (a) layout design line width is 2 μ m, the line width of the nano wire that forms after HNA corrosion is about 1 μ m, Fig. 2 (b ) for the layout design line width of 0.6 μm, the line width of the nanowires formed after HNA etching is about 370 nm.

The method for fabricating single-crystal silicon nanostructures by selective etching of HNA in the present invention has been described above through specific implementation methods. Those skilled in the art should understand that the above description should not be considered as a limitation of the present invention. Within the scope of not departing from the spirit and essence of the present invention, certain deformation or modification can be made to the present invention, and the protection scope of the present invention depends on the appended claims.

Claims (9)

1. A method for making a monocrystalline silicon nanostructure, comprising the steps of: 1) Select a silicon substrate with a low doping concentration below 10 ¹² cm ^-3 ; 2) According to the pattern of single crystal silicon nanostructure, photolithography is performed on the silicon substrate to define the mask pattern of micron-scale line width; 3) Ion implantation is performed to form a heavily doped region outside the mask pattern with a micron-scale line width, and the doping concentration is greater than 10 ¹⁹ cm ^-3 ; 4) High-temperature annealing, the implanted ions diffuse into the silicon material under the mask pattern, forming a moderately doped region with a doping concentration of 10 ¹⁷ ~ 10 ¹⁹ cm ^-3 , so that the low doping concentration region under the mask pattern The line width is reduced to the nanometer level; 5) Using HNA solution to selectively etch away the silicon in the moderately doped region to obtain a single crystal silicon nanostructure with low doping concentration. 2. The method according to claim 1, characterized in that, step 1) selects a silicon substrate or an SOI silicon wafer as the substrate. 3. The method according to claim 1, wherein the line width of the mask pattern in step 2) is less than 2 μm. 4. method as claimed in claim 1, is characterized in that, before step 2) thermal oxidation is formed one deck _SiO earlier on silicon substrate before ion implantation protection layer; Before step 5) with HNA solution selective corrosion silicon , the SiO ₂ layer is first etched away with a buffered hydrofluoric acid solution. 5. The method according to claim 1, wherein step 3) bakes the photoresist ion implantation mask before the ion implantation. 6. method as claimed in claim 1 is characterized in that, the kind of step 3) ion implantation is suitable with the type of silicon substrate, implants group III ion for p-type substrate, and implants group V ion for n-type substrate . 7. The method according to claim 1, characterized in that the annealing time of step 4) is 3-10 hours. 8. The method according to claim 1, characterized in that the HNA solution used in step 5) is a solution of _HNO3 :HF:HAc=3:1:8 (volume ratio). 9. The method according to claim 1, characterized in that, in step 5) during the HNA solution corrosion process, an appropriate amount of oxidizing agent or reducing agent is added to remove HNO ₂ .

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