CN102156666B - Temperature optimizing method for resource scheduling of coarse reconfigurable array processor - Google Patents

Abstract

A temperature optimization method for resource scheduling of coarse-grained reconfigurable array processors in the field of computer application technology. The temperature optimization strategy is initialized when hardware resource scheduling is executed in the algorithm task compilation process; the initial resource scheduling scheme is selected and passed Computing task nodes perform initial scheduling of array resources constrained by data dependencies, and each computing task node is completed by an array unit of a reconfigurable hardware array processor; finally, the scheduling position of computing tasks is randomly reselected and re-solved by three passes The thermal equation obtains the predicted temperature value, based on which a more optimal resource scheduling scheme is selected to reduce the temperature distribution of the device during operation. When the number of optimizations or the set optimal temperature is reached, the optimization process is stopped and the current optimal scheme is selected as The final resource scheduling scheme.

Description

A temperature-optimized method for processor resource scheduling of coarse-grained reconfigurable arrays

technical field

The invention relates to a method in the field of computer application technology, in particular to a temperature optimization method for coarse-grained reconfigurable array processor resource scheduling.

Background technique

Reconfigurable computing systems were born to fill the gap between ASICs and microprocessors. Coarse-grained reconfigurable systems have gained more and more attention due to their good trade-off between system performance and functional flexibility. The applications of coarse-grained reconfigurable systems involve image compression, graphics and picture processing, data encryption and DSP conversion, and so on.

However, programming a reconfigurable computing system would be an extremely tedious and error-prone process because it requires programmers to have a good understanding of the target hardware, which limits the widespread acceptance and promotion of this technology. In response to this problem, researchers have proposed many different methods, such as using programming languages, high-level compilation methods, etc. to map application algorithms to hardware. These semi-automatic and automatic compilation tools can make it easier for programmers to map the hardware of the application algorithm, and also make the algorithm more portable. Semi-automatic tools such as Hartej et al. proposed a comprehensive software platform for the Morphosys system in 2000, which uses manual methods to generate configuration words for reconfigurable arrays (RCA) in a graphical interface. A fully automatic method, such as the XPP C compiler developed by Joao M.P. for the PACT-XPP hybrid reconfigurable processor system in 2006, uses pipeline vectorization and time domain segmentation methods to generate configuration words. During the compilation process of the compiler, the calculation tasks in the algorithm need to be completed by calling reconfigurable hardware resources.

After searching the existing technologies, it is found that the current main resource scheduling technologies only focus on the utilization rate of hardware and the efficiency of task execution. For example, the resource scheduling technology in the compiler proposed in "XPP-VC: A C Compiler with Time Domain Division on the PACT-XPP Platform" published by Joao M.P. in 2006 only focuses on the calculation of tasks after time domain division. The efficiency of the calculation and the number of PEs occupied, without considering the temperature effect of the task running on the device. However, with the development of chip performance, on-chip thermal problems become more and more serious. High temperatures both affect power consumption during device operation and degrade device stability. In order to minimize the negative effects of high temperature, different measures should be taken during chip design, manufacturing and software compilation. Many strategies have been used to solve this problem, such as dynamic thermal management technology (DTM) in microprocessors, and simultaneous multithreading technology (SMT) in multi-core processors. This technology takes the temperature factor into the resource scheduling technology for the first time. The purpose of temperature optimization in this paper is to avoid local hot spots on the chip by balancing the temperature distribution on the chip. It automatically completes the resource scheduling of the mapping task during the algorithm compilation process, which does not increase any hardware design costs.

Contents of the invention

Aiming at the above-mentioned deficiencies in the prior art, the present invention provides a temperature optimization method for resource scheduling of coarse-grained reconfigurable array processors, which alleviates this problem by predicting and balancing the temperature of hardware resources during execution in the compilation process . This reduces the risk of localized hotspots on the chip without adding any hardware cost. As a result of the optimization, the computing tasks represented by the intermediate representation of the algorithm can be completed by invoking hardware resources through a temperature-optimized scheduling scheme.

The present invention is achieved through the following technical solutions, and the present invention comprises the following steps:

The first step is to initialize the temperature optimization strategy when executing hardware resource scheduling in the algorithm task compilation process;

The temperature optimization strategy initialization refers to establishing a thermal model based on hardware physical parameters, equivalent to the heat conduction relationship between modules in the device through thermal conductance, and then reading the power consumption parameters of the device.

The physical parameters of the hardware model include: hardware layout parameters, chip thickness, thermal diffusivity, and specific heat coefficient.

The calculation method of the thermal conductance is: Where: t is the effective thickness of the module, A is the area of the module, and k is the thermal conductivity.

The second step is to select an initial resource scheduling scheme and perform initial scheduling of array resources constrained by data dependencies through computing task nodes. Each computing task node is completed by an array unit of a reconfigurable hardware array processor.

The computing task node solves the thermal model and predicts the temperature during hardware execution under the current resource scheduling scheme: G T = P, where: G represents the thermal conductivity matrix, T represents the temperature to be predicted, and P represents power consumption .

The third step is to randomly re-select the scheduling position of the computing task and obtain the predicted temperature value by re-solving the thermal equation three times. Based on this, a more optimized resource scheduling scheme is selected to reduce the temperature distribution of the device during operation. When the optimization times are reached Or the set optimization temperature stops the optimization process and selects the current optimal solution as the final resource scheduling solution.

The present invention is proposed through the following principle: when there are spare hardware resources in the array, the computing tasks with higher temperature can be migrated to the spare resources without changing the data correlation, or can be migrated to High reconfigurable units are executed. The optimal migration strategy is obtained by optimizing the search. When searching, search in the row direction of the two-dimensional array first. When the scheduling of a certain row is completed, the search in the direction of the array column is started. In the process of column search, the nodes in each row are translated in the array as a whole, and the relative positions of the task nodes in the row remain unchanged.

Compared with the existing thermal optimization technology, the present invention has the following advantages: 1) It can predict the device temperature during execution while scheduling resources, and select the best scheduling scheme according to the prediction result. 2) The temperature optimization process is automatically completed during resource scheduling without requiring additional hardware resources, thereby saving hardware design costs. 3) The temperature optimization process is statically completed by the compiler before hardware execution, without complex dynamic management strategies.

Description of drawings

Figure 1 Reconfigurable hardware array processor architecture.

Figure 2 is the flow of temperature optimization in the process of resource scheduling.

Figure 3 Example of a simplified thermal model of a device.

Figure 4 Example of array temperature distribution before and after optimization.

Detailed ways

The embodiments of the present invention are described in detail below. This embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present invention is not limited to the following implementation example.

Example

As shown in Figure 1, the reconfigurable array hardware resource mentioned in this embodiment is a two-dimensional array composed of isomorphic reconfigurable units, and data communication can be performed between array units in adjacent rows, while The array units within cannot perform data interaction.

This embodiment includes the following steps:

The first step is to initialize the temperature optimization strategy when executing hardware resource scheduling in the algorithm task compilation process;

The temperature optimization strategy initialization refers to establishing a thermal model based on hardware physical parameters, equivalent to the heat conduction relationship between modules in the device through thermal conductance, and then reading the power consumption parameters of the device.

The physical parameters of the hardware model include: hardware layout parameters, chip thickness, thermal diffusivity, and specific heat coefficient.

其中：t是模块的有效厚度，A是模块的面积，k是热电导系数。The calculation method of the thermal conductance is:

Where: t is the effective thickness of the module, A is the area of the module, and k is the thermal conductivity.

The second step is to select an initial resource scheduling scheme and perform initial scheduling of array resources constrained by data dependencies through computing task nodes. Each computing task node is completed by an array unit of a reconfigurable hardware array processor.

The computing task node solves the thermal model and predicts the temperature during hardware execution under the current resource scheduling scheme: G T = P, where: G represents the thermal conductivity matrix, T represents the temperature to be predicted, and P represents power consumption .

The third step is to randomly re-select the scheduling position of the computing task and obtain the predicted temperature value by re-solving the thermal equation three times. Based on this, a more optimized resource scheduling scheme is selected to reduce the temperature distribution of the device during operation. When the optimization times are reached Or the set optimization temperature stops the optimization process and selects the current optimal solution as the final resource scheduling solution.

As shown in Figure 2, temperature optimization techniques are based on modeling the device. The optimization process includes reading the device model parameters and the power consumption parameters of each RC operation of the device, and then selecting the best scheduling schemes based on the thermal model. The selection process is an iterative search process. During the search process, it is necessary to continuously adjust the position of the task nodes on the array RC to obtain the optimal resource scheduling scheme for computing tasks.

As shown in Figure 3, the reconfigurable array in the processor is modeled using a simplified thermal model. The model considers the heat conduction process between each RC in the array, and also considers the heat conduction between the device layer and the heat conduction layer. The thermal model uses the horizontal thermal resistance to equate the heat conduction relationship between RCs, and uses the longitudinal thermal resistance to equate the heat conduction relationship between the device layer and the heat conduction layer.

As shown in Figure 4, the change in the temperature distribution on the device after using the temperature optimization technique in an application is compared. After optimization, the maximum temperature of the device is reduced by nearly 7°C. At the same time, the temperature distribution range during device operation is also reduced by about 10°C. Optimization technology can improve the temperature distribution of the device during operation, thereby effectively alleviating the damage of the thermal effect on the device.

The input data required by this method include a data flow graph (DFG) representing a computing task, a physical parameter file required for building a thermal model, and a power consumption parameter file of a reconfigurable array unit.

The mapped task DFG is transformed from the algorithm C source code. The DFG needs to be optimized and divided into subgraphs suitable for the computing scale of the hardware array before it can be used as input data for resource scheduling.

1. The temperature optimization strategy is implemented when the compiler starts resource scheduling.

2. Read the thermal model parameters of the array hardware into the program, start to build a simplified thermal model for the device, and prepare for the next step of temperature analysis. In the thermal model, the heat conduction relationship between the modules in the device is equivalent to the thermal conductance. The calculation method of the thermal conductance is:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; k</span>}\frac{\mathrm{<span\; class="notranslate">\; t</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}$

where t is the effective thickness of the module, A is the area of the module, and k is the thermal conductivity. When modeling, the device can be divided into two layers: one layer represents the device layer, and the other layer represents the thermal conductivity layer, see Figure 3. You can also choose more complex modeling methods according to the specific implementation of the device.

3. Then read the power consumption parameters when the array unit is executing, and provide the necessary power consumption information for solving the heat equation.

4. Find an initial resource scheduling scheme that satisfies both hardware connectivity constraints and task node data dependencies, and schedules the computing task nodes in the task DFG to a certain array unit position.

5. Start an iterative random optimization search for the initial scheduling plan. During the search process, the data correlation between task nodes should be ensured, and at the same time, by solving the heat equation

G·T=P

Predict the temperature distribution for the current schedule. When searching, the search is performed in the row direction of the array first, and when the array units on a row of the array are dispatched or the task cannot be scheduled on the row, the task scheduling of the row is stopped. When the scheduling of a certain row is completed, the search in the direction of the array column is started. In the process of column search, the nodes in each row are translated in the array as a whole, and the relative positions of the task nodes in the row remain unchanged.

6. When the set number of optimization times or optimization temperature is reached, the optimization process is terminated, and the current optimal solution is selected as the final resource scheduling solution.

Claims (5)

1. A temperature optimization method for coarse-grained reconfigurable array processor resource scheduling, characterized in that, comprising the following steps: The first step is to initialize the temperature optimization strategy when executing hardware resource scheduling in the algorithm task compilation process; The second step is to select an initial resource scheduling scheme and perform initial scheduling of array resources constrained by data dependencies through computing task nodes. Each computing task node is completed by an array unit of a reconfigurable hardware array processor; The third step is to randomly re-select the scheduling position of the computing task and obtain the predicted temperature value by re-solving the thermal equation. Based on this, a more optimized resource scheduling scheme is selected to reduce the temperature distribution of the device during operation. If the optimization temperature is set, the optimization process will be stopped and the current optimal plan will be selected as the final resource scheduling plan; different scheduling plans will be selected based on the thermal model. The selection process is an iterative search process; When the array units on a certain row of the array are scheduled or cannot continue to schedule tasks on this row, stop the task scheduling of this row; when the scheduling of a certain row is completed, start to search in the direction of the array column , during the column search process, the nodes in each row are translated in the array as a whole, and the relative positions of the task nodes in the row remain unchanged. 2. The temperature optimization method for coarse-grained reconfigurable array processor resource scheduling according to claim 1, characterized in that, the initialization of the temperature optimization strategy refers to: according to the physical parameters of the hardware, through thermal conductance etc. Establish a thermal model based on the heat conduction relationship between modules in the effective device, and then read the device power consumption parameters. 3. The temperature optimization method for coarse-grained reconfigurable array processor resource scheduling according to claim 2, wherein the physical parameters of the hardware model include: hardware layout parameters, chip thickness, thermal diffusivity, Specific heat coefficient. 4. The temperature optimization method for resource scheduling of a coarse-grained reconfigurable array processor according to claim 2, wherein the calculation method of the thermal conductance is:

Where: t is the effective thickness of the module, A is the area of the module, and k is the thermal conductivity. 5. The temperature optimization method for resource scheduling of coarse-grained reconfigurable array processors according to claim 1, wherein the computing task node solves the thermal model and predicts the hardware temperature under the current resource scheduling scheme. Execution temperature: G·T=P, where: G represents the thermal conductance matrix, T represents the temperature to be predicted, and P represents power consumption.

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