CN102148920B - Synchronous signal limiting device and synchronous signal limiting method - Google Patents

Abstract

The embodiment of the invention provides a synchronous signal amplitude limiting device and a synchronous signal amplitude limiting method, wherein the synchronous signal amplitude limiting device comprises a filtering module, an amplitude limiting level detector and a comparator. The filter module processes a video input to generate a filter output and includes a first filter circuit configured to receive the video input and perform an infinite impulse response filtering on the video input. The slice level detector is coupled to the filter module for receiving the filter output and determining a slice level corresponding to the sync signal component according to the filter output. The comparator is coupled to the first filter and the filtering module, and is used for receiving the filtering output and the amplitude limiting level and comparing the amplitude limiting level with the filtering output to generate a synchronous signal amplitude limiting output.

Description

Synchronous signal limiting device and synchronous signal limiting method

technical field

The present invention relates to signal clipping processing, in particular to a synchronous signal clipping device and method including using the output of infinite impulse response (Infinite Impulse Response, IIR) filter processing to determine the clipping level and generate the clipping output of the synchronous signal.

Background technique

Generally speaking, the synchronization processing of analog TV signals mainly relies on horizontal sync signal (horizontal sync, HSYNC) and vertical sync signal (vertical sync, VSYNC), in which the signal transmission of each scanning line will contain a horizontal sync signal, however, vertical sync Signals are only generated once per field. Please refer to FIG. 1 . FIG. 1 is a schematic waveform diagram of an existing composite video signal. As shown in the figure, the horizontal sync level (sync tip) is the lowest voltage level in the composite video signal, and has a voltage difference of 300mV from the reference black level. Generally speaking, analog TV translation Encoders often use sync slicing technology to determine the starting position of the horizontal sync signal component of the signal transmission of each scanning line in the composite video signal. For example, it will first find out the reference black level and horizontal Synchronization level, then, use the intermediate level of the reference black level and the horizontal synchronization level as the clipping level to perform clipping processing on the composite video signal so as to separate the horizontal synchronization signal component from the composite video signal for subsequent A circuit (such as a phase-locked loop) generates a horizontal synchronous clock.

However, the received analog TV signal often has some interference, such as white noise (white noise) and co-channel interference (co-channel interference), etc. Therefore, the actual composite video signal does not have the ideal waveform shown in Figure 1 , but will be disturbed and cause waveform distortion. Therefore, how to determine the appropriate clipping level to obtain an accurate clipping output of the synchronous signal has become an important issue in the design of the synchronous signal clipping.

Contents of the invention

Therefore, one object of the present invention is to provide a synchronization signal clipping device and method including utilizing the output of infinite impulse response filtering to determine the clipping level and generate a clipped output of the sync signal, so as to solve the above-mentioned problems.

According to an embodiment of the present invention, it discloses a synchronization signal limiting device. The synchronous signal limiting device includes a filtering module, a limiting level detector and a comparator. The filter module processes the video input to generate a filter output, and includes a first filter circuit for receiving the video input and performing infinite impulse response filter processing on the video input. The clipping level detector is coupled to the filtering module for receiving the filtering output, and determines the clipping level corresponding to the synchronous signal component according to the filtering output. The comparator is coupled to the clipping level detector and the filtering module to receive the filtering output and the clipping level, and compare the clipping level and the filtering output to generate a synchronous signal clipping output .

According to an embodiment of the present invention, it further discloses a synchronization signal limiting method. The synchronous signal clipping method includes: processing a video input to generate a filter output, which includes performing infinite impulse response filter processing on the video input; determining a clipping level corresponding to a synchronous signal component according to the filter output; and comparing the The clipping level is combined with this filtered output to produce a sync signal clipped output.

The invention can determine the appropriate clipping level to obtain an accurate clipping output of the synchronous signal.

Description of drawings

FIG. 1 is a schematic diagram of a waveform of an existing composite video signal.

FIG. 2 is a schematic diagram of a first embodiment of a synchronization signal limiting device of the present invention.

FIG. 3 is a schematic diagram of an infinite impulse response filtering process performed by the first filtering circuit.

Fig. 4 is a flow chart of the first embodiment of the synchronization signal clipping method of the present invention.

FIG. 5 is a schematic diagram of a second embodiment of a synchronization signal limiting device of the present invention.

FIG. 6 is a flow chart of the second embodiment of the synchronization signal clipping method of the present invention.

Detailed ways

Certain terms are used in the claims and description to refer to particular elements. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same element. The claims and description of the present invention do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to". Otherwise, the term "coupled" includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a first embodiment of a synchronization signal limiting device of the present invention. The synchronous signal clipping device 200 includes (but not limited to) a filtering module 202 , a clipping level detector 204 and a comparator 206 . The filter module 202 is used to process the video input (such as the sampling data of the composite video signal) S_IN to generate the filter output S_OUT. In this embodiment, the filter module 202 includes at least a first filter circuit 208, which receives the video input S_IN, and The video input S_IN is filtered by Infinite Impulse Response (IIR) to generate the filtered output S_OUT. In other words, the first filter circuit 208 can be realized by using an infinite impulse response filter architecture. The slicer level detector 204 is coupled to the filter module 202, and is used for receiving the filter output S_OUT from the filter module 202, and determines the slicer level (slicer level) SL corresponding to the synchronous signal component according to the filter output S_OUT, at In this embodiment, the synchronous signal component is a horizontal synchronous signal component, however, this is only for illustrative purposes and is not a limitation of the present invention. In addition, the comparator 206 is coupled to the slice level detector 204 and the filter module 202 to receive the filter output S_OUT and the slice level SL, and compare the slice level SL and the filter output S_OUT to generate a synchronous signal limit. Amplitude output Sliced_SYNC. Since the main technical feature of the present invention lies in the filter module 202 instead of the comparator 206 and the limit level detector 204, that is, the filter module 202 is used to generate the filter output S_OUT for subsequent circuits (including the comparator 206 and the limiter) Level detector 204) to use, moreover, in the application of the present invention, comparator 206 and clipping level detector 204 can adopt any existing circuit structure to operate, so for the sake of brevity of description, The descriptions of the comparator 206 and the slice level detector 204 are omitted here. The circuit and operation of the filter module 202 will be described in detail below.

As mentioned above, the first filtering circuit 208 in the filtering module 202 is used to perform infinite impulse response filtering processing, therefore, in this embodiment, the first filtering circuit 208 will process the input data in a recursive manner (that is, S_IN ), in other words, the filtered output S_OUT generated by the first filtering circuit 208 will be combined with the currently received input data (such as the current data of the composite video signal) and the previously received input data (such as the previous data of the composite video signal) data), in this embodiment, the first filter circuit 208 uses a weighted average (weighted average) operation to realize the infinite impulse response filtering process, however, this is only used as an example for illustration, rather than a limitation of the present invention, that is , without departing from the inventive spirit of the present invention, the first filter circuit 208 can also be implemented by using other infinite impulse response systems, and these design changes also belong to the scope of the present invention. As shown in FIG. 2 , the first filter circuit 208 in the filter module 202 includes (but not limited to) a first multiplication unit 210 , a second multiplication unit 212 , an addition unit 214 , a storage unit 216 and a weighted value setting unit 218 . The first multiplication unit 210 is used for multiplying each piece of data in the video input S_IN (for example, each sampling value of the composite video signal) by a first weighted value W (0≤W≤1) to generate a first multiplication output M1. The second multiplication unit 212 is coupled to the storage unit 216, and is used to multiply each piece of data in the processing result D_IIR stored in the storage unit 216 (for example, each sample value processed by weighted average) by a second weighted value ( 1-W) to generate the second multiplication output M2. The addition unit 214 is coupled to the first multiplication unit 210, the second multiplication unit 212 and the storage unit 216, and is used for summing the first multiplication output M1 and the second multiplication output M2 to generate an addition output M3, wherein M3=M1*W+ M2*(1−W), and write the addition output M3 into the storage unit 216 to update each piece of data corresponding to the processing result D_IIR stored in the storage unit 216 .

In this embodiment, the addition output M3 generated by the addition unit 214 is not only written back to the storage unit 216 for data update, but also directly used as the filter output S_OUT of the filter module 202 (that is, S_OUT=M3); in addition, the storage unit 216 is a line buffer (line buffer), and its buffer depth is equal to the predetermined total number of sampling points of a scan line. Therefore, under ideal conditions, each time the sampling data of a scan line is input, the storage unit 216 will just store the scan line The sampled data of is processed by infinite impulse response filtering. In addition, since the line buffer is an element originally included in the analog TV decoder, the first filter circuit 208 can use the existing line buffer as the required storage unit 216, thereby saving operational requirements. hardware cost.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of an infinite impulse response filtering process performed by the first filtering circuit 208 . Assume that during the period T ₀ -T ₁ , the filtering module 202 receives the sampling data D0 of the first scan line in the first frame one by one, and the sampling data D0 will be directly written into the storage unit 216 as the stored data in the storage unit 216. The initial processing result D_IIR ₀ , that is, D_IIR ₀ =D ₀ . From time T2, each piece of data (sampling value) in the sampling data D1 of the second scan line in the first frame starts to be input to the first filter circuit 208 one by one, when the first sampling data D1 is received When sampling values, the first filter circuit 208 will read out the corresponding processing oversampling value in the initial processing result D_IIR ₀ from the storage unit 216, and generate a new processing oversampling value through the above-mentioned infinite impulse response filtering process to store unit 216, and subsequent sampled values in the sampled data D1 will also undergo infinite impulse response filtering one by one. Therefore, in the period T ₁ ~ T ₂ , the first filter circuit 208 can be regarded as based on the initial processing result D_IIR ₀ and The sampling data D1 is processed by infinite impulse response filtering, so at time T ₂ , the storage unit 216 stores the updated processing result D_IIR ₁ . Similarly, during the period _T2 - _T3 , the first filter circuit 208 can be regarded as performing infinite impulse response filtering based on the processing result _{D_IIR1} and the next sampling data D1, so at the time _T3 , the storage unit 216 is The updated processing result D_IIR ₂ will be stored. Since those skilled in the art can easily know the subsequent operations after reading the above description, details are not repeated here.

Since the first filter circuit 208 will perform infinite impulse response filtering on the video input S_IN, and then input the filtered output S_OUT (that is, the filtered video input S_IN) generated by the infinite impulse response filtering to subsequent circuits (such as clipping level detector 204 and comparator 206), therefore, for clipping level detector 204 and comparator 206, since the filtered video input S_IN can input unwanted interference components in the original video input S_IN (such as white noise and co-channel interference, etc.) can be effectively filtered or attenuated, therefore, the limit level SL judged by the limit level detector 204 and the synchronization signal limit generated by the comparator 206 can be greatly improved Output the accuracy of Sliced_SYNC to improve the final picture display quality.

Please note that in this embodiment, the first filter circuit 208 is further provided with a weight value setting unit 218, which is coupled to the first multiplication unit 210 and the second multiplication unit 212, and is used to set the weight value according to the signal characteristic of the video input S_IN Set the first weighted value W and the second weighted value (1-W), for example, the weighted value setting unit 218 will dynamically adjust based on the signal-to-noise ratio (SNR) of the video input S_IN The first weighted value W and the second weighted value (1-W), therefore, when the signal-to-noise ratio of the video input S_IN is high (representing that the degree of interference of the video input S_IN is less severe), the weighted value setting unit 218 will Increase the first weighted value W and reduce the second weighted value (1-W), on the other hand, when the signal-to-noise ratio of the video input S_IN is low (representing the degree of interference of the video input S_IN is more serious), then the weighted value setting Single 218 will reduce the first weighted value W and increase the second weighted value (1-W), in other words, the first weighted value W is positively related to the SNR, while the second weighted value (1-W) is negatively correlated.

According to the above description, it can be seen that the setting of the weight value setting unit 218 can make the first weight value W and the second weight value (1-W) dynamically adjusted along with the actual signal quality of the video input S_IN itself, so that the first The filtering circuit 208 may have better performance of infinite impulse response filtering processing, however, the weight value setting unit 218 may actually be an optional element, for example, in another embodiment, if in a specific operating environment If the actual signal quality of the video input S_IN is very stable, then the first filter circuit 208 can omit the weight value setting unit 218, and only use a set of preset first weight values W and second weight values (1- W), and changes in this design also belong to the category of the present invention.

Fig. 4 is a flow chart of the first embodiment of the synchronization signal clipping method of the present invention. The flow shown in FIG. 4 is applied to the synchronization signal clipping device 200 shown in FIG. 2 . In addition, if substantially the same result can be obtained, the steps do not have to be executed in the order shown in FIG. 4 . The operation of the first embodiment of the synchronous signal limiting method of the present invention can be simply summarized as follows:

Step 402: Receive a video input (eg sample data of a composite video signal).

Step 404: Perform infinite impulse response filtering (eg, weighted averaging) on the video input to generate a filtered output.

Step 406: Determine the clipping level corresponding to the synchronous signal component (such as the horizontal synchronous signal component) according to the filtered output.

Step 408: Compare the slice level with the filtered output to generate a sync signal slice output. Next, go back to step 404 to continue processing the video input using the infinite impulse response filtering process.

Since those skilled in the art should be able to easily understand the operation details of each step after reading the above technical content about the synchronization signal clipping device 200 , relevant descriptions will not be repeated here.

In the above-mentioned embodiment, the storage unit 216 is a line buffer, and its buffer depth is equal to the total number of predetermined sampling points of a scanning line. Therefore, under ideal conditions, the storage unit 216 will just store the sampling data of each scanning line. The sampling data of this scan line is the result of infinite impulse response filtering. However, if the scan line period (line period) of the video input S_IN is unstable (for example, the source of the video input S_IN is a video cassette recorder (videocassette recorder) , VCR), so it is often limited by the characteristics of the reading mechanism itself, resulting in unstable scan line cycle) or changes (for example, the source of video input S_IN does not provide standard video output), so under the same sampling frequency, a The actual total number of sampling points of the scanning line will not be equal to the predetermined total number of sampling points (that is, the buffer depth of the line buffer), which will cause the situation that the video input S_IN and the processing result D_IIR cannot be aligned at this time, which may cause the filter module 202 to generate The signal quality of the filtered output S_OUT (that is, the filtered video input S_IN) deteriorates. Therefore, the present invention also discloses an adaptive filtering mechanism, which can dynamically select an appropriate filtering process according to the judgment criteria. Way.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of a second embodiment of a synchronization signal limiting device of the present invention. The synchronous signal clipping device 500 includes (but not limited to) a filtering module 502 and the clipping level detector 204 and the comparator 206 shown in FIG. In addition, a second filter circuit 508 , a multiplexer 510 and a control circuit 512 are further included. Since the functions and operations of the first filter circuit 208 , the slice level detector 204 and the comparator 206 have been described in detail above, they will not be repeated here. For the second filtering circuit 508, it also receives the video input S_IN, but performs predetermined filtering processing on the video input S_IN, and the predetermined filtering processing is different from the infinite impulse response filtering processing performed by the first filtering circuit 208, for example Generally speaking, the predetermined filtering process is a simple low-pass filtering process. Therefore, the second filtering circuit 508 will use multiple pieces of data corresponding to the same scanning line in the video input S_IN (for example, multiple data corresponding to the same scanning line in the composite video signal) sampled value) to carry out the average calculation and output the average value, however, this is only used as an example for illustration, and is not a limitation of the present invention, that is, in other embodiments, the predetermined filtering process can also use other types of filtering. In a broad sense, as long as the processing mechanism is different from the infinite impulse response filtering process adopted by the first filter circuit 208, it can be applied to the second filter circuit 508 without violating the inventive spirit of the present invention, and these designs The above changes all belong to the category of the present invention.

In addition, the multiplexer 510 has a plurality of input ports N1 and N2 respectively coupled to the first filter circuit 208 and the second filter circuit 508, a control port N3 and an output port N4, wherein the output port N4 is used to output the filter module 502 The filtered output S_OUT. The control circuit 512 is coupled to the control port N3, and is used to generate the selection signal SEL to the control port N3, so as to control the multiplexer 510 to output the output of the first filter circuit 208 (that is, the output of the adding unit 214 shown in FIG. 2 The addition output M3) of the second filter circuit 508 (for example, the result of low-pass filter processing) M3' is delivered to the output port N4 as the filter output S_OUT.

As shown in FIG. 5 , the comparator 206 will input the sliced_SYNC output of the synchronous signal to the clock generating device (such as a phase-locked loop) 501 for processing to generate a synchronous clock (such as a horizontal synchronous clock) CLK_SYNC, and the control circuit 512 is based on the synchronous The period of the clock CLK_SYNC is used to generate the selection signal SEL. For example, under the default operating state, the control circuit 512 will generate the selection signal SEL to control the multiplexer 510 to transmit the output M3 of the first filter circuit 208 to the output port N4 as the filtered output S_OUT In other words, the filter module 502 defaults to use the first filter circuit 208. However, when the control circuit 512 subsequently detects that the period of the synchronous clock CLK_SYNC is different from the ideal value of the scanning line period or detects that the period of the synchronous clock CLK_SYNC is different from the ideal If the value difference (phase difference) exceeds the allowable error range, the control circuit 512 immediately controls the multiplexer 510 to select the output M3' of the second filter circuit 508 to the output port through the adjustment of the selection signal SEL N4 is used as the filtered output S_OUT.

Please note that the control circuit 512 can also generate the selection signal SEL according to the statistical result of the synchronous clock CLK_SYNC period. For example, when the control circuit 512 detects the average period of the synchronous clock CLK_SYNC (which can be measured by (calculated from the statistical results of the period length) is different from the ideal value of the scan line period or detects that the difference (phase difference) between the average period of the synchronous clock CLK_SYNC and the ideal value exceeds the allowable error range, the control circuit 512 will The multiplexer 510 is controlled by adjusting the selection signal SEL to select and transmit the output M3 ′ of the second filter circuit 508 to the output port N4 as the filter output S_OUT, and this design change also belongs to the scope of the present invention.

In addition, if the filtering module 502 is currently switched to the use of the second filtering circuit 508, when the control circuit 512 subsequently detects that the period/average period of the synchronous clock CLK_SYNC is the same as the ideal value of the scanning line period or the period/average period of the synchronous clock CLK_SYNC If the difference (phase difference) from the ideal value falls within the allowable error range, the multiplexer 510 can be controlled by the selection signal SEL to select the output M3' of the second filter circuit 508 to be delivered to the output port N4 for As the filter output S_OUT, therefore, the filter module 502 resumes using the preset first filter circuit 208 at this time.

FIG. 6 is a flow chart of the second embodiment of the synchronization signal clipping method of the present invention. The process shown in FIG. 6 is applied to the synchronization signal clipping device 500 shown in FIG. 5 . In addition, if substantially the same result can be obtained, the steps do not have to be executed in the order shown in FIG. 6 . The operation of the second embodiment of the synchronization signal limiting method of the present invention can be simply summarized as follows:

Step 602: Receive a video input (such as sample data of a composite video signal).

Step 604: Perform infinite impulse response filtering (eg, weighted averaging) on the video input to generate a filtered output.

Step 606: Determine the clipping level corresponding to the synchronous signal component (such as the horizontal synchronous signal component) according to the filtered output.

Step 608: Compare the slice level with the filter output to generate a sync signal slice output.

Step 610: Determine whether the period/average period of the synchronous clock CLK_SYNC is different from the ideal value of the scan line period or whether the difference (phase difference) between the period/average period of the synchronous clock CLK_SYNC and the ideal value exceeds the allowable error range. It is necessary to switch to a predetermined filtering process different from the infinite impulse response filtering process (such as low-pass filtering process), if so, execute step 612 , otherwise, go back to step 604 and continue to use the infinite impulse response filtering process.

Step 612: Perform predetermined filter processing on the video input to generate the filter output.

Step 614: Determine the clipping level according to the filtered output.

Step 616: Compare the clipping level with the filtered output to generate the sync signal clipped output.

Step 618: Judging according to whether the period/average period of the synchronous clock CLK_SYNC is the same as the ideal value of the scanning line period or whether the difference (phase difference) between the period/average period of the synchronous clock CLK_SYNC and the ideal value falls within the allowable error range Whether it is necessary to restore the infinite impulse response filtering process, if yes, execute step 604, otherwise, return to step 612 and continue to use the predetermined filtering process.

Since those skilled in the art should be able to easily understand the operation details of each step after reading the above technical content about the synchronization signal clipping device 500 , relevant descriptions will not be repeated here.

Although the present invention has been disclosed above with respect to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the preceding claims.

Claims (20)

1. A synchronous signal limiting device, characterized in that, comprises: The filtering module is used to process the video input to generate the filtering output, and the filtering module includes: a first filtering circuit, which receives the video input and performs infinite impulse response filtering on the video input; A clipping level detector, coupled to the filter module, is used to receive the filter output, and determine the clipping level corresponding to the synchronous signal component according to the filter output; and A comparator, coupled to the clipping level detector and the filtering module, is used to receive the filtering output and the clipping level, and compare the clipping level and the filtering output to generate a synchronous signal clipping output . 2. The synchronization signal limiting device according to claim 1, wherein the synchronization signal component is a horizontal synchronization signal component. 3. The synchronous signal limiting device according to claim 1, wherein the first filtering circuit comprises: storage unit; A first multiplication unit, which multiplies each piece of data in the video input by a first weighted value to generate a first multiplication output; A second multiplication unit, coupled to the storage unit, is used to multiply each piece of data in the processing result stored in the storage unit by a second weighted value to generate a second multiplication output; and an addition unit, coupled to the first multiplication unit, the second multiplication unit and the storage unit, for summing the first multiplication output and the second multiplication output to generate an addition output, and writing the addition output to The storage unit updates each piece of data corresponding to the processing results stored in the storage unit. 4. The synchronous signal clipping device according to claim 3, wherein the storage unit is a line buffer whose buffer depth is equal to the total number of predetermined sampling points of a scanning line. 5. The synchronous signal limiting device according to claim 3, wherein the first filtering circuit further comprises: The weight setting unit is coupled to the first multiplication unit and the second multiplication unit, and is used for setting the first weight value and the second weight value according to the signal characteristic of the video input. 6. The synchronous signal limiting device according to claim 5, wherein the signal characteristic is a signal-to-noise ratio. 7. The synchronization signal clipping device as claimed in claim 6, wherein the first weighting value is positively correlated with the SNR, and the second weighting value is negatively correlated with the SNR. 8. The synchronous signal limiting device as claimed in claim 1, wherein the filter module further includes: a second filtering circuit, which receives the video input and performs predetermined filtering processing on the video input, wherein the predetermined filtering processing is different from the infinite impulse response filtering processing performed by the first filtering circuit; a multiplexer, having a control port, an output port, and a plurality of input ports respectively coupled to the first filter circuit and the second filter circuit, wherein the output port is used to output the filter output of the filter module; and A control circuit, coupled to the control port, is used to generate a selection signal to the control port to control the multiplexer to transmit the output of the first filter circuit or the output of the second filter circuit to the output port. 9. The synchronous signal limiting device according to claim 8, characterized in that, the comparator inputs the synchronous signal limiting output to the clock generating device for processing to generate a synchronous clock, and the control circuit is based on the synchronous clock cycle to generate the select signal. 10. The synchronous signal limiting device according to claim 9, wherein the control circuit generates the selection signal according to the statistical result of the period of the synchronous clock. 11. A synchronous signal limiting method, characterized in that, comprising: Process video input to produce filtered output, including: Apply infinite impulse response filtering to the video input; determining the clipping level corresponding to the synchronous signal component according to the filtered output; and The clipping level is compared with the filtered output to produce a sync signal clipped output. 12. The synchronization signal clipping method according to claim 11, wherein the synchronization signal component is a horizontal synchronization signal component. 13. The synchronization signal limiting method according to claim 11, wherein the infinite impulse response filtering process comprises: multiplying each piece of data in the video input by a first weighted value to generate a first multiplication output; multiplying each piece of data in the processing results stored in the storage unit by a second weighted value to generate a second multiplication output; and summing the first multiplication output and the second multiplication output to generate an addition output, and writing the addition output to the storage unit to update each piece of data corresponding to the processing result stored in the storage unit. 14. The synchronization signal clipping method according to claim 13, wherein the storage unit is a line buffer whose buffer depth is equal to the total number of preset sampling points of a scan line. 15. The synchronous signal limiting method according to claim 13, wherein the infinite impulse response filtering process further comprises: The first weighted value and the second weighted value are set according to the signal characteristic of the video input. 16. The synchronization signal limiting method according to claim 15, wherein the signal characteristic is a signal-to-noise ratio. 17. The synchronization signal clipping method of claim 16, wherein the first weighting value is positively correlated with the SNR, and the second weighting value is negatively correlated with the SNR. 18. The synchronization signal clipping method as claimed in claim 11, wherein the step of processing the video input to generate the filtered output further comprises: performing predetermined filtering on the video input, wherein the predetermined filtering is different from the infinite impulse response filtering; and The output of the infinite impulse response filtering or the output of the predetermined filtering process is selected as the filtering output. 19. The synchronous signal clipping method according to claim 18, characterized in that, the synchronous signal clipping output is further processed by a clock generating device to generate a synchronous clock, and the output of the infinite impulse response filter or the predetermined filter is selected The steps to process the output as the filtered output include: The output of the infinite impulse response filtering or the output of the predetermined filtering process is selectively output based on the period of the synchronous clock. 20. The synchronous signal limiting method according to claim 19, wherein the step of selecting and outputting the output of the infinite impulse response filter or the output of the predetermined filtering process based on the period of the synchronous clock comprises: The output of the infinite impulse response filtering or the output of the predetermined filtering process is selected and output according to the statistical result of the cycle of the synchronous clock.

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