CN102148245B - intrinsic MOS transistor and forming method thereof - Google Patents
intrinsic MOS transistor and forming method thereof Download PDFInfo
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- CN102148245B CN102148245B CN201010111103.7A CN201010111103A CN102148245B CN 102148245 B CN102148245 B CN 102148245B CN 201010111103 A CN201010111103 A CN 201010111103A CN 102148245 B CN102148245 B CN 102148245B
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Abstract
A kind of intrinsic MOS transistor and forming method thereof, the forming method of described intrinsic MOS transistor includes: provide Semiconductor substrate, being sequentially formed with gate dielectric layer and gate electrode in described Semiconductor substrate, the Semiconductor substrate of described gate electrode side is source region, and the Semiconductor substrate of opposite side is drain region；Described source region and drain region are carried out the first ion implanting, in described Semiconductor substrate, directly forms source electrode and drain electrode；Described gate electrode carries out the second ion implanting, and the ionic type of described second ion implanting is contrary with the ionic type of described first ion implanting.The present invention improves the threshold voltage of intrinsic MOS transistor.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly to a kind of intrinsic MOS transistor and formation side thereof
Method.
Background technology
Along with the raising of integrated circuit integrated level, device size is the most scaled, current characteristic size
Reach 32nm magnitude.Metal oxide semiconductor field effect tube (MOS) is modal semiconductor device
Part, is the elementary cell constituting various complicated circuits.MOS transistor basic structure includes three main region
Territory: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode are logical
Cross highly doped formation, different according to type of device, N-shaped doping (NMOS) and p-type doping can be divided into
(PMOS)。
Owing to the threshold voltage of MOS transistor is relevant with substrate doping, brilliant in order to improve MOS
The threshold voltage (threshold voltage) of body pipe, MOS transistor of the prior art is to be formed mostly
In well region (well) in the semiconductor substrate, as a example by nmos pass transistor, its forming process includes:
Semiconductor substrate is carried out p-type ion implanting, forms p-well (P-well)；Described p-well sequentially forms
Gate dielectric layer and gate electrode；For mask, described Semiconductor substrate is carried out N-type ion implanting, shape with gate electrode
Become source/drain.
It addition, also there is a type of MOS transistor in prior art, it is not formed in well region,
And be directly formed in Semiconductor substrate, this type of MOS transistor is referred to as intrinsic MOS transistor
(native MOS).Still as a example by nmos pass transistor, its forming process includes: serve as a contrast at P-type semiconductor
Gate dielectric layer and gate electrode is sequentially formed at the end；For mask, described Semiconductor substrate is carried out N-type with gate electrode
Ion implanting, forms source/drain.Owing to intrinsic MOS transistor is directly formed in Semiconductor substrate,
Its forming process does not include the ion implantation process of well region.Owing to being formed without the ion implantation process of well region,
The doping content of described P-type semiconductor substrate than the common MOS transistor being formed with well region substrate (i.e.
Well region) much lower, thus its threshold voltage is the most much lower.Still as a example by nmos pass transistor, this
Levy the threshold voltage of nmos pass transistor close to 0, for " normally opened " (already on) state, belong to consumption
Type MOS transistor to the greatest extent；The threshold voltage of the nmos pass transistor being formed in well region is then positive voltage,
For reinforcing MOS transistor.
Owing to intrinsic MOS transistor has a higher response speed, thus more it is applied to low-voltage electricity
In road and current mirroring circuit.But, owing to its threshold voltage is relatively low, belong to depletion-type mos transistor,
For normally open, limit its range of application.
About intrinsic MOS transistor, more detailed contents refer to disclosed Application No.
200310109233.7 Chinese patent application.
Summary of the invention
The problem that the present invention solves is to provide a kind of intrinsic MOS transistor and manufacture method thereof, improves intrinsic
The threshold voltage of MOS transistor.
For solving the problems referred to above, the invention provides a kind of intrinsic MOS transistor, including:
Semiconductor substrate；
Gate dielectric layer, is formed in described Semiconductor substrate；
Gate electrode, is formed on described gate dielectric layer；
Source electrode and drain electrode, be formed directly in the Semiconductor substrate of described gate electrode both sides respectively；
The doping type of described gate electrode is contrary with the doping type of source electrode and drain electrode.
Optionally, the doping type of described Semiconductor substrate is p-type ion, mixing of described source electrode and drain electrode
Miscellany type is N-type ion, and the doping type of described gate electrode is p-type ion.
Optionally, the doping type of described Semiconductor substrate is N-type ion, mixing of described source electrode and drain electrode
Miscellany type is p-type ion, and the doping type of described gate electrode is N-type ion.
Optionally, the doping content scope of described Semiconductor substrate is 1E16/cm3To 10E16/cm3。
Optionally, the doping content scope of described source electrode and drain electrode is 1E19/cm3To 10E19/cm3。
Optionally, the doping content scope of described gate electrode is 1E19/cm3To 10E19/cm3。
Optionally, described intrinsic MOS transistor also includes side wall, is formed at described gate electrode and gate medium
In the Semiconductor substrate of layer both sides.
For solving the problems referred to above, the invention provides the forming method of a kind of intrinsic MOS transistor, including:
Semiconductor substrate is provided, described Semiconductor substrate is sequentially formed with gate dielectric layer and gate electrode, institute
The Semiconductor substrate stating gate dielectric layer and described gate electrode side is source region, and the Semiconductor substrate of opposite side is
Drain region；
First described source region and drain region are carried out the first ion implanting, directly formed in described Semiconductor substrate
Source electrode and drain electrode；
Then described gate electrode is carried out the second ion implanting, the ionic type of described second ion implanting with
The ionic type of described first ion implanting is contrary；
Also include before described source region and drain region are carried out the first ion implanting: described source region and drain region are entered
Row is lightly doped ion implanting, forms lightly doped source electrode and drain electrode；
After ion implanting is lightly doped, before the first ion implanting, form side wall in described gate electrode both sides.
Optionally, the doping type of described Semiconductor substrate is p-type ion, described first ion implanting
Ionic type is N-type ion, and the ionic type of described second ion implanting is p-type ion.
Optionally, the ion of described first ion implanting is P ion or As ion, described second ion note
The ion entered is B ion or In ion.
Optionally, the doping type of described Semiconductor substrate is N-type ion, described first ion implanting
Ionic type is p-type, and the ionic type of described second ion implanting is N-type.
Optionally, the ion of described first ion implanting is B ion or In ion, described second ion note
The ion entered is P ion or As ion.
Optionally, the doping content scope of described Semiconductor substrate is 1E16/cm3To 10E16/cm3。
Optionally, the dosage of described first ion implanting is 1E15/cm2To 10E15/cm2, energy is
50KeV to 70KeV.
Optionally, the dosage of described second ion implanting is 1E15/cm2To 10E15/cm2, energy is
30KeV to 50KeV.
Optionally, also include before described source region and drain region are carried out the first ion implanting: to described source region
Carry out ion implanting is lightly doped with drain region, form lightly doped source electrode and drain electrode.
Optionally, the dosage that ion implanting is lightly doped described in is 1E13/cm2To 10E13/cm2, energy is
50KeV to 70KeV.
Optionally, after described source region and drain region are lightly doped ion implanting and carry out the first ion
Also include before injection: form side wall in the both sides of described gate electrode and gate dielectric layer.
Compared with prior art, technique scheme has the advantage that intrinsic MOS of the technical program
Transistor is formed directly in Semiconductor substrate, does not form well region, and the doping type of gate electrode and source
The doping type of pole and drain electrode is contrary, thus improves the threshold voltage of intrinsic MOS transistor.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the forming method of the intrinsic MOS transistor of the embodiment of the present invention；
Fig. 2 to Fig. 6 is each step of the forming process of the intrinsic NMOS transistor of the embodiment of the present invention
Cross-sectional view；
Fig. 7 is the structural representation of the intrinsic NMOS transistor that the embodiment of the present invention is formed.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Elaborate detail in the following description so that fully understanding the present invention.But the present invention can
Being different from alternate manner described here implement with multiple, those skilled in the art can be without prejudice to this
Similar popularization is done in the case of invention intension.Therefore the present invention is not limited by following public being embodied as.
Intrinsic MOS transistor of the prior art is formed directly in Semiconductor substrate, does not form trap
District, and during forming source/drain, carry out ion implanting with gate electrode for mask, formed
While source/drain, the scope of ion implanting also includes gate electrode simultaneously so that the doping class of gate electrode
Type is identical with the doping type of source/drain.As a example by intrinsic NMOS transistor, its source/drain is N-type
Doping, gate electrode is also n-type doping, and corresponding Semiconductor substrate is P-type semiconductor substrate, owing to not having
Having and carry out ion implanting formation well region, the doping content of described Semiconductor substrate is relatively low.Owing to quasiconductor serves as a contrast
The doping content at the end and the material of gate electrode and doping type can affect the threshold voltage of MOS transistor,
And the doping type of the gate electrode of the intrinsic MOS transistor of prior art is identical with Semiconductor substrate, therefore
Gate electrode is less with the work function difference of Semiconductor substrate (work function difference), causes prior art
The threshold voltage of intrinsic MOS transistor less, close to 0, for normally open, have impact on its application
Scope.
The forming method of the intrinsic MOS transistor that the present invention provides, enters respectively to source/drain and gate electrode
Row ion implanting so that the doping type of gate electrode is the most identical with Semiconductor substrate with source/drain, from
And increase the work function difference between gate electrode and Semiconductor substrate, improve the threshold of intrinsic MOS transistor
Threshold voltage.
Fig. 1 is the schematic flow sheet of the forming method of the intrinsic NMOS transistor of the embodiment of the present invention.As
Shown in Fig. 1, including: perform step S101, it is provided that Semiconductor substrate, in described Semiconductor substrate successively
Being formed with gate dielectric layer and gate electrode, the Semiconductor substrate of described gate electrode side is source region, opposite side
Semiconductor substrate is drain region；Perform step S102, described source region and drain region carried out the first ion implanting,
Source electrode and drain electrode is directly formed in described Semiconductor substrate；Perform step S103, described gate electrode is entered
The ion of row the second ion implanting, the ionic type of described second ion implanting and described first ion implanting
Type is contrary.
Below in conjunction with Fig. 2 to Fig. 6, the forming method of the intrinsic NMOS transistor of the embodiment of the present invention is entered
Row describes in detail.
With reference to Fig. 1 and Fig. 2, perform step S101, it is provided that Semiconductor substrate, in described Semiconductor substrate
Being sequentially formed with gate dielectric layer and gate electrode, the Semiconductor substrate of described gate electrode side is source region, another
The Semiconductor substrate of side is drain region.
The present embodiment specifically includes: providing Semiconductor substrate 100, described Semiconductor substrate 100 is p-type
Semiconductor substrate, doping content is 1E16/cm3To 10E16/cm3, preferred 5E16/cm in the present embodiment3,
Its material can be silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure, it is also possible to be silicon-on-insulator
(SOI).Or the III-V such as other material, such as GaAs can also be included.
Being formed with gate dielectric layer 101 on the surface of described Semiconductor substrate 100, its material is silicon oxide, thick
Degree is for tens of to hundreds of angstroms, and its deposition process can be conventional vacuum coating technique, such as boiler tube thermal oxide,
Ald (ALD), chemical vapour deposition (CVD), plasma-enhanced chemical vapor deposition
(PECVD) technique, the present embodiment specifically uses boiler tube thermal oxidation technology.
Gate electrode layer (not shown), the material of described gate electrode layer is formed afterwards on gate dielectric layer 101
For polysilicon, its forming method is low-pressure chemical vapor phase deposition (LPCVD), the thickness of described gate electrode layer
Between hundreds of to thousand of angstroms.Then described gate electrode layer is patterned, forms intrinsic NMOS crystal
The gate electrode 102 of pipe.So far, the device architecture of formation is as shown in Figure 2.Process above flow process is all with existing
Intrinsic NMOS transistor process flow consistent.
After described gate electrode 102 is formed, described Semiconductor substrate 100 is divided into three parts, Qi Zhong
A part is for be positioned at gate electrode 102 and the part of gate dielectric layer less than 101, for intrinsic NMOS transistor
Channel region, second and third part is as shown in Tu2Zhong I district and IIth district, for being positioned at described gate electrode 102
The part of both sides, respectively source region and drain region, from structure, source region and drain region are equivalent, but at tool
Body circuit varies in size according to applied voltage polarity and can distinguish source region and drain region.In the present embodiment I
District is source region, and IIth district is drain region.
In the present embodiment, after forming gate electrode 102, also include described source region and drain region are carried out gently
Dopant ion injects.As it is shown on figure 3, the type that ion implanting is lightly doped described in the present embodiment is N-type,
Dopant ion is selected from phosphorus (P) ion or arsenic (As) ion；Described ion implanting is lightly doped dosage be
1E13/cm2To 10E13/cm2, energy is 50KeV to 70KeV, and in the present embodiment, preferred dosage is
5E13/cm2, preferred energy is 60KeV.Through described ion implanting is lightly doped after, define and gently mix
Miscellaneous source electrode 103 and lightly doped drain electrode 104.It should be noted that described ion implanting is lightly doped before,
Be formed with photoetching offset plate figure (not shown) on the surface of described gate electrode 102, therefore described in ion is lightly doped
The scope injected does not includes described gate electrode 102.Described ion implanting is lightly doped after, by described photoetching
Glue pattern is removed.It should be noted that in other embodiments of the technical program, it is also possible to do not carry out
Described ion implanting is lightly doped.
As shown in Figure 4, described ion implanting is lightly doped after, in formation side, described gate electrode 101 both sides
Wall 105.Specifically include: dielectric layer (not shown) on the gate dielectric layer of described Semiconductor substrate 100,
The present embodiment is silica material, and generation type can be low-pressure chemical vapor phase deposition (LPCVD), thickness
Higher than the height of described gate electrode 102, described dielectric layer also can be selected for oxide layer-silicon nitride-silicon oxide layer
(ONO) structure.Carry out back described dielectric layer carving (etch back) technique, at described gate electrode 102
Both sides form side wall (spacer) 105.
In conjunction with Fig. 1 and Fig. 5, perform step S102, described source region and drain region carried out the first ion implanting,
Source electrode and drain electrode is directly formed in described Semiconductor substrate.
In the present embodiment, first in described Semiconductor substrate 100 and gate electrode 102, spin coating forms the first light
Photoresist layer, and be patterned, form the first photoetching offset plate figure 106.Described first photoetching offset plate figure 106
Define the shape in source region and drain region, and cover the surface of described gate electrode 102.
Afterwards with described first photoetching offset plate figure 106 as mask, carry out the first ion implanting, described first
The ionic type of ion implanting is N-type, and such as P ion or As ion, its implantation dosage is 1E15/cm2
To 10E15/cm2, energy is 50KeV to 70KeV, and in the present embodiment, preferred dosage is 5E15/cm2,
Preferably energy is 60KeV.After described first ion implanting, form respectively source electrode 103a and leakage
Pole 104a.Mask effect due to described first photoetching offset plate figure 106 so that described first ion implanting
Scope do not include described gate electrode 102, therefore gate electrode 102 does not include the first ion implanting
Ion.Further, since the barrier effect of side wall 105 so that the scope of described first ion implanting is not
Including the semiconductor substrate region below described side wall 105, this region constitutes lightly doped LDD
(lightly doped drain) structure 103b and 104b.After described first ion implanting, described
Directly defining source electrode 103a and drain electrode 104a in Semiconductor substrate 100, its doping content is 1E19/cm3
To 10E19/cm3.After described first ion implanting, remove described first light by ashing (ashing)
Photoresist figure 106, exposes the surface of described gate electrode 102.
It should be noted that described source electrode 103a and drain electrode 104a is formed directly into Semiconductor substrate 100
In, refer to source electrode 103a and the drain electrode raceway groove between 104a, source/drain of intrinsic MOS transistor
All it is formed directly in Semiconductor substrate, is formed without dopant well in Semiconductor substrate, is formed at routine
The source electrode of the MOS transistor in the well region of doping is different with drain electrode.
Although it is emphasized that in portion of techniques scheme of the prior art such as relevant patent application also
Not mentioned formation well region in Semiconductor substrate, but those skilled in the art can push away according to Conventional wisdom
Knowing the well region containing doping in its substrate, the improvement being only because its scheme is unrelated with dopant well or substrate,
So not having specifically mentioned, therefore they are different from the forming process forming intrinsic MOS transistor.
In conjunction with Fig. 1 and Fig. 6, perform step S103, described gate electrode is carried out the second ion implanting, institute
The ionic type stating the second ion implanting is contrary with the ionic type of described first ion implanting.
In the present embodiment, first on the surface of described Semiconductor substrate 100 and gate electrode 102, spin coating is formed
Second photoresist layer, and be patterned, form the second photoetching offset plate figure 107.Described second photoetching
Glue pattern 107 has defined the region of gate electrode 102, and covers described source electrode 103a and drain electrode 104a.
Afterwards with described second photoetching offset plate figure 107 as mask, carry out the second ion implanting.Described second
The ionic type of ion implanting is p-type, and such as boron (B) ion or indium (In) ion, its implantation dosage is
1E15/cm2To 10E15/cm2, energy is 30KeV to 50KeV, and in the present embodiment, preferred dosage is
5E15/cm2, preferred energy is 40KeV.Due to the mask effect of described second photoetching offset plate figure 107,
The scope making described second ion implanting does not include described source electrode 103a and drain electrode 104a, therefore grid electricity
Pole 102 only includes the ion of the second ion implanting.After described second ion implanting, described grid electricity
The doping content of pole 102 is 1E19/cm3To 10E19/cm3。
After described second ion implanting, remove described second photoetching offset plate figure 107 by ashing (ashing),
Expose described source electrode 103a and the semiconductor substrate surface in drain electrode 104a region.
So far, the intrinsic NMOS transistor that the present embodiment is formed structure as it is shown in fig. 7, comprises: half
Conductor substrate 100；Gate dielectric layer 101, is formed in described Semiconductor substrate 100；Gate electrode 102,
It is formed on described gate dielectric layer 101；Source electrode 103a and drain electrode 104a, is formed directly into described grid respectively
In the Semiconductor substrate 100 of electrode 102 and gate dielectric layer 101 both sides.The intrinsic that the present embodiment is formed
Nmos pass transistor also includes LDD structure 103b and the 104b of source electrode and drain electrode.Fig. 7 in the present embodiment
Shown structure is intrinsic NMOS transistor, and the doping type of described Semiconductor substrate 100 is p-type,
Doping content is 1E16/cm3To 10E16/cm3.Described source electrode 103a and the doping type of drain electrode 104a
For N-type, doping content is 1E19/cm3To 10E19/cm3.The doping type of described gate electrode 102 is
P-type, doping content is 1E19/cm3To 10E19/cm3。
Technique scheme is during forming intrinsic NMOS transistor, by different types of ion
Injection process so that gate electrode is contrary with the doping type of source electrode and drain electrode, is specially in this embodiment
Source/drain is n-type doping, and gate electrode is p-type doping, therefore, and the intrinsic NMOS crystal of formation
Work function difference between the gate electrode of pipe and Semiconductor substrate is relatively big, thus increases the intrinsic NMOS of formation
The threshold voltage of transistor.Find through inventor's measurement Research, the intrinsic NMOS that above-described embodiment is formed
The threshold voltage of transistor is about 1V, much larger than 0 so that it is become enhancement transistor, for normal off
(already off) state.
Above-described embodiment is as a example by forming intrinsic NMOS transistor, the technical program can be also used for
Form intrinsic PMOS transistor.The knot of the intrinsic PMOS transistor of its concrete forming process and formation
Structure is basically identical with intrinsic NMOS transistor, and difference is the Semiconductor substrate of intrinsic PMOS transistor
Type is N-type, and source drain doping type is p-type, and gate electrode doping type is N-type.
The above is two specific embodiments of the present invention, forms intrinsic NMOS transistor and basis respectively
Levy PMOS transistor.By source/drain and gate electrode are carried out ion implanting respectively so that gate electrode
Doping type is the most identical with Semiconductor substrate with source/drain, thus increases gate electrode and serve as a contrast with quasiconductor
Work function difference at the end, improves the threshold voltage of intrinsic MOS transistor.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (9)
1. the forming method of an intrinsic MOS transistor, it is characterised in that including:
Semiconductor substrate is provided, described Semiconductor substrate is sequentially formed with gate dielectric layer and gate electrode, institute
The Semiconductor substrate stating gate dielectric layer and described gate electrode side is source region, and the Semiconductor substrate of opposite side is
Drain region；
First described source region and drain region are carried out the first ion implanting, directly formed in described Semiconductor substrate
Source electrode and drain electrode；
Then described gate electrode is carried out the second ion implanting, the ionic type of described second ion implanting with
The ionic type of described first ion implanting is contrary；
Also include before described source region and drain region are carried out the first ion implanting: described source region and drain region are entered
Row is lightly doped ion implanting, forms lightly doped source electrode and drain electrode；
After ion implanting is lightly doped, before the first ion implanting, form side wall in described gate electrode both sides.
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The doping type of Semiconductor substrate is p-type ion, and the ionic type of described first ion implanting is N-type,
The ionic type of described second ion implanting is p-type.
The forming method of intrinsic MOS transistor the most according to claim 2, it is characterised in that described
The ion of the first ion implanting is P ion or As ion, and the ion of described second ion implanting is B
Ion or In ion.
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The doping type of Semiconductor substrate is N-type ion, and the ionic type of described first ion implanting is p-type,
The ionic type of described second ion implanting is N-type.
The forming method of intrinsic MOS transistor the most according to claim 4, it is characterised in that described
The ion of the first ion implanting is B ion or In ion, and the ion of described second ion implanting is P
Ion or As ion.
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The doping content scope of Semiconductor substrate is 1E16/cm3To 10E16/cm3。
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The dosage of the first ion implanting is 1E15/cm2To 10E15/cm2, energy is 50KeV to 70KeV.
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The dosage of the second ion implanting is 1E15/cm2To 10E15/cm2, energy is 30KeV to 50KeV.
The forming method of intrinsic MOS transistor the most according to claim 1, it is characterised in that described
The dosage that ion implanting is lightly doped is 1E13/cm2To 10E13/cm2, energy is 50KeV to 70KeV.
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