CN102142372B - Preparation method of field blocking type bipolar transistor of insulated gate - Google Patents
Preparation method of field blocking type bipolar transistor of insulated gate Download PDFInfo
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Abstract
The invention relates to a preparation method of a field blocking type bipolar transistor of an insulated gate, which comprises the following steps of: pre-diffusing N+ type semiconductor impurities on a positive surface and a negative surface of an N-type single wafer after the N-type single wafer is cleaned; forming N+ impurity regions through main diffusion and knotting; removing one N+ impurity region as a front surface of a silicon wafer through grinding; polishing the front surface of the silicon wafer to obtain a substrate material; photoetching a field-limiting ring to form a P+ window of the field-limiting ring; performing boron ion injection; forming a window of a source region through photoetching; performing polysilicon deposition and doping after a silicon wafer gate is oxidized; injecting ions in the window of the silicon wafer gate, and forming a P impurity region and an N+ impurity region through diffusion; depositing and refluxing an insulated dielectric layer, photoetching a lead hole and depositing a metal layer to form an emitting electrode and a grid electrode; thinning the N+ impurity region at the back of the silicon wafer through grinding; annealing the N+ impurity region to form a P+ impurity region after the boron ions are injected in the N+ impurity region; and depositing a metal layer to form a collecting electrode. The method has the characteristics of having simplified process flow, achieving low production cost, and being beneficial for realizing the soft turn-off of an IGBT (Insulated Gate Bipolar Translator).
Description
Technical field
The present invention relates to a kind of method of blocking-up type igbt for preparing, belong to technical field of semiconductor device.
Background technology
Because using the ratio of igbt (IGBT) in the consumption electronic products such as electromagnetic oven, frequency-conversion domestic electric appliances, digital camera constantly increases and consumption electronic product complete machine output tremendous influence; IGBT has become the newly emerging force in the power device family; And a blocking-up type igbt (FS-IGBT) is because low switch loss and on-state voltage drop are compatible; High short-circuit capacity, a series of outstanding performances such as easy parallel connection, range of application constantly enlarges.See Fig. 1, shown in 2, for field blocking-up type igbt, because N+stop layer is a barrier layer, its concentration is far above substrate concentration N-impurity range, so electric field will end at the N+ impurity range, its Electric Field Distribution is trapezoidal.And non-punch igbt (NPT IGBT) is not because there is a barrier layer; Its electric field ends at the edge that the N-impurity range exhausts fully; Its Electric Field Distribution is a triangle, and trapezoidal electric field is with respect to the triangle electric field, identical withstand voltage down; Thickness can be thinner, so the on-state voltage drop of FS-IGBT is lower.The N+ impurity concentration also directly influences the hangover electric current of FS-IGBT, dynamic properties such as switching loss with distributing.Conventional in the fabricating yard during field barrier layer of blocking-up type igbt; Generally be that N type impurity is injected with the superenergy ion implantor in the silicon chip back side; This injection energy generally all requires greater than 300KeV; But not the superenergy ion implantor injects energy generally at 20KeV～200KeV, carries out impurity activation and the higher field barrier layer N+ impurity range of knot formation concentration with laser annealing then.Because the silicon chip back process has arrived the technological process coda, the moulding of silicon chip front device architecture, the follow-up elevated temperature heat of can't carrying out again spreads; And a barrier layer needs certain degree of depth; So can only use laser annealing, but these two equipment of needed extrahigh energy ion implantor of back process and laser annealing stove are all very expensive, the operation of thin slice technology is also very complicated; Fragment rate is very high, causes the integrated artistic process cost high.
Summary of the invention
The purpose of this invention is to provide a kind of method of blocking-up type igbt for preparing, can simplify technological process, reduce manufacturing cost, and the linear graded junction that utilizes High temperature diffusion to form, help realizing the soft shutoff of IGBT.
The present invention is that the technical scheme that achieves the above object is: a kind of method of blocking-up type igbt for preparing is characterized in that: may further comprise the steps,
(1), substrate preparation: to thickness after the N-type single-chip of 100-1000 μ m cleans; Prediffusion concentration is higher than the N+ N-type semiconductor N impurity of N-single-chip on positive and negative two surfaces of N-type single-chip; Under 1100-1300 ℃ of temperature; Carry out the main diffusion of the N+ type impurity of 100-400h, the knot degree of depth forms the N+ impurity range to 10-300 μ m, and one of them N+ impurity range and positive as silicon chip is removed in grinding; Polished silicon slice is positive, makes as the N+ impurity range of place blocking region and the backing material of N-impurity range;
(2), photoetching field limiting ring and boron ion inject: carry out oxidation in the silicon chip front and form field oxide; Apply photoresist, make public, development, etching, form field limiting ring P+ window; Carry out boron ion implantation high temperature diffusion knot again, form the P impurity range at conducting channel place;
(3), photoetching active area: at silicon chip front surface coated photoresist, make public, development, etching, be formed with the source region window;
(4), gate oxidation: silicon chip is carried out clean, remove the field oxide in the active area, and silicon chip is carried out oxidation formation gate oxide;
(5), polysilicon deposit and doping: deposit polysilicon layer on gate oxide, and polysilicon layer carried out ion doping;
(6), photoetching polysilicon gate window: at polysilicon layer surface-coated photoresist, make public, development, etching form the polysilicon gate window;
(7), ion injects and diffusion: in boron ion implanted polysilicon grid window, High temperature diffusion forms the P impurity range, again arsenic ion is injected into the polysilicon gate window, activated at diffuse to form the N+ impurity range;
(8), sidewall protection wall deposit and etching: at the silicon dioxide layer of polysilicon layer surface deposition
; Carry out dry etching then, form polysilicon gate two side protection wall;
(9), insulating medium layer deposit and backflow:, then insulating medium layer is carried out reflow treatment at the positive deposit insulating medium layer of silicon chip;
(10), fairlead photoetching and corrosion: the fairlead that forms emitter and grid in silicon chip front surface coated photoresist, photoetching, development, etching;
(11), metal level deposit and passivation layer deposit and photoetching: to positive sputter of silicon chip or evaporated metal layer; Form emitter and grid through the photoetching metal level; And at the positive deposit passivation layer of silicon chip, and to the passivation layer photoetching and etch emitter and grid draw window;
(12), back side ion injects and annealing: the N+ impurity range mill at the silicon chip back side is subdued be as thin as 5-50 μ m, the boron ion is injected the silicon chip back side, process annealing forms the P+ impurity range;
(13), metal layer on back deposit:, make a blocking-up type igbt to silicon chip back spatter Ti or Ni or Ag formation collector electrode.
The present invention adopts N-type single-chip and forms the N+ impurity range through impurity expansion in advance, High temperature diffusion, knot, and it is positive as silicon chip to grind one of them surperficial N+ impurity range of removal, behind silicon wafer polishing; Make backing material with N-impurity range and N+ impurity range; And the N+ impurity range is transistorized barrier layer district, and the present invention makes a fault zone earlier, promptly forms P impurity range and N+ impurity range on N-impurity range surface in the silicon chip front again; And through insulating medium layer deposit, backflow and fairlead photoetching and corrosion back formation emitter and grid; N+ impurity range to silicon chip back is thinned to 5-50 μ m again, at last the silicon chip back side is got into the boron ion and injects and thermal annealing, forms the P+ impurity range; And, make a blocking-up type igbt through metal deposit formation collector electrode.The present invention need not at the silicon chip back side to make a barrier layer through superenergy ion injection and laser annealing; Replaced expensive laser annealing with common low temperature annealing process; Simplify technological process, reduced fragment rate, rate of finished products obviously improves; The machinery equipment of routine capable of using can be accomplished the making of high-performance FS-IGBT, has saved production cost greatly.The backing material that the present invention utilizes High temperature diffusion to prepare N-impurity range and N+ impurity range makes the place barrier layer earlier; Carry out the making of the positive operation of silicon chip again; At last the boron ion being injected into silicon chip back side formation P+ impurity range through ion implantor gets final product; The linear graded junction that therefore can utilize High temperature diffusion to form helps realizing the soft shutoff of IGBT more.
Description of drawings
Below in conjunction with accompanying drawing embodiments of the invention are done further to describe in detail.
Fig. 1 is the structural representation of conventional blocking-up type igbt.
Fig. 2 is a distribution map of the electric field of blocking-up type igbt.
Fig. 3 is a flow chart of the present invention.
Embodiment
See shown in Figure 3ly, a method for preparing blocking-up type igbt of the present invention may further comprise the steps:
(1), substrate preparation: after the N-type single-chip of 100-1000 μ m cleaned, this N-type single-chip resistivity was at 10-300 Ω cm to thickness, and elder generation's prediffusion concentration on positive and negative two surfaces of N-type single-chip is higher than the N+ N-type semiconductor N impurity of N-single-chip; Available phosphorus source is expanded in advance, under 1100-1300 ℃ of temperature, carries out the N+ type impurity main diffusion of 100-400h again; The knot degree of depth forms the N+ impurity range to 10-300 μ m, in the main diffusion of N+ type impurity of the present invention, and can be under 1150-1250 ℃ of temperature; Carry out the N+ type diffusion of impurities of 150-200h, the knot degree of depth forms the N+ impurity range to 50-200 μ m, and the oxide layer through the two sides that forms in the main diffusion can prevent to pick in the knot process; Extending out in a large number of phosphonium ion; Guaranteeing to meet the requirements of the degree of depth, grind that to remove one of them N+ impurity range also positive as silicon chip, the thickness that keeps the N-impurity range can be decided according to the puncture voltage of the application of FS-IGBT; Polished silicon slice is positive, makes as the N+ impurity range of place blocking region and the backing material of N-impurity range.
(2), photoetching field limiting ring and boron ion inject: carry out oxidation in the silicon chip front and form field oxide, on silicon chip, apply photoresist by common process, make public, development, etching field oxide; Form field limiting ring P+ window, this window width is controlled at 0.5 μ m～30 μ m, carries out boron ion implantation high temperature diffusion knot again; Under 1000～1250 ℃, spread knot; It injects energy at 60～120KeV, and implantation dosage forms the p type impurity district at conducting channel place at 5E12～5E14.
(3), photoetching active area: press common process at silicon chip front surface coated photoresist, make public, development, etching field oxide be formed with the source region window, the active area window width can be controlled in 0.2 μ m～20 μ m.
(4), gate oxidation: silicon chip is carried out clean; Remove the field oxide in the active area; And silicon chip is carried out oxidation form gate oxide; Silicon chip is put into oxidation furnace under 900 ℃～1200 ℃ conditions, carry out gate oxidation; Form gate oxide, the controllable thickness of this gate oxide is built in
(5), polysilicon deposit and doping: silicon chip is put into the deposit stove; Utilize low pressure chemical vapor deposition (LPCVD) deposit polysilicon layer on gate oxide; The THICKNESS CONTROL of polysilicon layer can be confirmed the concrete thickness of polysilicon layer according to the designing requirement of device in that
its thickness also can be controlled in
; And polysilicon layer carried out ion doping; Use the POCL3 deposit; Silicon chip is put into diffusion furnace, under 850 ℃～1000 ℃ temperature, polysilicon layer is carried out ion doping and form conductive layer.
(6), photoetching polysilicon gate window: press common process at polysilicon layer surface-coated photoresist, make public, development, etch polysilicon layer, form the polysilicon gate window;
(7), ion injects and diffusion: the boron ion is injected in the polysilicon gate window through ion implantor, and it injects energy at 60～120KeV, and implantation dosage is at 1E12～8E14/cm
2, under 1000～1250 ℃ high temperature, diffuse to form the P impurity range, again arsenic ion is injected into the polysilicon gate window, it injects energy at 30-80KeV, and implantation dosage is at 1E15～1E16/cm
2, 950～1100 ℃ activated at and diffusion, form the N+ impurity range again.
(8), sidewall protection wall deposit and etching: at the silicon dioxide layer of polysilicon layer surface deposition
; Carry out the dry etching silicon dioxide layer then, form polysilicon gate two side protection wall;
(9), insulating medium layer deposit and backflow: silicon chip is put into the deposit stove; With plasma-reinforced chemical vapour deposition (PECVD); At the positive deposit insulating medium layer of silicon chip; This insulating medium layer adopts conventional phosphorosilicate glass or boron-phosphorosilicate glass, makes the dielectric laminar surface comparatively smooth when reaching reflow treatment, preferably selects boron-phosphorosilicate glass for use; The dielectric layer thickness passes through the control to the dielectric layer thickness at
; Can guarantee to stop the ability of movable charge pickup, can guarantee the accuracy of fairlead etching again, then insulating medium layer carried out reflow treatment.
(11), fairlead photoetching and corrosion: press common process at silicon chip front surface coated photoresist, photoetching, development, etching insulating medium layer, form the fairlead of emitter and the fairlead of grid.
(11), the deposit of front metal layer and passivation layer deposit and photoetching: to positive sputter of silicon chip or evaporated metal layer; Form emitter and grid through the photoetching metal level; At the positive deposit passivation layer of silicon chip, at the positive deposit passivation layer of silicon chip, the thickness of this passivation layer is at 1～5 μ m with the plasma-reinforced chemical vapour deposition again; Can protect device to avoid moisture and contamination as passivation layer through silicon nitride layer; And to passivation layer carry out photoetching and etch emitter and grid draw window, the place of promptly emitter and grid being drawn is carved and is opened, and is convenient to follow-up routing encapsulation.
(12), back side ion injects and annealing: the N+ impurity range mill at the silicon chip back side is subdued be as thin as 5-50 μ m; Concrete thickness needs finally to confirm according to factors such as production line actual conditions and device property, stability; At 10 μ, 15 μ, 20 μ, 25 μ, 3 μ, 5,40 μ, 45 μ m etc. inject the silicon chip back side with the boron ion like the thickness of N+ impurity range; It injects energy at 30～200KeV, and implantation dosage is at 1E13～1E16/cm
2, process annealing forms the P+ impurity range, can under 400～800 ℃ temperature, anneal, and promptly forms collector area.
(13), metal layer on back deposit: to silicon chip back spatter Ti or Ni or Ag, form collector electrode, make a blocking-up type igbt.
Claims (2)
1. one kind prepares a method of blocking-up type igbt, it is characterized in that: may further comprise the steps,
(1), substrate preparation: to thickness after the N-type monocrystalline silicon piece of 100-1000 μ m cleans; Prediffusion concentration is higher than the N+ N-type semiconductor N impurity of N-type monocrystalline silicon piece on positive and negative two surfaces of N-type monocrystalline silicon piece; Under 1100-1300 ℃ of temperature; Carry out the main diffusion of the N+ type impurity of 100-400h, the knot degree of depth forms the N+ impurity range to 10-300 μ m, and one of them N+ impurity range and positive as silicon chip is removed in grinding; Polished silicon slice is positive, makes as the N+ impurity range of place blocking region and the backing material of N-impurity range;
(2), photoetching field limiting ring and boron ion inject: carry out oxidation in the silicon chip front and form field oxide; Apply photoresist, make public, development, etching, form field limiting ring P+ window; Carry out boron ion implantation high temperature diffusion knot again, form the P impurity range at conducting channel place;
(3), photoetching active area: at silicon chip front surface coated photoresist, make public, development, etching, be formed with the source region window;
(4), gate oxidation: silicon chip is carried out clean, remove the field oxide in the active area, and silicon chip is carried out oxidation formation gate oxide;
(5), polysilicon deposit and doping: deposit polysilicon layer on gate oxide, and polysilicon layer carried out ion doping;
(6), photoetching polysilicon gate window: at polysilicon layer surface-coated photoresist, make public, development, etching form the polysilicon gate window;
(7), ion injects and diffusion: in boron ion implanted polysilicon grid window, High temperature diffusion forms the P impurity range, again arsenic ion is injected into the polysilicon gate window, activated at diffuse to form the N+ impurity range;
(8), sidewall protection wall deposit and etching: at the silicon dioxide layer of polysilicon layer surface deposition
; Carry out dry etching then, form polysilicon gate two side protection wall;
(9), insulating medium layer deposit and backflow:, then insulating medium layer is carried out reflow treatment at the positive deposit insulating medium layer of silicon chip;
(10), fairlead photoetching and corrosion: the fairlead that forms emitter and grid in silicon chip front surface coated photoresist, photoetching, development, etching;
(11), metal level deposit and passivation layer deposit and photoetching: to positive sputter of silicon chip or evaporated metal layer; Form emitter and grid through the photoetching metal level; And at the positive deposit passivation layer of silicon chip, and to the passivation layer photoetching and etch emitter and grid draw window;
(12), back side ion injects and annealing: the N+ impurity range mill at the silicon chip back side is subdued be as thin as 5-50 μ m, the boron ion is injected the silicon chip back side, process annealing forms the P+ impurity range;
(13), metal layer on back deposit:, make a blocking-up type igbt to silicon chip back spatter Ti or Ni or Ag formation collector electrode.
2. according to the said method of blocking-up type igbt for preparing of claim 1; It is characterized in that: above-mentioned (1) step under 1150-1250 ℃ of temperature; Carry out the N+ type diffusion of impurities of 150-200h, the knot degree of depth is to 50-200 μ m formation N+ impurity range.
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| CN102931081B (en) * | 2011-08-12 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for semiconductor device with field barrier layer |
| CN102290436B (en) * | 2011-09-15 | 2016-08-03 | 江苏宏微科技有限公司 | Novel structure for back side of IGBT and preparation method thereof |
| CN102420133B (en) * | 2011-09-30 | 2013-07-24 | 上海华虹Nec电子有限公司 | Method for manufacturing insulated gate bipolar transistor (IGBT) device |
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| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
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| CN103117302A (en) * | 2013-03-06 | 2013-05-22 | 江苏物联网研究发展中心 | Back structure of FS type IGBT device |
| CN104252103A (en) * | 2013-06-25 | 2014-12-31 | 无锡华润上华科技有限公司 | Removal method of residual photoresist after photoetching reworking |
| CN104347402A (en) * | 2013-07-30 | 2015-02-11 | 无锡华润上华半导体有限公司 | Manufacturing method of insulated gate bipolar transistor |
| CN104347403B (en) * | 2013-07-31 | 2017-11-14 | 无锡华润上华科技有限公司 | A kind of manufacture method of insulated gate bipolar transistor |
| CN103594356B (en) * | 2013-08-30 | 2017-10-17 | 国家电网公司 | A kind of manufacture method of field stop type IGBT device |
| CN103489776B (en) * | 2013-09-18 | 2016-06-01 | 中国东方电气集团有限公司 | A kind of realize a processing method for cut-off type insulated gate bipolar transistor npn npn |
| CN104517835A (en) * | 2013-09-26 | 2015-04-15 | 无锡华润上华半导体有限公司 | Back surface technology of field cut-off type insulated gate bipolar transistor |
| CN104716028B (en) * | 2013-12-12 | 2018-10-19 | 江苏宏微科技股份有限公司 | The trench gate structure and preparation method thereof of groove-shaped igbt |
| CN105551944B (en) * | 2015-12-25 | 2018-09-04 | 深圳深爱半导体股份有限公司 | The manufacturing method of power transistor |
| CN113410135B (en) * | 2021-06-15 | 2023-06-30 | 西安微电子技术研究所 | Manufacturing method of anti-radiation junction field effect transistor |
| CN118737827B (en) * | 2024-09-04 | 2024-11-22 | 深圳市冠禹半导体有限公司 | A method for preparing a cell structure, a cell structure and an IGBT device |
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