CN102142268B - Control device and related control method - Google Patents

Abstract

The invention relates to a control device, comprising: a first delay circuit having a first delay amount for selectively delaying one of a first input clock and a second input clock according to a selection signal to generate an output clock to a storage device; a second delay circuit for delaying the selection signal by a second delay amount to generate a second delayed selection signal; a first control circuit for selectively accessing the storage device according to the second delay selection signal; a third delay circuit for delaying the selection signal by a third delay amount to generate a third delayed selection signal; and a second control circuit for selectively accessing the storage device according to the third delay selection signal. The invention also relates to a control method. The invention not only has faster response time, but also overcomes the problem of clock burst signal, and improves the speed of a control circuit accessing a single-port first-in first-out memory.

Description

Control device and related control method

technical field

The present invention relates to the technical field of a control device and its related control method, more specifically, to a control device of a single-port FIFO memory and its related control method.

Background technique

In an access system, a storage device, such as a single-port first-in-first-out (One-port FIFO) memory, is usually assigned to control circuits with different clock characteristics (such as different clock frequencies or duty cycles) for storage. take action. Taking the single-port FIFO memory as an example, an I/O port of the single-port FIFO memory must often be switched between different control circuits. However, in the switching process, in order to avoid the generation of clock glitch, the firmware of the traditional access system will implement a protection mechanism to ensure that the glitch will not be generated. Furthermore, when a first control circuit with a first clock is accessing the single-port FIFO memory, the firmware intends to switch the circuit that accesses (uses) the single-port FIFO memory, and will A circuit for accessing (using) the single-port FIFO memory is switched from a first control circuit to a second control circuit. Wherein the first control circuit has a first control clock and the second control circuit has a second control clock, at this time, the firmware of the conventional access system will switch the first control clock input to the single-port FIFO memory is the second control clock. Then, the firmware counts a specific delay time before controlling the second control circuit to start accessing the single-port FIFO memory. In other words, the specific delay time must be long enough to ensure that the first control clock received by the single-port FIFO memory is successfully switched to the second control clock before the second control circuit starts to access the single port. Port FIFO memory to avoid clock bursts. However, when the clock frequencies of the first control clock and the second control clock are high, their cycle time is relatively reduced, so the time required for switching from the first control clock to the second control clock is also reduced up. However, if the specific delay time remains unchanged at this time, the specific delay time will be too long to cause unnecessary waste of time, thereby slowing down the speed of a control circuit accessing a single-port FIFO memory. . Therefore, how to adaptively adjust the specific delay time to increase the speed of a control circuit to access a single-port FIFO memory has become an urgent problem to be solved for an access system.

Contents of the invention

The technical problem to be solved by the present invention is to provide a single-port first-in-first-out memory control device and its related control method to solve the problems faced by the prior art.

One of the technical solutions adopted by the present invention to solve the technical problem is to construct a control device. The control device includes a first delay circuit, a second delay circuit, a first control circuit, a third delay circuit and a second control circuit. The first delay circuit has a first delay amount and is used for selectively delaying one of a first input clock and a second input clock according to a selection signal to generate an output clock to a storage device. The second delay circuit is coupled to the first delay circuit and used to delay the selection signal by a second delay amount to generate a second delayed selection signal. The first control circuit operates on the first input clock and is coupled to the second delay circuit for selectively accessing the storage device according to the second delay selection signal. The third delay circuit is coupled to the first delay circuit and used to delay the selection signal by a third delay amount to generate a third delayed selection signal. The second control circuit operates on the second input clock and is coupled to the third delay circuit for selectively accessing the storage device according to the third delay selection signal.

In the control device of the present invention, when the second delay selection signal allows the first control circuit to access the storage device, the third delay selection signal does not allow the second control circuit to access the storage device.

In the control device of the present invention, at least one of the second delay amount and the third delay amount is greater than the first delay amount.

The control device of the present invention, wherein the second delay circuit includes:

A plurality of first specific delay units are connected in series to respectively provide a delay amount, and the plurality of first specific delay units include at least one first delay unit and a second delay unit, wherein the first delay unit operates on the under the first input clock, and the second delay unit operates under the second input clock.

In the control device of the present invention, the sum of the delays of the first delay unit and the second delay unit is substantially equal to the second delay.

The control device of the present invention, wherein the third delay circuit includes:

A plurality of second specific delay units are connected in series to respectively provide a delay amount, and the plurality of second specific delay units include at least one third delay unit and a fourth delay unit, wherein the third delay unit operates on the under the first input clock, and the fourth delay unit operates under the second input clock; and

An inverter is serially connected to a delay unit among the plurality of second specific delay units.

In the control device of the present invention, the sum of the delays of the third delay unit and the fourth delay unit is substantially equal to the third delay.

The control device of the present invention further includes:

a selection circuit, coupled to the first delay circuit, the second delay circuit, the third delay circuit, the first control circuit, and the second control circuit, used to generate a first delay circuit based on the first control circuit A control signal and a second control signal generated by the second control circuit are used to generate the selection signal to the first delay circuit, the second delay circuit and the third delay circuit.

In the control device of the present invention, the second delay circuit, the third delay circuit and the selection circuit are pure hardware circuits.

The control device of the present invention, wherein the selection circuit includes:

A first trigger (toggle) circuit, controlled by the first input clock, is used to trigger a first trigger output signal according to the first control signal;

A second trigger circuit, controlled by the second input clock, is used to trigger a second trigger output signal according to the second control signal; and

A logic gate, coupled to the first trigger circuit and the second trigger circuit, is used to generate the selection signal according to the first trigger output signal and the second trigger output signal.

In the control device of the present invention, the logic gate is an exclusive OR gate.

The second technical solution adopted by the present invention to solve the technical problem is to construct a control method. The control method includes the following steps: selectively delaying one of a first input clock and a second input clock according to a selection signal to generate an output clock to a storage device; delaying the selection signal by a second delay amount to generate a second delay selection signal; instruct a first control circuit to selectively access the storage device according to the second delay selection signal; delay the selection signal by a third delay amount to generate a third delay selection signal; and instruct a second control circuit to selectively access the storage device according to the third delay selection signal.

In the control method of the present invention, when the second delay selection signal indicates that the first control circuit allows access to the storage device, the third delay selection signal indicates that the second control circuit does not allow access to the storage device.

In the control method of the present invention, at least one of the second delay amount and the third delay amount is greater than the first delay amount.

The control method of the present invention further includes:

The selection signal is generated according to a first control signal and a second control signal.

In the control method of the present invention, the step of generating the selection signal according to the first control signal and the second control signal includes:

triggering a first trigger output signal according to the first control signal;

triggering a second trigger output signal according to the second control signal; and

The selection signal is generated according to the first trigger output signal and the second trigger output signal.

Implementing the control device and the control method thereof of the present invention has the following beneficial effects: the present invention can be implemented in the form of a pure hardware circuit without firmware, not only has a faster response time (that is, clock switching time), At the same time, the problem of clock burst signal is overcome, and the speed of accessing a single-port FIFO memory by a control circuit is improved.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

Fig. 1 is a schematic diagram of an embodiment of a control device of the present invention;

2 is a timing diagram of a selection signal, a first input clock, a second input clock and multiple signals of a first delay circuit of the present invention;

Fig. 3 is a waveform timing diagram of a first control signal, a second control signal, a first trigger output signal, a second trigger output signal and the selection signal of the control device of the present invention;

4 is a schematic diagram of another embodiment of a first delay circuit of the control device of the present invention;

Fig. 5 is a flowchart of an embodiment of a control method according to the present invention.

[Description of main component symbols]

100 controls

101, 201 The first delay circuit

102 Second delay circuit

103 first control circuit

104 The third delay circuit

105 Second control circuit

106 selection circuit

107 storage device

101a, 101b, 101c, 101d, 201a, 201b, 201c, 201d AND gate

101e, 101f, 101g, 101h, 201e, 201f, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b D-type flip-flops

101i, 201g OR gate

101j Inverter

1022 first delay unit

1024 second delay unit

1042 third delay unit

1044 fourth delay unit

1062 first trigger circuit

1064 second trigger circuit

1066 logic gates

Detailed ways

Certain terms are used in the specification and subsequent claims to refer to particular components. It should be understood by those skilled in the art that hardware manufacturers may refer to the same component by different terms. This specification and subsequent patent applications do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect means of electrical connection. Therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device. second device, or indirectly electrically connected to the second device through other devices or connection means.

Please refer to Figure 1. FIG. 1 shows a schematic diagram of an embodiment of a control device 100 according to the present invention. The control device 100 includes a first delay circuit 101 , a second delay circuit 102 , a first control circuit 103 , a third delay circuit 104 , a second control circuit 105 and a selection circuit 106 .

The first delay circuit 101 has a first delay amount D1 for selectively delaying one of a first input clock C1 and a second input clock C2 according to a selection signal Ss to generate an output clock Cout to a storage device 107 .

The second delay circuit 102 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a second delay amount D2 to generate a second delayed selection signal Ssd2. The first control circuit 102 operates on the first input clock C1 and is coupled to the second delay circuit 102 for selectively accessing the storage device 107 according to the second delay selection signal Ssd2.

The third delay circuit 104 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a third delay amount D3 to generate a third delayed selection signal Ssd3. The second control circuit 105 operates on the second input clock C2 and is coupled to the third delay circuit 104 for selectively accessing the storage device 107 according to the third delay selection signal Ssd3.

The selection circuit 106 is coupled to the first delay circuit 101, the second delay circuit 102, the third delay circuit 104, the first control circuit 103 and the second control circuit 105, and is used to generate a first The control signal Sc1 and a second control signal Sc2 generated by the second control circuit 105 generate the selection signal Ss to the first delay circuit 101 , the second delay circuit 102 and the third delay circuit 104 . In this embodiment, the storage device 107 is implemented as a One-port FIFO memory, but it is not a limitation of the present invention.

The first delay circuit 101 includes AND gates (And Gate) 101a, 101b, 101c, 101d, D-type flip-flops (D Flip-Flop) 101e, 101f, 101g, 101h, an OR gate (Or Gate) 101i and a Inverter 101j. The D-type flip-flops 101e, 101f are connected in series to provide a delay amount 1, 5Ta according to the first input clock C1, where Ta is the period of the first input clock C1. The D-type flip-flops 101g, 101h are connected in series to provide a delay amount of 1, 5Tb according to the second input clock C2, wherein Tb is a period of the second input clock C2. An input terminal N1 of the AND gate 101a is used to receive the selection signal Ss, and an output terminal N2 is coupled to an input terminal of the D-type flip-flop 101e. A non-inverting output terminal N3 of the D-type flip-flop 101f is coupled to an input terminal of the AND gate 101c. Another input terminal N4 of the AND gate 101c receives the first input clock C1. In addition, the inverter 101j is coupled between the input terminal N1 and an input terminal N5 of the AND gate 101b. Another input terminal N6 of the AND gate 101b is coupled to an inverting output terminal of the D-type flip-flop 101f, and an output terminal N7 of the AND gate 101b is coupled to an input terminal of the D-type flip-flop 101g. A non-inverting output terminal N8 of the D-type flip-flop 101h is coupled to an input terminal of the AND gate 101d. The other input terminal N9 of the AND gate 101d receives the second input clock C2. The respective output terminals N10 and N11 of the AND gate 101c and the AND gate 101d are respectively coupled to two input terminals of an OR gate (Or Gate) 101i. The output terminal N12 of the OR gate 101i is used to output the output clock Cout. Please note that for the detailed connection relationship of the first delay circuit 101 , please refer to FIG. 1 of the present invention, which will not be repeated here.

Due to the structure of the first delay circuit 101, the first control signal Sc1/second control signal Sc2 is generated from the first control circuit 103/second control circuit 105 to indicate the desire to access (use) the storage device 107 until the storage device Until the 107 receives the changed output clock Cout, a delay time of 1, 5Ta+1, 5Tb will be required in total. Since a clock burst signal (Glitch) is often generated when the clock is switched, in order to prevent the storage device 107 from receiving a clock signal with a clock burst signal and malfunctioning, the first delay circuit 101 is used to delay for a period of time (for example, 1, 5Ta +1, 5Tb), input the storage device 107 after the clock signal after the clock change is stable. The first delay circuit 101 shown in FIG. 1 is only an exemplary embodiment, rather than a limitation of the present invention. Those skilled in the art should change the D-type delay circuit 101 in the first delay circuit 101 under the teaching of the present invention. The number of flip-flops, and realize the first delay circuit 101 in various variations, for example, the first delay circuit 101 that can produce 2, 5Ta+1, 5Tb or the first delay circuit 101 that can produce 2, 5Ta+2, 5Tb, etc. .

The second delay circuit 102 includes a plurality of first specific delay units connected in series to provide a delay value respectively. In this embodiment, the plurality of first specific delay units include a first delay unit 1022 and a second delay unit 1024, wherein the first delay unit 1022 operates under the second input clock C2, and the second delay unit 1024 operates under the first input clock C1. The first delay unit 1022 includes D-type flip-flops 1022a and 1022b, which are connected in series to provide a delay value of 2Tb. The second delay unit 1024 includes D-type flip-flops 1024a, 1024b, which are connected in series to provide a delay value 2Ta. Please note that the serial connection sequence of the D-type flip-flops 1022a, 1022b, 1024a, and 1024b in this embodiment is for illustrative purposes only, and is not a limitation of the present invention. The serial connection sequence can be adjusted arbitrarily. In this embodiment, the sum of the delays of the first delay unit 1022 and the second delay unit 1024 is substantially equal to the second delay D2, that is, 2Ta+2Tb=D2. In other words, the second delay circuit 102 is used to provide a delay amount of 2Ta+2Tb to the selection signal Ss, and the second delayed selection signal Ssd2 generated after delay is output to an output terminal N13 of the D-type flip-flop 1024b.

On the other hand, the third delay circuit 104 includes a plurality of second specific delay units connected in series to provide a delay amount respectively. In this embodiment, the plurality of second specific delay units include a third delay unit 1042 and a fourth delay unit 1044, wherein the third delay unit 1042 operates under the first input clock C1, and the fourth delay unit 1044 operates under the second input clock C2. The third delay unit 1042 includes D-type flip-flops 1042a, 1042b, which are connected in series to provide a delay value 2Ta. The fourth delay unit 1044 includes D-type flip-flops 1044a, 1044b connected in series to provide a delay of 2Tb. Please note that the serial connection sequence of the D-type flip-flops 1042a, 1042b, 1044a, and 1044b in this embodiment is for illustration only, and not a limitation of the present invention. The serial connection sequence can be adjusted arbitrarily. In addition, the third delay circuit 104 of the present invention further includes an inverter 1046 coupled between the input terminal N1 and an input terminal N14 of the D-type flip-flop 1042a to generate an inverted selection signal Ssb according to the selection signal Ss . In this embodiment, the sum of the delays of the third delay unit 1042 and the fourth delay unit 1044 is substantially equal to the third delay D3, that is, 2Ta+2Tb=D3. In other words, the third delay circuit 104 is used to provide a delay amount of 2Ta+2Tb to the inverted selection signal Ssb, and output the delayed third delayed selection signal Ssd3 to an output terminal N15 of the D-type flip-flop 1044b. . Please note that the present invention does not limit the coupling manner of the inverter 1046, in other words, as long as it is connected in series with the third delay unit 1042 and the fourth delay unit 1044, it is within the scope of the present invention. For example, the inverter 1046 can also be coupled between the fourth delay unit 1044 and the second control circuit 105 .

In addition, the selection circuit 106 of this embodiment includes a first toggle circuit 1062 , a second toggle circuit 1064 and a logic gate 1066 . The first trigger circuit 1062 operates under the first input clock C1 and is used for triggering a first trigger output signal St1 according to the first control signal Sc1. The second trigger circuit 1064 operates under the second input clock Sc2 and is used to trigger a second trigger output signal St2 according to the second control signal Sc2. The logic gate 1066 is coupled to the first trigger circuit 1062 and the second trigger circuit 1064 for generating the selection signal Ss according to the first trigger output signal St1 and the second trigger output signal St2. In this embodiment, the logic gate 1066 is implemented as an Exclusive OR gate.

Please refer to Figure 2. 2 shows the selection signal Ss, the first input clock C1, the second input clock C2, the signal S1, the signal S2, the signal S3, the signal S4, the signal S5, the signal S6, the signal S7, The timing diagram of the signal S8 and the signal S9, wherein the signal S1 is the signal of the output terminal N2 of the AND gate 101a, the signal S2 is the signal of an output terminal N16 of the D-type flip-flop 101e, and the signal S3 is the signal of the D-type flip-flop 101f The signal of the output terminal N3 and the signal S4 are the signals of the inverting output terminal N17 of the D-type flip-flop 101f, the signal S5 is the signal of the output terminal N7 of the AND gate 101b, and the signal S6 is an output terminal of the D-type flip-flop 101g The signal of N18, the signal S7 is the signal of the output terminal N8 of the D-type flip-flop 101h, the signal S8 is the signal of the inverting output terminal N19 of the D-type flip-flop 101h, and the signal S9 is the signal of the output terminal N5 of the inverter 101j signal.

In order to further describe the spirit of the present invention, this embodiment assumes that the first input clock C1 is synchronized with the second input clock C2. When the selection signal Ss is switched from a low voltage level to a high voltage level at time T1, the signal S9 and the signal S5 are also switched from the high voltage level to the low voltage level. Since the D-type flip-flop 101g is a rising-edge triggered D-type flip-flop, the second input clock C2 will trigger the D-type flip-flop 101g at time T2 so that the signal S6 switches from the high voltage level to the low voltage level. voltage level. Then, since the D-type flip-flop 101h is a falling-edge triggered D-type flip-flop, the second input clock C2 will trigger the D-type flip-flop 101h at time T3 so that the signal S7 switches from the high voltage level to the low voltage level. At the same time, the signal S8 of the D-type flip-flop 101h is switched from the low voltage level to the high voltage level, thereby making the signal S1 switch from the low voltage level to the high voltage level. Similarly, the first input clock C1 will trigger the D-type flip-flop 101e (the D-type flip-flop 101e is a rising-edge triggered D-type flip-flop) at time T4 so that the signal S2 switches from the low voltage level to the high voltage level. Then, the first input clock C1 triggers the D-type flip-flop 101f (the D-type flip-flop 101f is a falling-edge triggered D-type flip-flop) at time T5 so that the signal S3 switches from the low voltage level to the High voltage level. Therefore, after the time T5, the output signal of the AND gate 101d will be the low voltage level, and the output signal of the AND gate 101c will be the first input clock C1. In other words, after the time T5, the output clock Cout (that is, the output terminal of the OR gate 101i) is switched from the second input clock C2 to the first input clock C1.

On the other hand, please refer to FIG. 2 again, when the selection signal Ss is switched from the high voltage level to the low voltage level at time T6 (that is, the output clock Cout is to be switched from the first input clock C1 to the second input clock C2), the signal S1 will also switch from the high voltage level to the low voltage level. Since the D-type flip-flop 101e is a rising-edge triggered D-type flip-flop, the first input clock C1 will trigger the D-type flip-flop 101e at time T7 so that the signal S2 switches from the high voltage level to the low voltage level. voltage level. Then, since the D-type flip-flop 101f is a falling-edge triggered D-type flip-flop, the first input clock C1 will trigger the D-type flip-flop 101f at time T8 so that the signal S3 switches from the high voltage level to the low voltage level. At the same time, the signal S4 of the D-type flip-flop 101f is switched from the low voltage level to the high voltage level, thereby making the signal S5 switch from the low voltage level to the high voltage level. Similarly, the second input clock C2 triggers the D-type flip-flop 101g at time T9 to switch the signal S6 from the low voltage level to the high voltage level. Then, the second input clock C2 triggers the D-type flip-flop 101h at time T10 to make the signal S7 switch from the low voltage level to the high voltage level. Therefore, after the time T10, the output signal of the AND gate 101c will be the low voltage level, and the output signal of the AND gate 101d will be the second input clock C2. In other words, after the time T10, the output clock Cout (that is, the output terminal of the OR gate 101i) is switched from the first input clock C1 to the second input clock C2.

Furthermore, the delay unit formed by the D-type flip-flops 101g and 101h can delay the signal S5 by 1, 5Tb at the longest, and the delay unit formed by the D-type flip-flops 101e and 101f can delay the signal S1 at the longest 1, 5Ta, therefore, the first delay amount D1 of the first delay circuit 101 can have a maximum delay time of 1, 5Ta+1, 5Tb. In other words, when the selection signal Ss is switched from the low voltage level to the high voltage level, the output clock Cout will be switched from the second input clock C2 with a delay time not exceeding 1, 5Ta+1, 5Tb at the longest. is the first input clock C1. Conversely, when the selection signal Ss is switched from the high voltage level to the low voltage level, the delay time of the output clock Cout will not exceed 1, 5Ta+1, 5Tb at the longest, and it will switch from the first input clock C1 to the second Two input clock C2. Therefore, when the selection signal Ss is switched from the low voltage level to the high voltage level, as long as the first control circuit 103 can exceed the delay time (1, 5Ta+1, 5Tb) of the first delay circuit 101 If the storage device 107 accesses, the storage device 107 (that is, the output terminal N12 ) can avoid malfunction caused by the generation of the clock burst signal (Glitch). Please note that those skilled in the art, under the teaching of the present invention, should change the number, type (D-type flip-flop or other types of flip-flops) and triggers of the flip-flops in the first delay circuit 101. mode (rising edge trigger or falling edge trigger) to change the delay time of the first delay circuit 101 .

Therefore, for the selection signal Ss, the second delay circuit 102 of this embodiment provides a delay time of 2Ta+2Tb to generate the second delayed selection signal Ssd2. And the first control circuit 103 will access the storage device 107 according to the second delay selection signal Ssd2. As can be seen from FIG. 1, the D-type flip-flops 1022a, 1022b in the second delay circuit 102 provide a delay time of 2Tb, while the D-type flip-flops 1024a, 1024b provide a delay time of 2Ta, so the second delay circuit 102 provides a delay time of 2Ta+2Tb in total.

On the other hand, for the selection signal Ss, the third delay circuit 104 also provides a delay time of 2Ta+2Tb to generate the third delay selection signal Ssd3. Please note that the present invention is not limited to the above-mentioned embodiments, as long as the delay time provided by the second delay circuit 102 and the third delay circuit 104 is longer than the delay time provided by the first delay circuit 101, the circuit combination is The scope of the present invention is, that is, those who are familiar with this art, under the teaching of the present invention, should change the number, type and trigger mode of the flip-flops in the second delay circuit 102 or the third delay circuit 104 so as to The delay time of the first delay circuit 101 is changed. Therefore, after the first delay amount D1 (that is, 2Ta+2Tb), the second delay selection signal Ssd2 switches from the low voltage level to the high voltage level to allow the first control circuit 103 to access the storage device 107 . Please note that those with ordinary knowledge in this field should be able to understand the corresponding operation of the control device 100 after reading the technical content disclosed above, that is, when the selection signal Ss is switched from a high voltage level to a low voltage level It also has the advantages described above, so it will not be repeated here.

Please note that the second delay circuit 102 , the third delay circuit 104 and the selection circuit 106 of the control device 100 in this embodiment are pure hardware circuits. In other words, in one embodiment, the control device 100 may control the first control circuit 103 or the second control circuit 105 to access the storage device 107 without using firmware. Therefore, when the first control circuit 103 needs to access the storage device 107, the first control circuit 103 generates the first control signal Sc1 to the selection circuit 106 to generate the selection signal Ss. Similarly, when the second control circuit 105 needs to access the storage device 107, the second control circuit 105 generates the second control signal Sc2 to the selection circuit 106 to generate the selection signal Ss. For example, suppose that when the second control circuit 105 is accessing the storage device 107 and the first control circuit 103 wants to access the storage device 107, the first control circuit 103 will first generate the first control signal Sc1 to the first trigger The circuit 1062, wherein the first control signal Sc1 is a pulse signal, as shown in FIG. 3 .

3 is a timing diagram of waveforms of the first control signal Sc1, the second control signal Sc2, the first trigger output signal St1, the second trigger output signal St2 and the selection signal Ss of the control device 100 according to the embodiment of the present invention. When the first control circuit 103 generates the first control signal Sc1 at time To, the first trigger circuit 1062 is triggered by the first control signal Sc1 and switches the first trigger output signal St1 from a low voltage level at time Tx. to a high voltage level. Then, the logic gate 1066 (that is, the XOR gate) generates the selection signal Ss according to the first trigger output signal St1 and the second trigger output signal St2. Since the voltage level of the second trigger output signal St2 is the low voltage level at this time, the logic gate 1066 switches the selection signal Ss from the low voltage level to the high voltage level at time Tb. Next, the first delay circuit 101 performs the operation shown in FIG. 2 to switch the output clock Cout from the second input clock C2 to the first input clock C1. Then, after the first delay amount D1 (ie 2Ta+2Tb), the first control circuit 103 is allowed to access the storage device 107 .

Conversely, when the first control circuit 103 is accessing the storage device 107 and the second control circuit 105 intends to access the storage device 107, the second control circuit 105 will first generate the second control signal Sc2 to the second trigger circuit 1064, The second control signal Sc2 is also a pulse signal, as shown in FIG. 3 . When the second control circuit 105 generates the second control signal Sc2 at the time To', the second trigger circuit 1064 will be triggered by the second control signal Sc2 and change the second trigger output signal St2 from a low voltage level at the time Ty switch to a high voltage level. Since the voltage levels of the first trigger output signal St1 and the second trigger output signal St2 are at the high voltage level at this time, the logic gate 1066 will switch the selection signal Ss from the high voltage level to the low voltage level at time Ty. voltage level. Similarly, the first delay circuit 101 will perform the operation shown in FIG. 2 to switch the output clock Cout from the first input clock C1 to the second input clock C2. Then, after the first delay D1 (ie 2Ta+2Tb), the second control circuit 105 is allowed to access the storage device 107 . Therefore, through the coordinated operation of the first trigger circuit 1062, the second trigger circuit 1064 and the logic gate 1066 in the selection circuit 106, the first control circuit 103 and the second control circuit 105 can be selected without depending on the control of the firmware. to access the storage device 107. Therefore, compared with the traditional storage device access system, the control device 100 of the present invention not only has a faster response time (ie clock switching time), but also overcomes the problem of clock burst signals.

Please refer to Figure 4. FIG. 4 is a schematic diagram of another embodiment of the first delay circuit 101 of the control device 100 of the present invention, and the other embodiment is marked with reference numeral 201 . The first delay circuit 201 includes AND gates 201a, 201b, 201c, 201d, D-type flip-flops 201e, 201f, an OR gate 201g, and an inverter 201h. The D-type flip-flop 101e provides a delay amount of 0, 5Ta' according to a first input clock C1', wherein Ta' is a period of the first input clock C1'. The D-type flip-flop 201f is used to provide a delay amount of 0, 5Tb' according to a second input clock C2', wherein Tb' is a period of the second input clock C2'. An input terminal N1' of the AND gate 201a is used to receive a selection signal Ss', and an output terminal N2' is coupled to an input terminal of the D-type flip-flop 201e. A non-inverting output terminal N3' of the D-type flip-flop 201e is coupled to an input terminal of the AND gate 201c, and the other input terminal N4' of the AND gate 201c receives the first input clock C1'. In addition, the inverter 201h is coupled between the input terminal N1' and an input terminal N5' of the AND gate 201b. Another input terminal N6' of the AND gate 201b is coupled to an inverting output terminal of the D-type flip-flop 201e, and an output terminal N7' of the AND gate 201b is coupled to an input terminal of the D-type flip-flop 201f. A non-inverting output terminal N8' of the D-type flip-flop 201f is coupled to an input terminal of the AND gate 201d. The other input terminal N9' of the AND gate 201d receives the second input clock C2'. The output terminals N10' and N11' of the AND gate 201c and the AND gate 201d are respectively coupled to two input terminals of the OR gate 201g. The output terminal N12' of the OR gate 201g is used to output the output clock Cout'. Referring to the operation of the first delay circuit 101, those skilled in the art should understand that the first delay circuit 201 can have a maximum delay time of 0.5Ta'+0.5Tb'. In other words, when the selection signal Ss' is switched from the low voltage level to the high voltage level, the delay time of the output clock Cout' will not exceed 0.5Ta'+0.5Tb' at the longest from the second The input clock C2' is switched to the first input clock C1'. Conversely, when the selection signal Ss' is switched from the high voltage level to the low voltage level, the output clock Cout' will not exceed the delay time of 0, 5Ta'+0, 5Tb' at the longest, and it will start from the first input clock C1' switches to the second input clock C2'. Therefore, for the embodiment in which the control device 100 is formed by using the first delay circuit 201, when the selection signal Ss' is switched from the low voltage level to the high voltage level, as long as the first control circuit 103 can exceed 0 If the storage device 107 is accessed after the delay time of , 5Ta'+0, 5Tb', the storage device 107 (that is, the output terminal N12) can avoid the problem caused by the clock burst signal (Glitch). In other words, in this embodiment, as long as the second delay amount D2 of the second delay circuit 102 and the third delay amount D3 of the third delay circuit 103 are set to be greater than 0, 5Ta'+0, 5Tb' If it is longer (eg 1Ta'+1Tb'), the generation of clock burst signal can be avoided.

Please refer to Figure 5. FIG. 5 is a flowchart of an embodiment of a control method 500 according to the present invention. In order to illustrate the spirit of the present invention more clearly, the control method 500 is implemented with the control device 100 of the embodiment shown in FIG. 1 , but the provided embodiments are not intended to limit the scope of the present invention. In addition, if substantially the same result can be achieved, it is not necessary to follow the order of the steps in the process shown in Figure 5, and the steps shown in Figure 5 do not have to be performed continuously, that is, other steps can also be inserted therein . The control method 500 includes the following steps:

Step 501: Generate at least one of the first control signal Sc1 and the second control signal Sc2;

Step 502: respectively triggering the first trigger output signal St1 and the second trigger output signal St2 according to the first control signal Sc1 or the second control signal Sc2;

Step 503: Generate a selection signal Ss according to the first trigger output signal St1 and the second trigger output signal St2, and skip to step 504;

Step 504: Delay one of the first input clock C1 and the second input clock C2 by a first delay amount D1 according to the selection signal Ss to generate an output clock Cout to the storage device 107;

Step 505: Delay the selection signal Ss by a second delay amount D2 to generate a second delayed selection signal Ssd2;

Step 506: selectively access the storage device 107 according to the second delay selection signal Ssd2;

Step 507: Delay the selection signal Ss by a third delay amount D3 to generate a third delayed selection signal Ssd3;

Step 508: Selectively access the storage device 107 according to the third delay selection signal Ssd3.

In step 501, when a control circuit in the first control circuit 103 and the second control circuit 105 intends to access the storage device 107, the control circuit will generate a control signal to the first trigger circuit 1062 or the second trigger circuit circuit 1064. For example, when the first control circuit 103 intends to access the storage device 107 , the first control circuit 103 will generate a control signal Sc1 to the first trigger circuit 1062 . When the second control circuit 105 intends to access the storage device 107 , the second control circuit 105 generates a control signal Sc2 to the second trigger circuit 1064 . Then, the trigger circuit triggered by the control signal switches the voltage level of its output signal (the first trigger output signal St1 or the second trigger output signal St2 ) (step 502 ). Then, in step 503 , the logic gate 1066 generates the selection signal Ss according to the first trigger output signal St1 and the second trigger output signal St2 . Correspondingly, the selection signal Ss can indicate which one of the first control circuit 103 or the second control circuit 105 wants to access the storage device 107 . With reference to the description of the operation of the control device 100, the selection signal Ss will pass through three delay circuits (that is, the first delay circuit 101 (step 504), the second delay circuit 102 (step 505) and the third delay circuit 104 (step 507). ) to generate three output signals (that is, the output clock Cout, the second delay selection signal Ssd2 and the third delay selection signal Ssd3), wherein the delay time of the second delay circuit 102 and the third delay circuit 104 (D2, D3) greater than the delay time (D1) of the first delay circuit 101. Next, if the output clock Cout is the first input clock C1, the first control circuit 103 starts to access the storage device 107 according to the instruction of the second delay selection signal Ssd2 (step 506). On the contrary, if the output clock Cout is the second input clock C2, the second control circuit 105 starts to access the storage device 107 according to the instruction of the third delay selection signal Ssd3 (step 508). Please note that the control device 100 generates three output signals (that is, the output clock Cout, the second delay selection signal Ssd2 and the third delay selection signal Ssd3) according to the selection signal Ss, wherein the second delay selection signal Ssd2 is used to indicate the first When the control circuit 103 starts to access the storage device 107 , the third delay selection signal Ssd3 is used to indicate when the second control circuit 105 starts to access the storage device 107 . Under normal operation, when the second delay selection signal Ssd2 instructs the first control circuit 103 to access the storage device 107, the third delay selection signal Ssd3 instructs the second control circuit 105 not to access the storage device 107, and vice versa. Because when the first control circuit 103 or the second control circuit 105 starts to access the storage device 107, the corresponding input clock has been sent to the storage device 107 earlier, so the storage device 107 can avoid the clock burst caused by the question.

To sum up, compared with the traditional storage device access system, the control device 100 and its control method 500 of the present invention can be implemented in a pure hardware circuit without firmware, which not only has faster The response time (that is, the clock switching time), also overcomes the problem of the clock burst signal at the same time.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (11)

1. a control device, is characterized in that, includes:

One first delay circuit, has one first retardation, is used for selecting signal one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device according to one;

One second delay circuit, is coupled to this first delay circuit, is used for to this selection signal delay one second retardation to produce one second the delayed selection culture signal;

One first control circuit, operates in this first input clock and is coupled to this second delay circuit, is used for carrying out this storage device of optionally access according to this second the delayed selection culture signal;

One the 3rd delay circuit, is coupled to this first delay circuit, is used for to this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal; And

One second control circuit, operates in this second input clock and is coupled to the 3rd delay circuit, is used for carrying out this storage device of optionally access according to the 3rd the delayed selection culture signal;

Further, this second retardation, the 3rd retardation are greater than this first retardation; This first retardation, the second retardation and the 3rd retardation are all relevant with the clock period of the second input clock to the clock period of the first input clock.

2. control device according to claim 1, is characterized in that, wherein, when this second the delayed selection culture signal allows this this storage device of first control circuit access, the 3rd the delayed selection culture signal does not allow this this storage device of second control circuit access.

3. control device according to claim 1, is characterized in that, wherein this second delay circuit includes:

Multiple the first specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the first specific delays unit includes at least one the first delay cell and one second delay cell, wherein this first delay cell operates under this first input clock, and this second delay cell operates under this second input clock.

4. control device according to claim 3, is characterized in that, wherein the retardation summation of this first delay cell and this second delay cell equals this second retardation.

5. control device according to claim 1, is characterized in that, wherein the 3rd delay circuit includes:

Multiple the second specific delays unit, tandem connection is to provide respectively a retardation, the plurality of the second specific delays unit includes at least one the 3rd delay cell and one the 4th delay cell, wherein the 3rd delay cell operates under this first input clock, and the 4th delay cell operates under this second input clock; And

One phase inverter, is serially connected with a delay cell in the plurality of the second specific delays unit.

6. control device according to claim 5, is characterized in that, wherein the retardation summation of the 3rd delay cell and the 4th delay cell equals the 3rd retardation.

7. control device according to claim 1, is characterized in that, separately includes:

One selects circuit, be coupled to this first delay circuit, this second delay circuit, the 3rd delay circuit, this first control circuit and this second control circuit, be used for being controlled the one second control signal that signal and this second control circuit produce and producing this selection signal to this first delay circuit, this second delay circuit and the 3rd delay circuit according to produce one first by this first control circuit.

8. control device according to claim 7, is characterized in that, wherein this second delay circuit, the 3rd delay circuit and this selection circuit are pure hardware circuit.

9. control device according to claim 7, is characterized in that, wherein this selection circuit includes:

One first trigger circuit, are controlled by this first input clock, are used for triggering one first according to this first control signal and trigger output signal;

One second trigger circuit, are controlled by this second input clock, are used for triggering one second according to this second control signal and trigger output signal; And

One logic gate, is coupled to these first trigger circuit and this second trigger circuit, is used for producing this selection signal according to this first triggering output signal and this second triggering output signal.

10. control device according to claim 9, is characterized in that, wherein this logic gate is an XOR gate.

11. 1 kinds of control methods, is characterized in that, include:

According to one, select signal and one first retardation one of optionally to postpone in one first input clock and one second input clock to produce output clock to storage device;

To this selection signal delay one second retardation to produce one second the delayed selection culture signal;

According to this second the delayed selection culture signal, operate in optionally this storage device of access of first control circuit of the first input clock;

To this selection signal delay 1 the 3rd retardation to produce one the 3rd the delayed selection culture signal; And

According to the 3rd the delayed selection culture signal, operate in optionally this storage device of access of second control circuit of the second input clock;

Further, this second retardation, the 3rd retardation are greater than this first retardation; This first retardation, the second retardation and the 3rd retardation are all relevant with the clock period of the second input clock to the clock period of the first input clock.

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