CN102130037B - Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process - Google Patents
Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process Download PDFInfo
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Abstract
一种采用吸杂工艺制备带有绝缘埋层的半导体衬底的方法，包括如下步骤：提供器件衬底与支撑衬底；在器件衬底的表面形成绝缘层；热处理器件衬底，从而在所述器件衬底的表面形成洁净区域；将带有绝缘层的器件衬底与支撑衬底键合，使绝缘层夹在器件衬底与支撑衬底之间；对键合界面实施退火加固，使键合界面的牢固程度能够满足后续倒角研磨、减薄以及抛光工艺的要求；对键合后的器件衬底实施倒角研磨、减薄以及抛光。本发明的优点在于，在键合前采用吸杂工艺对器件衬底进行处理，表面形成洁净区域，随后将该洁净区域转移到另一片支撑衬底之上，得到具有高晶体质量的键合材料。
A method for preparing a semiconductor substrate with an insulating buried layer using a gettering process, comprising the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on the surface of the device substrate; heat treating the device substrate, thereby Form a clean area on the surface of the device substrate; bond the device substrate with an insulating layer to the supporting substrate, so that the insulating layer is sandwiched between the device substrate and the supporting substrate; anneal and strengthen the bonding interface, so that The firmness of the bonding interface can meet the requirements of subsequent chamfering, grinding, thinning and polishing processes; chamfering, grinding, thinning and polishing are performed on the bonded device substrate. The advantage of the present invention is that the device substrate is treated with a gettering process before bonding to form a clean area on the surface, and then the clean area is transferred to another supporting substrate to obtain a bonding material with high crystal quality .
Description
Technical field
The invention relates to a kind of method for preparing silicon-on-insulator material, particularly a kind ofly adopt gettering process preparation with the method for the Semiconductor substrate of insulating buried layer.
Background technology
Along with reducing of the characteristic size of integrated circuit, the control of defective in the silicon single crystal become to be even more important.Defective in the silicon chip is the grown-in defects that produces in the process of crystal growth, such as crystal primary partical (COPs) mainly from two aspects on the one hand; Be the defective that produces in the wafer heat process on the other hand, such as oxygen precipitation, if these defectives in the active region of silicon chip surface, will have destruction to performance of devices, make component failure.In addition, silicon chip will be subject to the contamination such as metals such as Cu, Ni and Fe inevitably in the process of processing and integrated circuit manufacturing, the diffusion of these metal impurities in silicon is very fast, if be present in the active area of device, to cause the inefficacy of device, the metal impurities of therefore effectively eliminating silicon chip surface are vital.Oxygen precipitation and induced defects thereof can be used as the gettering point of metal impurities, so that metal impurities assemble at fault location, if but oxygen precipitation and induced defects appear at the device active region, also can affect the electric property of device.Therefore, in device technology, on the one hand need in silicon chip, produce a large amount of oxygen precipitations, play the effect of gettering, wish again that on the other hand oxygen precipitation does not appear at the active region of silicon chip, the basic concept of Here it is intrinsic gettering (InternalGettering).The systemic impurity process of silicon chip by heat treatment, forms the clean area (Denuded Zone-DZ) of hypoxemia and low metal at silicon chip surface, and forms oxygen precipitation and induced defects to absorb metal impurities in wafer bulk.Through the silicon chip of DZ PROCESS FOR TREATMENT, the device preparation can improve the yield of device effectively in the DZ zone.
In addition, thick film SOI material (top layer silicon is usually greater than 1 μ m) is widely used in high voltage power device and MEMS (micro electro mechanical system) (MEMS) field at present, particularly in the development of the aspects such as automotive electronics, demonstration, wireless telecommunications rapidly.Because the control of power supply and conversion, automotive electronics and consumer power device aspect are to the requirement of adverse circumstances, high temperature, large electric current, high power consumption aspect, so that the strict demand aspect reliability has to adopt the SOI device.The user of thick film SOI material mainly comprises U.S. Maxim, ADI, TI (USA), Japanese NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc. at present.In these SOI materials user the inside, very large application is mainly derived from the drive circuit in the various application: such as the amplifier circuit that is applied to be mainly mobile phone acceptance section of Maxim; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in the display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba even in the power control circuit of air-conditioning; Omron is mainly aspect transducer; ADI is also mainly at high temperature circuit, sensor; The application of Phillips then mainly is the LDMOS in the power device, is used for consumer electronics such as automobile audio, audio frequency, audio frequency amplifier etc.; The Magnchip of Korea S (Hynix) then produce to be used for display driver circuit that digital camera uses for Kopin and for the PDP display driver circuit of LG production etc.
But, for the SOI material, because the existence of oxygen buried layer, if it is heat-treated, the oxygen element of oxygen buried layer will outdiffusion, on the contrary so that in its top layer silicon oxygen element content raise, therefore traditional gettering process is not suitable for the SOI material, also cause the top layer silicon of SOI material not have this DZ zone, like this so that the yield of devices of SOI preparation is relatively low.
Summary of the invention
Technical problem to be solved by this invention is that a kind of gettering process that can be applicable to the Semiconductor substrate of insulating buried layer is provided.
In order to address the above problem, the invention provides and a kind ofly adopt gettering process preparation with the method for the Semiconductor substrate of insulating buried layer, comprise the steps: to provide device substrate and support substrates; Surface in device substrate forms insulating barrier; Heat treatment device substrate, thus clean area formed on the surface of described device substrate; To with device substrate and the support substrates bonding of insulating barrier, insulating barrier be clipped between device substrate and the support substrates; The para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing; Device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing.
As optional technical scheme, described device substrate is monocrystalline substrate.
As optional technical scheme, comprise the steps: that further after device substrate was implemented chamfer grinding, attenuate and glossing, the para-linkage rear interface was implemented to replenish annealing and reinforced.
As optional technical scheme, the step of described heat treatment device substrate further comprises: the first heat treatment step, to form crystal region on the device substrate surface; The second heat treatment step, temperature are lower than the first heat-treatment of annealing step, so that the saturated oxygen element in the device substrate beyond the clean area gathers nucleation; The 3rd heat treatment step makes the oxygen element that gathers nucleation in the second heat treatment step form larger oxygen precipitation, and described oxygen precipitation can absorb the metal impurities in the clean area simultaneously.
As optional technical scheme, comprise the steps: that further the surface of coming out in support substrates forms protective layer before device substrate is implemented chamfer grinding, attenuate and glossing.
The invention has the advantages that adopt gettering process that device substrate is processed, the surface forms clean area, subsequently this clean area is transferred on another sheet support substrates, obtains having the bonding material of high-crystal quality before bonding.Further contemplate the thermal stability of the oxygen precipitation in the device substrate body, therefore in preparation technology, can select to implement double annealing technique, first step process annealing, make its bond strength can satisfy the needs that grind and polish, second step is reinforced its bond strength of enhancing more at last, is forming at the interface covalent bond.
Description of drawings
The implementation step flow chart of the specific embodiment of the invention shown in the accompanying drawing 1,
Accompanying drawing 2A is to shown in the accompanying drawing 2E being the process schematic representation of the specific embodiment of the invention.
Embodiment
Next introduce in detail by reference to the accompanying drawings and of the present inventionly a kind ofly adopt gettering process preparation with the embodiment of the method for the Semiconductor substrate of insulating buried layer.
Be the implementation step flow chart of this method shown in the accompanying drawing 1, comprise: step S10 provides device substrate and support substrates; Step S11 forms insulating barrier on the surface of device substrate; Step S12, heat treatment device substrate, thus form clean area on the surface of described device substrate; Step S13 will with device substrate and the support substrates bonding of insulating barrier, be clipped between device substrate and the support substrates insulating barrier; Step S14, the para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing; Step S15, the device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing; Step S16, para-linkage rear interface implement to replenish annealing and reinforce.
Accompanying drawing 2A is to shown in the accompanying drawing 2E being the process schematic representation of the specific embodiment of the invention.
Shown in the accompanying drawing 2A, refer step S10 provides device substrate 100 and support substrates 190.Described device substrate 100 is used to form the device layer of final products, so its material should be for example monocrystalline silicon of common semi-conducting material, also can be that other are such as compound semiconductor etc.And support substrates 190 is owing to only play a supporting role, so selection range is wider, except monocrystalline silicon and common compound semiconductor materials, also can is sapphire even can is metal substrate.In the present embodiment, device substrate 100 is monocrystalline silicon with the material of support substrates 190.
Shown in the accompanying drawing 2B, refer step S11 forms insulating barrier 110 on the surface of device substrate 100.Described insulating barrier 110 is used to form the insulating buried layer of final products, and its material can be silica or silicon nitride etc., and growing method can be chemical vapour deposition (CVD) or thermal oxidation (be used for the monocrystalline substrate surface and form insulating layer of silicon oxide).
Shown in the accompanying drawing 2C, refer step S12, heat treatment device substrate 100, thus form clean area 101 on the surface of described device substrate 100.
Above step can further be decomposed into intensification-cooling-three heat treatment steps of intensification.The first heat treatment step is to form crystal region on the device substrate surface; The second heat treatment step, temperature are lower than the first heat-treatment of annealing step, so that the saturated oxygen element in the device substrate beyond the clean area gathers nucleation; The 3rd heat treatment step makes the oxygen element that gathers nucleation in the second heat treatment step form larger oxygen precipitation, and described oxygen precipitation can absorb the metal impurities in the clean area simultaneously.
Specifically; the first heat treatment step is heating step; target temperature is any temperature value in 900 ℃～1400 ℃ scopes; the target temperature of optimizing is 1250 ℃; the lasting annealing time that rises to behind the target temperature is 0.5～20 hour, is optimized for 4 hours, and programming rate is 0.5～20 ℃/minute; the programming rate of optimizing is 3 ℃/minute, and the protective gas in the temperature-rise period is optimized for Ar/O
2Mist can be other gas or mist, and the atmosphere that continues annealing is N
2, Ar (perhaps other inert gases), H
2, O
2, N
2/ O
2Mist, Ar/O
2Mist, Ar/H
2Mist and N
2In/Ar the mist any one.Heat up for the first time and annealing process in, the outdiffusion of device substrate 100 near surf zone interstitial oxygen concentrations, the width of the temperature and time decision clean area 101 of this step annealing, the width of clean area 101 is generally 10～50 μ m after treatment.
The second heat treatment step is cooling step, cooling rate is 0.5～20 ℃/minute, the cooling rate of optimizing is 3 ℃/minute, the target temperature of cooling is any temperature value in 500～900 ℃ of scopes, the target temperature of optimizing is 750 ℃, and the lasting annealing time of being down to behind the target temperature is 0.5～64 hour, and the optimization time is 8 hours, annealing atmosphere is oxygen-free atmosphere, specifically can be N
2, Ar (perhaps other inert gases), H
2The perhaps mist of above gas.In this cooling step, saturated oxygen element gathers nucleation in clean area 101 device substrate 100 in addition with making.
The 3rd heat treatment step is heating step, programming rate is 0.5～20 ℃/minute, the programming rate of optimizing is 3 ℃/minute, target temperature is any temperature value in 900～1400 ℃ of scopes, the target temperature of optimizing is 1150 ℃, and the lasting annealing time that rises to behind the target temperature is 0.5～40 hour, is optimized for 16 hours, annealing atmosphere is oxygen-free atmosphere, is specially N
2, Ar (perhaps other inert gases), H
2The perhaps mist of above gas.In this step, will make the oxygen element that gathers nucleation in clean area 101 device substrate 100 in addition form larger oxygen precipitation, this oxygen precipitation can absorb the metal impurities in the clean area 101 effectively simultaneously.
The enforcement order of above step S11 and S12 can be put upside down.The advantage that step S11 is at first implemented is that the insulating barrier 110 that generates in advance can form protection to device substrate 100 surfaces, and can shorten the heat treated time, thereby reduces cost.And in the situation that step S11 implements after step S12, be in the execution mode of monocrystalline silicon in device substrate 100, can implement in the second time original position cooling behind the heating step, cooling rate is 0.5～20 ℃/minute, the cooling rate of optimizing is 3 ℃/minute, the target temperature of cooling is any temperature value in 900～1400 ℃ of scopes, and the temperature of optimization is 1050 ℃.Implement in-situ oxidation after the cooling, oxidization time is determined that by needed oxidated layer thickness oxidizing atmosphere is dried oxygen or wet oxygen, or Ar/O
2Mist will form layer of oxide layer on its surface after the oxidation, and this oxide layer can be used as insulating barrier 110.
Shown in the accompanying drawing 2D, refer step S13 will with the device substrate 100 and support substrates 190 bondings of insulating barrier 110, be clipped between device substrate 100 and the support substrates 190 insulating barrier 110.
Be in the execution mode of monocrystalline substrate in support substrates 190, can be chosen in before the bonding and monocrystalline silicon support substrates 190 be ground and the pre-treatment such as polishing, with its thickness of attenuate.Take 8 inches monocrystalline substrate as example, 750 microns of substrate thickness, the substrate total thickness deviation is less than 4 microns, the target thickness of substrate thinning is 650 microns, at first grind this monocrystalline substrate of attenuate, milling apparatus is preferably the single face grinder, unit type is DFG 841 type grinders, at first roughly grind quick attenuate, grinding wheel speed is greater than 2000rpm, and correct grinding reduces to grind the damage that causes subsequently, and grinding wheel speed is greater than 2000rpm, grind back substrate thickness and more than 3 microns, be thinned to 660 microns greater than target thickness here.Support substrates 190 after grinding is polished, and can be that twin polishing also can be single-sided polishing, also can be two-sided+single-sided polishing, is optimized for two-sided+single-sided polishing here.At first twin polishing, unit type are Peter Wolters AC2000 type Twp-sided polishing machine, and whole polishing process was divided into for two steps, at first rough polishing, subsequently finishing polish, and always polishing removal amount is 8 microns; Adopt subsequently single-sided polishing with accurate control silicon wafer thickness, unit type is IPEC 372 type single side polishing machines, and whole polishing process is divided into rough polishing and two steps of finishing polish equally, and the polishing removal amount is not more than 2 microns, after revising, can make the substrate total thickness deviation less than 1 micron.
Before can also being chosen in bonding support substrates 190 is carried out the insulating processing, make its appearance cover one deck insulation etch resistant layer, particularly make its back side cover this etch resistant layer, optimizing insulating treatment process is that the ordinary oxygen metallization processes gets final product, and also can adopt PECVD deposit silicon dioxide silicon nitride etc.Etch resistant layer thickness is generally one micron.Because technique backward is ruggedization under lower temperature, support substrates 190 possibly can't stop the corrosion of TMAH solution in chamfer angle technique, form overleaf a lot of etch pits, therefore generates in advance one deck insulation etch resistant layer, makes its effectively back side of protection support substrates.
After support substrates 190 carried out pre-treatment, device substrate 100 and support substrates 190 are cleaned and bondings.Bonding can be that common hydrophilic bonding also can be hydrophobic bonding, it also can be the auxiliary hydrophilic bonding of plasma, be preferably the auxiliary hydrophilic bonding of hydrophilic bonding and plasma, here be combined into example with hydrophilic bond, use successively SC1 and SC2 solution to clean this substrate, before the bonding, adopt rotary-cleaning device substrate 100 and support substrates 190 substrates at the EVG801 bonder, to remove the particle that the surface may exist and to adsorb more hydrone, subsequently device substrate 100 and support substrates 190 are bonded together.
Refer step S14, the para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing.It is 900～1400 ℃ that temperature is reinforced in annealing, and the temperature of optimization is 1050 ℃, and the annealing consolidation time is 0.5～10 hour, be optimized for 6 hours, programming rate is 0.5～20 ℃/minute, and the programming rate of optimization is 3 ℃/minute, and annealing atmosphere is optimized for dried oxygen or wet oxygen.Adopt above annealing reinforcing condition then to need not to replenish the step of reinforcing, namely need not implementation step S16.Diffusion in for fear of impurity in the process of annealing reinforcing to the clean area 101 of device substrate 100 can also be selected more gentle annealing conditions, and replenish at subsequent implementation step S16 in this step.The temperature of reinforcing of for example will annealing is chosen in 500～1200 ℃, is optimized for 900 ℃, and consolidation time is 1～10 hour, is optimized for 4 hours, and it is N that atmosphere is reinforced in annealing
2, Ar (perhaps other inert gases), O
2, N
2/ O
2Mist, Ar/O
2Mist etc.Below the consolidation effect at more gentle annealing conditions para-linkage interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing equally.
Shown in the accompanying drawing 2E, refer step S15, the device substrate 100 behind the para-linkage is implemented chamfer grinding, attenuate and polishing.Accompanying drawing 2E is the state of above-mentioned process implementing after complete, it is pointed out that through in the steps such as attenuate and polishing to the control of removal amount, can guarantee that the device substrate 100 that keeps among the accompanying drawing 2E all is to be made of clean area 101.
Step S16, para-linkage rear interface implement to replenish annealing and reinforce.If what adopt among the step S14 is relatively mild annealing reinforcement process, then need to select to implement this step, to strengthen the bond strength between support substrates 190 and the insulating barrier 110, forming at the interface covalent bond.The annealing temperature of this step is 900～1400 ℃, and the annealing temperature of optimization is 1150 ℃, and annealing time is 0.5～10 hour, be optimized for 4 hours, programming rate is 0.5-20 ℃/minute, and the programming rate of optimization is 3 ℃/minute, and annealing atmosphere is optimized for dried oxygen or wet oxygen.For the device substrate 100 that is consisted of by single crystal silicon material, in the process of this oxidation, also further formed layer of oxide layer on device substrate 100 surfaces, thickness by the control oxide layer can further be controlled the thickness of the device substrate 100 that consumes, and reaches the purpose of accurate control device layer thickness.Adopt HF solution removal oxide layer after the annealing, obtain the final substrate with insulating buried layer, its device layer is made of the clean area 101 of device substrate 100.
The advantage of technique scheme is, before bonding, adopt gettering process that device substrate 100 is processed, the surface forms clean area 101, subsequently this clean area 101 is transferred on another sheet support substrates 190, obtains having the bonding material of high-crystal quality.Further contemplate the thermal stability of the oxygen precipitation in device substrate 100 bodies, therefore in preparation technology, can select to implement double annealing technique, first step process annealing, make its bond strength can satisfy the needs that grind and polish, second step is reinforced its bond strength of enhancing more at last, is forming at the interface covalent bond.
In sum; although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; the persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining that claims apply for.
Claims (4)
1. one kind is adopted the gettering process preparation with the method for the Semiconductor substrate of insulating buried layer, it is characterized in that, comprises the steps:
Device substrate and support substrates are provided;
Surface in device substrate forms insulating barrier;
Device substrate is implemented the first heat treatment step, so that the outdiffusion of the nearly surf zone interstitial oxygen concentration of device substrate forms clean area in the surface of device substrate inside;
Device substrate is implemented the second heat treatment step, and temperature is lower than the first heat-treatment of annealing step, so that the saturated oxygen element in the device substrate beyond the clean area gathers nucleation;
Device substrate is implemented the 3rd heat treatment step, make the oxygen element that gathers nucleation in the second heat treatment step form larger oxygen precipitation, described oxygen precipitation can absorb the metal impurities in the clean area simultaneously;
To with device substrate and the support substrates bonding of insulating barrier, insulating barrier be clipped between device substrate and the support substrates;
The para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing;
Device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing.
2. method according to claim 1 is characterized in that, described device substrate is monocrystalline substrate.
3. method according to claim 1 is characterized in that, comprises the steps: that further after device substrate was implemented chamfer grinding, attenuate and glossing, the para-linkage rear interface was implemented to replenish annealing and reinforced.
4. method according to claim 1 is characterized in that, comprises the steps: that further the surface of coming out in support substrates forms protective layer before device substrate is implemented chamfer grinding, attenuate and glossing.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010607936 CN102130037B (en) | 2010-12-27 | 2010-12-27 | Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process |
| US13/976,486 US9299556B2 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer gettering process |
| PCT/CN2010/080599 WO2012088710A1 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
| KR1020137019860A KR101512393B1 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
| JP2013546558A JP5752264B2 (en) | 2010-12-27 | 2010-12-31 | Method for manufacturing a semiconductor substrate with an insulating layer by an impurity gettering process |
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|---|---|---|---|
| CN 201010607936 CN102130037B (en) | 2010-12-27 | 2010-12-27 | Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process |
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| CN102130037A CN102130037A (en) | 2011-07-20 |
| CN102130037B true CN102130037B (en) | 2013-03-13 |
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| CN102315096A (en) * | 2011-08-19 | 2012-01-11 | 上海新傲科技股份有限公司 | Preparation method of multilayer semiconductor substrate |
| JP6168143B2 (en) * | 2013-05-01 | 2017-07-26 | 信越化学工業株式会社 | Method for manufacturing hybrid substrate |
| CN104952726A (en) * | 2014-03-26 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturemethod of semiconductor substrate for passive device |
| FR3051968B1 (en) * | 2016-05-25 | 2018-06-01 | Soitec | METHOD FOR MANUFACTURING HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE |
| CN109346433B (en) * | 2018-09-26 | 2020-10-23 | 上海新傲科技股份有限公司 | Method for bonding semiconductor substrate and bonded semiconductor substrate |
| CN112689886B (en) * | 2020-06-16 | 2022-11-18 | 福建晶安光电有限公司 | Substrate processing method and semiconductor device manufacturing method |
| US20230154785A1 (en) * | 2020-08-13 | 2023-05-18 | Enkris Semiconductor, Inc. | N-face polar gan-based device and composite substrate thereof, and method of manufacturing composite substrate |
| CN113421849B (en) * | 2021-06-09 | 2023-01-03 | 中环领先半导体材料有限公司 | Preparation process of silicon substrate with insulating buried layer |
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| CN101114574A (en) * | 2006-07-24 | 2008-01-30 | 株式会社上睦可 | Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby |
| CN101432849A (en) * | 2006-04-27 | 2009-05-13 | 信越半导体股份有限公司 | SOI wafer manufacturing method |
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| CN101114574A (en) * | 2006-07-24 | 2008-01-30 | 株式会社上睦可 | Method for manufacturing bonded soi wafer and bonded soi wafer manufactured thereby |
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