CN102129379B - Logic component for data loading - Google Patents
Logic component for data loading Download PDFInfo
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- CN102129379B CN102129379B CN201110040242.XA CN201110040242A CN102129379B CN 102129379 B CN102129379 B CN 102129379B CN 201110040242 A CN201110040242 A CN 201110040242A CN 102129379 B CN102129379 B CN 102129379B
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Abstract
The invention relates to a logic component which is applied in a computer system; the computer system comprises a CPU (Central Processing Unit) connected with the logic component and a second logic component connected with the logic component; the logic component comprises a write operation detecting unit and a clock generating unit, wherein the write operating detecting unit is used for detecting the write operation for write logic data initiated by the CPU to the second logic component through the first logic component and informing the clock signal generating unit when the write operation is detected; the clock signal generating unit is used for generating clock signal according to a predetermined cycle after the inform of the detecting unit is received and supplying the clock signal into the second logic component to collect written data.
Description
Technical field
The present invention relates to logical device loading technique, relate in particular to the logical device technology that a kind of rapid data loads.
Background technology
Development along with logical device technology, the programmable logic chip such as FPGA and CPLD gets a lot of applications gradually, this class chip need to carry out the loading (being commonly referred to logic loads) of program or configuration file conventionally, and general traditional approach is after first burning logic, logic chip to be welded on circuit board.But the obvious underaction of this method, if need the upgrading of debugging or version just more difficult, for the finished product having used on market, the upgrading of version has increased operation cost more greatly.
The appearance of JTAG technology has brought very large change to loading, and logic chip loads flow process and is reduced to: first immobilising device on circuit board again with JTAG to chip programming.Such flow process is speeded up the work greatly.By JTAG line, download the main way that logic becomes debugging, maintenance, production gradually.Yet along with the development of technology, complexity and the capacity of chip are increasing, by JTAG, are downloaded and are just produced no small defect:
First, for a product being widely used on market, the renewal of version and maintenance all need to open cabinet, connect JTAG downloading wire and carry out logical renewal, and the inconvenience causing is self-evident, and operation cost is a no small numeral especially.
Secondly, JTAG is serial line interface, uses the simple JTAG cable of LPT, utilization be the feature that the output band of LPT latchs, use software to produce JTAG sequential by I/O.Sequential is determined by JTAG standard, by byte of JTAG Writing/Reading, needs a series of operation.Suppose to use simple JTAG cable, utilize LPT, by JTAG, export a byte to Target Board, on average need 43 LPT I/O, for the computing machine of a P4 dominant frequency 1.7G, per secondly approximately can carry out 660K I/O operation, speed of download approximates greatly 15K Byte/S.Yet such speed, take the logic that MB is unit-sized for one, needs to load for a long time.
Please refer to Fig. 1, also has at present a kind of scheme, use configuration file/program that CPU or microcontroller read out logic chip from storage medium instead and carry out logic loading, the loading sequential of other that simulation JTAG sequential or device are supported, is loaded into configuration file in logic chip and goes.Thisly by CPU or microprocessor simulated timing diagrams, realize on-line loaded and solved the inconvenience loading from JTAG line.There are at present two kinds of implementations.
A kind of implementation is to use CPU or microprocessor GPIO mouth simulated timing diagrams to realize on-line loaded.This mode can obtain speed faster, but taken CPU or microprocessor compared with multi-pipe pin.
In the embedded system that another kind of implementation is the current widespread use of consideration, all contain CPLD programming device, by CPLD being articulated in the bus of CPU or microprocessor, FPGA is connected to CPLD upper, by the CPLD on CPU or microprocessor control bus, simulates on-line loaded sequential.So neither can additionally take the pin of CPU or microprocessor, realize again the Configuration Online to logical device.This mode cost is low, have very strong convenience, but the loading velocity of this scheme is not fast especially, can not meet developer's demand.
Summary of the invention
The object of the present invention is to provide a kind of logical device of rapid loading, to overcome the slow problem of prior art logical data loading velocity, the present invention is achieved by the following scheme.
A kind of logical device, it is applied in computer system, and described computer system comprises, the CPU being connected with this logical device and the second logical device being connected with this logical device, described logical device comprises write operation detecting unit and clock generating unit, wherein:
Described write operation detecting unit, the write operation that writes logical data of initiating to the second logical device by the first logical device for detection of CPU, and when described write operation generation being detected, notify described clock signal generation unit;
Described clock signal generation unit, for after receiving the notice of detecting unit, according to predetermined cycle clocking, and this clock signal is offered to described the second logical device, the logical data that utilizes this clock signal collection to write for the second logical device.
Preferably, the sequential of the cycle of wherein said clock signal and the second logical device requires adaptive.
Preferably, wherein the second logical device comprises data sampling unit, and sample to the logical data writing according to this clock signal in this data sampling unit, and this logical data is updated in the storage space of self.
Preferably, wherein said logical device and the second logical device are CPLD or FPGA.
Preferably, whether described write operation detecting unit has data to be written in corresponding register on the data line of the bus that is connected with CPU to have determined whether that write operation occurs by detecting.
Accompanying drawing explanation
Fig. 1 is prior art logic schematic diagram.
Fig. 2 is prior art sequential chart.
Fig. 3 is logic schematic diagram of the present invention.
Fig. 4 is sequential chart of the present invention.
Embodiment
Present inventor by experiment with scheme that analyse in depth to find Fig. 1 when carrying out on-line loaded, logic configuration file/the program (hereinafter to be referred as logic) reading out from storage medium need to be sent in logic chip device and goes, when sending a secondary data, need to provide a clock edge.This clock is along what normally simulate by software at present, but CPU is according to software code control bus operation CPLD, simulation produces clock along needing the long period, has had a strong impact on loading velocity.
Please refer to Fig. 2, wherein the implication of each time is as follows:
Tpre represents to write the time span of data;
Ts represents to write the time that invoke code after data is write data again;
Trc clock cclk writes the running time of high/low level under software operation.
Can find out from the graph, whole sequential is that the software by operating on CPU is simulated, and it is T1=Tpre+Trc+Trc+Ts that Fig. 2 clearly exercises out the time that completes a complete data write operation and need.Because data writing operation is all to realize by writing register manipulation in bus with writing clock operation, so the length of these two times of Tpre and Trc is basically identical.The time span of Ts is very short, can ignore, because roughly can think T1=3Tpre in engineering design in whole T1.Existing scheme logical data writes and generally comprises following steps:
1.CPU is to D[0:7] corresponding register data writing
2.CPLD is to D[0:7] reflect data variation on data line
CPU writes 0 by the corresponding register of CCLK
CPLD drags down CCLK
CPU writes 1 by the corresponding register of CCLK
CPLD draws high CCLK, and FPGA samples at rising edge clock, obtains data
CPU needs the long period according to software code control bus operation CPLD simulation generation clock as can be seen here, has had a strong impact on loading velocity.And the business processing of bearing as CPU is busier time, likely affects it and controls the operation that CPLD simulation produces clock, loading velocity will further be affected.
Please refer to Fig. 3, is the typical application scenarios of the present invention shown in Fig. 3, is relatively typically one with the embedded processing systems of CPU, such as Network Security Device etc.; Yet the present invention is not limited thereto.Conventionally with the computer system of CPU, need to carry out when logic loads all can applying the present invention.Described computer system comprises CPU, storage medium, the first logical device and the second logical device.Wherein between the first logical device and CPU, by bus, be connected.Described the first logical device comprises write operation detecting unit and clock signal generation unit; Described the second logical device comprises data sampling unit.The write operation that writes logical data that wherein said write operation detecting unit is initiated to the second logical device by the first logical device for detection of CPU, and when described write operation generation being detected, notify described clock signal generation unit.Described clock signal generation unit, for after receiving the notice of detecting unit, according to predetermined cycle clocking, and this clock signal is offered to described the second logical device, the logical data that utilizes this clock signal collection to write for the second logical device.The sequential of the cycle of wherein said clock signal and the second logical device requires adaptive.Sample to the logical data writing according to this clock signal in the data sampling unit of the second logical device, and this logical data is updated in the storage space of self.With the first logical device, be CPLD below, the second logical device is that FPGA is that example is carried out exemplary illustration.
Please refer to Fig. 3, the first logical device (being CPLD) and the second logical device (being FPGA) coupling part comprise: the control register in PROGRAM, CS, the corresponding CPLD of RDWR_B, INIT, status register in INIT, DONE, the corresponding CPLD of BUSY, when status register is operated, without time clock is provided.D[0:7 wherein] data register in corresponding CPLD, when operating on it, need to provide time clock.
Before logical data is write to FPGA, CPU first will read in internal memory (not shown) by the logical data of FPGA (such as configuration file) from storage medium, then by the sequential of adaptive FPGA and order, FPGA is configured, is about to described logical data and is written in described FPGA.
First, CPU is to D[0:7] corresponding register writes above-mentioned logical data; The write operation detecting unit of CPLD inside detects the D[0:7 of the bus being connected with CPU] reflect data variation on data line, be that CPLD detects to the operation of corresponding registers data writing, with being about to CCLK, drag down, then according to predetermined sequential, require CCLK to draw high, the clock generating unit that now described CCLK is CPLD inside offers the clock signal of FPGA, also has corresponding register in CPLD.FPGA samples at rising edge clock, and then obtains the logical data that CPU will be written to FPGA.
Please refer to Fig. 4, as can be seen from Figure 4 come, due to this programmable hardware assist clocking of CPLD, the size of T2 has become Tpre+Ts.Because Ts is smaller, can ignore.Therefore can roughly think T2=Tpre, with respect to the time span of the needed T1=Tpre of prior art, T2 only has 1/3 size of T1.Therefore the ablation process of logical data has shortened greatly, and on-line loaded speed has obtained the lifting of matter.This clock is to be triggered by the write operation of CPU simultaneously, so also meet normal sequential requirement completely.
Described above is only preferably implementation of the present invention, not in order to limit protection scope of the present invention, within any variation being equal to and modification all should be encompassed in protection scope of the present invention.
Claims (5)
1. a logical device, it is applied in computer system, and described computer system comprises, the CPU being connected with this logical device and the second logical device being connected with this logical device, described logical device comprises write operation detecting unit and clock generating unit, it is characterized in that:
Described write operation detecting unit, the write operation that writes logical data of initiating to the second logical device by this logical device for detection of CPU, and when described write operation generation being detected, notify described clock signal generation unit;
Described clock signal generation unit, for after receiving the notice of this write operation detecting unit, according to predetermined cycle clocking, and this clock signal is offered to described the second logical device, the logical data that utilizes this clock signal collection to write for the second logical device.
2. according to the logical device described in claim l, it is characterized in that, the sequential of the cycle of described clock signal and the second logical device requires adaptive.
3. logical device according to claim 1, it is characterized in that, described the second logical device comprises data sampling unit, and sample to the logical data writing according to this clock signal in this data sampling unit, and this logical data is updated in the storage space of self.
4. logical device according to claim 1, is characterized in that, wherein said logical device and the second logical device are CPLD or FPGA.
5. logical device according to claim 1, is characterized in that, whether described write operation detecting unit has data to be written in corresponding register on the data line of the bus that is connected with CPU to have determined whether that write operation occurs by detecting.
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| CN102129379B true CN102129379B (en) | 2014-01-15 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523510A (en) * | 2003-02-18 | 2004-08-25 | 明基电通股份有限公司 | Method and device for repeatedly downloading data to field programmable gate array |
| CN1808374A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | Field programmable gate array loading method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523510A (en) * | 2003-02-18 | 2004-08-25 | 明基电通股份有限公司 | Method and device for repeatedly downloading data to field programmable gate array |
| CN1808374A (en) * | 2005-01-21 | 2006-07-26 | 华为技术有限公司 | Field programmable gate array loading method |
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Address after: 310000 Binjiang District, Hangzhou, Binjiang Avenue, No. Huarong Times Building, room 1601, room 3880 Patentee after: Hangzhou Dipu Polytron Technologies Inc Address before: 310000 Binjiang District, Hangzhou, Binjiang Avenue, No. Huarong Times Building, room 1601, room 3880 Patentee before: Hangzhou Dipu Technology Co., Ltd. |
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Effective date of registration: 20181031 Address after: 310051 05, room A, 11 floor, Chung Cai mansion, 68 Tong Xing Road, Binjiang District, Hangzhou, Zhejiang. Patentee after: Hangzhou Depp Information Technology Co., Ltd. Address before: 310000 room 1601, Huarong Times Building, 3880 Binjiang Avenue, Hangzhou, Zhejiang, Binjiang District. Patentee before: Hangzhou Dipu Polytron Technologies Inc |