CN102122643B - Method for manufacturing bipolar junction transistor - Google Patents
Method for manufacturing bipolar junction transistor Download PDFInfo
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- CN102122643B CN102122643B CN201110032428.0A CN201110032428A CN102122643B CN 102122643 B CN102122643 B CN 102122643B CN 201110032428 A CN201110032428 A CN 201110032428A CN 102122643 B CN102122643 B CN 102122643B
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Abstract
The invention relates to a method for manufacturing a bipolar junction transistor, which is compatible with a process for preparing a complementary metal oxide semiconductor (CMOS) transistor. In the method, an emitter is formed in a bipolar junction transistor preparation region while gate polycrystalline silicon is formed in a CMOS transistor preparation region; high doping is generally required to be performed on an extrinsic base region in the bipolar junction transistor so as to form good ohmic contact with an electrode; a self-aligned extrinsic base region is realized by means of self-aligned high-doping ion implantation of the CMOS transistor; and doping ions are implanted and propelled to the emitter, so that the doping ions are uniformly propelled to the base region to form an emitter junction, the thickness of the emitter junction is more uniform, and etching damage is repaired by means of a rapid thermal oxidation process of a CMOS polycrystalline silicon gate after a polycrystalline silicon layer is etched; therefore, the boundary effect is reduced and the leakage current is reduced.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of the bipolar transistor compatible mutually with CMOS transistor preparation process.
Background technology
Bipolar transistor (BJT, Bipolar Junction Transistor) is one of conventional device architecture forming modern large scale integrated circuit, and its service speed is fast, saturation voltage drop is little, current density is large and production cost is low.Bipolar transistor is that one utilizes electronics and hole (hole) these two kinds of charge carriers (Carries) to carry out the electronic component of conduction current, and the structure of bipolar transistor is by two groups of three ends (Three Terminal) elements of forming of PN junction closely.Three ends are emitter (Emitter), base stage (Base) and collector electrode (Collector) respectively.
Fig. 1 a ~ Fig. 1 c is the structural representation of the forming process of bipolar transistor in prior art, as shown in Fig. 1 a ~ Fig. 1 c, the step of bipolar transistor is formed in prior art, comprise and semi-conductive substrate 10 is provided, in described substrate 10, form shallow channel isolation area 14, in described substrate 10, form well region 11, then, in described substrate 10, and described well region 11 forms collector area 12 by ion implantation, in described substrate 10, on described collector area 12 and between described shallow channel isolation area 14, form base region 13 by ion implantation, form oxide layer 15 at described substrate 10 surface deposition, form structure as shown in Figure 1a, etching window in described oxide layer 15, to expose the part base region 13 in substrate 10, form one deck polysilicon layer 16 in described oxide layer 15 and part base region 13 surface deposition, form structure as shown in Figure 1 b, partial etching polysilicon layer 16, to form emitter 18, Doped ions injection is carried out to described emitter 18, carry out high-temperature annealing process, Doped ions is made to enter base region certain depth, to form emitter junction 17, as illustrated in figure 1 c, due to described oxide layer 15 open up described wicket after form step, the described polysilicon layer 16 then formed is uneven above described wicket, cause the degree of depth of ion implantation uneven, emitter junction 17 degree of depth formed after its thermal diffusion is like this also uneven, in " V " character form structure, in the middle of described emitter junction 17, dark two ends are shallow, the impact of polysilicon and silicon interface defect is vulnerable in emitter junction shallow junction region, greatly increase emitter base leakage current, the thickness of described oxide layer is thicker, and described emitter junction thickness changing trend is more obvious, and leakage current increases, and affects device performance, so device performance is subject to the impact of oxide layer stable preparation process, the instability of polysilicon shoulder height makes polysilicon effective thickness unstable, so be difficult to the degree of depth and the concentration that control emitter doping injection.And the dense doping in above-mentioned processing procedure required for extrinsic base region is difficult to realize the autoregistration with emitter junction easily, easy like this cause emitter junction both sides to be all highly doped thus tunnel electric leakage increase.
Summary of the invention
The technical problem to be solved in the present invention is, provides a kind of mutually compatible with CMOS transistor preparation process, extrinsic base region and emitter junction self aligned, the manufacture method of the uniform bipolar transistor of emitter junction thickness.
For solving the problems of the technologies described above, the invention provides manufacture method that the is a kind of and bipolar transistor of CMOS transistor preparation process compatibility, comprising the following steps: provide a substrate, described substrate comprises CMOS transistor and prepares district and bipolar transistor prepares district; Preparing district and bipolar transistor in described CMOS transistor prepares after the deposit simultaneously of surface, district forms the first oxide layer, and etching removes the first oxide layer that bipolar transistor prepares surface, district; Prepare district and bipolar transistor in described CMOS transistor to prepare the deposit simultaneously of surface, district and form polysilicon layer; Doped ions injection is carried out to described polysilicon layer; Prepare district in described CMOS transistor to etch described polysilicon layer and formed while grid polycrystalline silicon, prepare district at described bipolar transistor and etch described polysilicon layer and form polysilicon emitter; Carry out rapid thermal oxidation, form the second oxide layer, to repair the damage in etching process being prepared by bipolar transistor to district; Synchronously oxide side wall is formed in described grid polycrystalline silicon both sides and described polysilicon emitter both sides; CMOS transistor is prepared district and bipolar transistor and is prepared district's autoregistration simultaneously and inject highly doped ion, prepares in district, the substrate of described polysilicon emitter both sides forms extrinsic base region at described bipolar transistor; Carry out rapid thermal anneal process, the Doped ions in described polysilicon emitter is advanced, to form emitter junction.
Further, the thickness of described second oxide layer is
Further, described polysilicon layer thicknesses is
Further, the time of described rapid thermal oxidation is 10s ~ 50s, and temperature is 1000 DEG C-1300 DEG C.
Further, when carrying out Doped ions to described polysilicon layer and injecting, the energy of the Doped ions of employing is 20KeV ~ 40KeV, and the doping content of described Doped ions is 4E15cm
-2~ 5E15cm
-2.
Further, the energy of described highly doped ion is 20KeV ~ 60KeV, and doping content is 1E15cm
-2~ 5E15cm
-2.
Further, the annealing temperature of described rapid thermal anneal process is 1000 DEG C ~ 1100 DEG C, and annealing time is 5s-20s.
Further, described bipolar transistor is NPN type or positive-negative-positive.
In sum, the manufacture method of bipolar transistor of the present invention, described CMOS transistor prepares in district the process forming grid polycrystalline silicon while, prepare the direct deposit of substrate surface in district at described bipolar transistor and form polysilicon layer, form polysilicon emitter.For bipolar transistor usually need to extrinsic base region carry out highly doped so that and the ohmic contact that formed of electrode, use the high ion implantation of mixing of CMOS transistor autoregistration and realize self aligned extrinsic base region, and Doped ions injection and propelling are carried out to described polysilicon emitter, thus Doped ions is advanced into described base region formation emitter junction equably, thus make the thickness of emitter junction more even, the rapid thermal oxidation process of simultaneously using CMOS polysilicon gate after etches polycrystalline silicon layer repairs etching injury, and carry out Doped ions injection and propelling, thus Doped ions is advanced into described base region formation emitter junction equably, thus make the thickness of emitter junction more even, thus reduction interfacial effect, reduce leakage current.By using deposition and the etching of CMOS transistor polysilicon gate, not needing extra polysilicon preparation and etching technics, saving manufacturing cost.Achieve the autoregistration of extrinsic base region and emitter junction, reduce the electric leakage of emitter junction.
Accompanying drawing explanation
Fig. 1 a ~ Fig. 1 c is the structural representation of the forming process of bipolar transistor in prior art.
The Making programme schematic diagram that Fig. 2 is bipolar transistor described in one embodiment of the invention.
Fig. 3 a ~ Fig. 3 c is the structural representation of the forming process of bipolar transistor in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Core concept of the present invention is: the forming process of CMOS transistor while, use CMOS grid polycrystalline silicon, oxide side wall and highly doped ion autoregistration injection process, the oxide side wall of synchronous formation bipolar transistor polysilicon emitter, emitter and extrinsic base region self aligned with emitter junction, because polysilicon emitter thickness is smooth, the emitter junction uniform depth that its Doped ions is formed in thermal annealing process, thus reach the object avoiding the too simple and easy shortcoming affected by boundary defect of emitter junction edge junction depth in usual technique.
Described bipolar transistor can be NPN type or positive-negative-positive.In the present embodiment, for PNP bipolar transistor, in addition equally the present invention is suitable for for NPN bipolar transistor, Fig. 3 a ~ Fig. 3 c is the structural representation of the forming process of bipolar transistor in one embodiment of the invention, the Making programme schematic diagram that Fig. 2 is bipolar transistor described in one embodiment of the invention, shown in Fig. 2 and Fig. 3 a ~ Fig. 3 c, form described PNP bipolar transistor and comprise the following steps:
S01: as shown in Figure 3 a, provides a substrate 300, and described substrate 300 comprises CMOS transistor and prepares district 200 and bipolar transistor prepares district 100; Described substrate 300 forms well region 110, prepare in district 100 at described substrate 300 bipolar transistor, collector area 120 is formed above well region 110, for PNP bipolar transistor, described collector area 120 is P type, therefore Doped ions can be boron (Boron), gallium (Ga) etc., wherein preferably, be utilize ion implantation to inject boron ion; Base region 130 is formed above described collector area 120, for PNP bipolar transistor, described base region 130 is N-type, therefore Doped ions can be phosphorus (P), arsenic (As) etc., wherein preferably, utilize ion implantation to inject phosphonium ion, before the described well region 110 of formation, fleet plough groove isolation structure (STI) 140 is also formed in described substrate 300, the formation process of described collector area 120, base region 130 and described fleet plough groove isolation structure 140, known by those skilled in the art, does not repeat at this.
S02: prepare district 200 and bipolar transistor in described CMOS transistor and prepare after the deposit simultaneously of surface, district 100 forms the first oxide layer 400, etching removes the first oxide layer 400 that bipolar transistor prepares surface, district 100; As shown in Figure 3 a, district 200 is prepared and bipolar transistor prepares district 100 surface smear photoresist 500 in described CMOS transistor, the photoresist that bipolar transistor prepares surface, district 100 is removed by exposure, development, carry out etching technics again, remove the first oxide layer 400 that bipolar transistor prepares surface, district 100.
S03: as shown in Figure 3 b, prepares district 200 and bipolar transistor in described CMOS transistor and prepares the deposit simultaneously of surface, district 100 and form polysilicon layer 150; Form described polysilicon layer 150 and adopt chemical meteorology deposition method, described polysilicon layer 150 thickness is
S04: Doped ions injection is carried out to described polysilicon layer 150; Carry out Doped ions injection to polysilicon layer 150, preferably, for PNP bipolar transistor, described Doped ions is boron, and ion implantation energy is 25KeV ~ 35KeV, and Doped ions concentration is 4E15cm
-2~ 5E15cm
-2.
S05: as shown in Figure 3 c, prepares district 200 in described CMOS transistor and etches while described polysilicon layer 150 forms grid polycrystalline silicon 250, prepares district 100 etch described polysilicon layer 150 and form polysilicon emitter 151 at described bipolar transistor; Forming process is, at described polysilicon layer 150 surface smear photoresist, utilize identical mask plate, prepare to described CMOS transistor the photoresist that district 200 and described bipolar transistor prepare district 100 expose and develop, to expose the polysilicon layer 150 that needs etch away, then dry etching is utilized to remove the polysilicon layer 150 exposed, after removing photoresist, the polysilicon layer 150 of reservation forms grid polycrystalline silicon 250 and polysilicon emitter 151 simultaneously.
S06: as shown in Figure 3 c, carries out rapid thermal oxidation, to repair the damage in etching process being prepared by bipolar transistor to district 100, prepares district 200 and bipolar transistor prepare district 100 surface uniform and form the second oxide layer 190 in described CMOS transistor.Described second oxide layer 190 can repair the damage in etching process of described polysilicon emitter 151 and base region 130, and the time of described rapid thermal oxidation is 10s ~ 50s, and temperature is 1000 DEG C-1300 DEG C.After described CMOS transistor is prepared in district and is formed grid polycrystalline silicon 250, rapid thermal oxidation can form the second oxide layer 190 on the surface of polysilicon emitter 151, therewith synchronously, the surface of preparing district 100 at described bipolar transistor does not cover the oxide layer of deposition for etching stopping before forming polysilicon layer 150, therefore in etches polycrystalline silicon layer 150 process, do not adopt etching stop layer, but many etchings remove section substrate 300, described second oxide layer 190 is formed on surface after formation polysilicon emitter 151, the etching injury of described polysilicon emitter 151 can be repaired.
S07: synchronously form oxide side wall 160 in described grid polycrystalline silicon 250 both sides and described polysilicon emitter 151 both sides; Described oxide side wall 160 is in order to determine that height mixes the autoregistration distance of ion and described polysilicon emitter 151.
S08: prepare district and bipolar transistor in CMOS transistor and prepare district's autoregistration simultaneously and inject highly doped ion, prepare in district at described bipolar transistor, the substrate 300 of described polysilicon emitter both sides forms extrinsic base region 170, namely CMOS transistor is prepared while district 200 forms source region and drain region, prepares autoregistration in the substrate 300 of polysilicon emitter 151 both sides, district 100 inject highly doped ion and form extrinsic base region 170 at bipolar transistor; The energy of described highly doped ion is 20 ~ 60KeV, and doping content is 1E15 ~ 5E15, and the extrinsic base region 170 with highly doped ion can make base region 130 form good ohmic contact with the plain conductor of follow-up formation.
S09: carry out rapid thermal anneal process, advances the Doped ions in described polysilicon emitter, to form emitter junction 180.Described rapid thermal annealing, advance the Doped ions in described emitter to described base region, to form emitter junction 180, the annealing temperature of described rapid thermal annealing is 1000 DEG C ~ 1100 DEG C, and annealing time is 3s ~ 7s.
In sum, the present invention is in the forming process of CMOS transistor, use the ion autoregistration injection process of MOS polysilicon gate, grid side wall and dense doping, realize bipolar transistor polysilicon emitter and extrinsic base region self aligned with emitter junction, and because polysilicon emitter thickness is smooth, the emitter junction uniform depth that its Doped ions is formed in thermal annealing process, thus avoid the junction depth too simple and easy shortcoming affected by boundary defect in emitter junction edge in usual technique; And said method can make surface, district and CMOS transistor making district at bipolar transistor utilizes identical mask plate to expose photoresist, develop, and synchronous etching forms polysilicon emitter and grid polycrystalline silicon, in ic manufacturing process, greatly save processing step, enhanced productivity and cost.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (8)
1. a manufacture method for the bipolar transistor compatible mutually with CMOS transistor preparation process, is characterized in that, comprise the following steps:
There is provided a substrate, described substrate comprises CMOS transistor and prepares district and bipolar transistor prepares district;
Preparing district and bipolar transistor in described CMOS transistor prepares after the deposit simultaneously of surface, district forms the first oxide layer, and etching removes the first oxide layer that described bipolar transistor prepares surface, district;
Prepare district and bipolar transistor in described CMOS transistor to prepare the deposit simultaneously of surface, district and form polysilicon layer;
Doped ions injection is carried out to described polysilicon layer;
Prepare district in described CMOS transistor to etch described polysilicon layer and formed while grid polycrystalline silicon, prepare district at described bipolar transistor and etch described polysilicon layer and form polysilicon emitter;
Carry out rapid thermal oxidation, form the second oxide layer, to repair the damage in etching process being prepared by bipolar transistor to district;
Synchronously oxide side wall is formed in described grid polycrystalline silicon both sides and described polysilicon emitter both sides;
Prepare district and bipolar transistor in CMOS transistor to prepare district's autoregistration simultaneously and inject heavy doping ion, prepare in district at described bipolar transistor, the substrate of described polysilicon emitter both sides forms extrinsic base region;
Carry out rapid thermal anneal process, the Doped ions in described polysilicon emitter is advanced, to form emitter junction.
2. the manufacture method of bipolar transistor as claimed in claim 1, it is characterized in that, the thickness of described second oxide layer is
3. the manufacture method of bipolar transistor as claimed in claim 1, it is characterized in that, the thickness of described polysilicon layer is
4. the manufacture method of bipolar transistor as claimed in claim 1, is characterized in that, when carrying out Doped ions to described polysilicon layer and injecting, the energy of the Doped ions of employing is 20KeV ~ 40KeV, and doping content is 4E15cm
-2~ 5E15cm
-2.
5. the manufacture method of bipolar transistor as claimed in claim 2, it is characterized in that, the time of described rapid thermal oxidation is 10s ~ 50s, and temperature is 1000 DEG C-1300 DEG C.
6. the manufacture method of bipolar transistor as claimed in claim 1, it is characterized in that, the energy of described heavy doping ion is 20 ~ 60KeV, and doping content is 1E15cm
-2~ 5E15cm
-2.
7. the manufacture method of bipolar transistor as claimed in claim 1, it is characterized in that, the annealing temperature of described rapid thermal anneal process is 1000 DEG C ~ 1100 DEG C, and annealing time is 5s-20s.
8. the manufacture method of bipolar transistor as claimed in claim 1, it is characterized in that, described bipolar transistor is NPN type or positive-negative-positive.
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| CN105097505B (en) * | 2014-04-21 | 2017-10-20 | 北大方正集团有限公司 | The method of the polysilicon emitter manufacture of transistor |
| CN105097507B (en) * | 2014-05-15 | 2018-06-05 | 北大方正集团有限公司 | A kind of polysilicon emitter transistor and preparation method thereof |
| CN105990135B (en) * | 2015-02-05 | 2018-12-07 | 北大方正集团有限公司 | polysilicon emitter transistor manufacturing method |
| CN106033743B (en) * | 2015-03-17 | 2019-04-02 | 北大方正集团有限公司 | BiCMOS integrated circuit manufacture method |
| CN107611034A (en) * | 2017-09-07 | 2018-01-19 | 复旦大学 | The preparation method of bipolar transistor based on two-dimensional semiconductor material |
| CN112071751B (en) * | 2020-11-11 | 2021-02-19 | 晶芯成(北京)科技有限公司 | A method of manufacturing a semiconductor device |
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| CN1957461A (en) * | 2004-05-25 | 2007-05-02 | 皇家飞利浦电子股份有限公司 | Semiconductor device and manufacturing method thereof |
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| JPH0474434A (en) * | 1990-07-17 | 1992-03-09 | Nec Corp | Manufacture of bi-cmos integrated circuit |
| JP3106492B2 (en) * | 1990-10-23 | 2000-11-06 | ソニー株式会社 | Method for manufacturing semiconductor device |
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