CN102118157B - Method and device for loading FPGA (Field Programmable Gate Array) - Google Patents

Abstract

The invention discloses a loading method of FPGA, comprising: loading part of the content of the FPGA, at this time, the FPGA cannot complete the inspection of the loaded content; monitoring whether the FPGA needs to be used, and if so, loading the content of the FPGA remaining content. The invention also discloses an FPGA loading device. Before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. FPGA power consumption is reduced without sacrificing efficiency.

Description

A kind of FPGA loading method and device

technical field

The invention relates to the field of electronic technology, in particular to an FPGA loading method and device.

Background technique

Field Programmable Gate Array (Field Programmable Gate Array, FPGA) has programming flexibility and high-speed hardware, so it is more and more widely used. With the development of semiconductor technology, the integration level of FPGA is getting higher and higher, and the power consumption of FPGA is also increasing.

With the continuous progress of society and the continuous development of science and technology, people now fully realize the importance of the environment to human development. All countries are taking active and effective measures to improve the environment and reduce pollution. The most important and urgent issue is energy. The problem, in addition to finding new energy sources, energy saving is the key and the most direct and effective important measure at present.

The power consumption of FPGA is increasing, which not only increases energy consumption, but also accelerates the aging of FPGA equipment. Therefore, how to reduce the power consumption of FPGA has become a technical hotspot and difficulty.

Contents of the invention

Embodiments of the present invention provide an FPGA loading method and device, which can reduce the power consumption of the FPGA.

The embodiment of the present invention provides a loading method of a field programmable gate array FPGA, comprising:

Loading part of the content of the FPGA, at this time the FPGA cannot complete the inspection of the loaded content;

It is monitored whether the FPGA needs to be used, and if so, the remainder of the FPGA is loaded.

The embodiment of the present invention also provides a loading device for FPGA, characterized in that, comprising:

The first loading unit is used to load part of the content of the FPGA, and now the FPGA cannot complete the inspection of the loaded content;

The first monitoring unit is used to monitor whether the FPGA loaded by the first loading unit needs to be used;

The second loading unit is configured to load the remaining content of the FPGA when the first monitoring unit detects that the FPGA needs to be used.

It can be seen from the above technical solutions that in the embodiment of the present invention, firstly load part of the content of the FPGA, and then monitor whether the FPGA needs to be used, and if so, load the remaining content of the FPGA. Before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When the need to use the FPGA is detected, only the remaining content of the FPGA needs to be loaded, and the loading can be completed in a short time. FPGA power consumption is reduced without sacrificing efficiency.

Description of drawings

Fig. 1 is a kind of FPGA loading method flowchart that the embodiment of the present invention provides;

Fig. 2 is another kind of FPGA loading method flowchart that the embodiment of the present invention provides;

Fig. 3 is another kind of FPGA loading method flowchart that the embodiment of the present invention provides;

Fig. 4 is another kind of FPGA loading method flowchart that the embodiment of the present invention provides;

Fig. 5 is a kind of FPGA loading device structural diagram provided by the embodiment of the present invention;

FIG. 6 is a structural diagram of another FPGA loading device provided by an embodiment of the present invention;

FIG. 7 is a structural diagram of another FPGA loading device provided by an embodiment of the present invention;

FIG. 8 is a structural diagram of another FPGA loading device provided by an embodiment of the present invention.

Detailed ways

In order to describe the present invention more clearly, below in conjunction with accompanying drawing and embodiment, specific embodiment of the present invention is described in further detail:

As shown in Figure 1, a kind of FPGA loading method provided for the embodiment of the present invention includes:

S100, loading part of the content of the FPGA;

Only part of the content is loaded, and the FPGA cannot complete the inspection of the loaded content. The power consumption of the FPGA is basically the same as the erase state, and it is in a low power consumption state.

S102, monitor whether the FPGA needs to be used, if yes, jump to S104, if not, continue monitoring;

Whether the FPGA needs to be used can be monitored by the CPU, and if it is not needed, continue monitoring, keep the state of S102, and jump to S104 if it needs to be used.

S104. Load remaining content of the FPGA.

After detecting that the FPGA needs to be used, start loading the remaining content of the FPGA. Since the remaining content of the FPGA is relatively small, the time to complete the loading is relatively short and will not affect the customer experience.

If the power consumption of the FPGA logic is set to 100% when all functions are implemented, after research, it is found that the power consumption of the FPGA logic is about 77% when it is loaded but no functions are implemented, and the power consumption when it is reset is about 60%. The power consumption at completion is about 6%, which is experimentally confirmed.

In this embodiment, S100 is directly implemented after power-on. In another embodiment, in order to ensure that the FPGA is successfully loaded, the FPGA is first erased after power-on, and then S100 is implemented. In another embodiment, when no FPGA is used , erase the FPGA, and implement S100.

Normally, the loading content, that is, the last part of the logic file contains a verification field, and the FPGA will run the logic only after completing the verification of the loaded content, so the loading can be stopped before the FPGA completes the verification of the loaded content, and the size of the remaining content can be It is determined according to the FPGA's requirements for the length of the check field, for example, it can be 1K Byte.

In this embodiment, before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. Loading is done, reducing FPGA power consumption without sacrificing efficiency.

As shown in Figure 2, a kind of FPGA loading method provided for the embodiment of the present invention includes:

S200, loading part of the content of the FPGA;

Only part of the content is loaded, and the FPGA's power consumption and erase state are basically the same, and it is in a low power consumption state.

S202, monitor whether the FPGA needs to be used, if yes, jump to S204, if not, continue monitoring;

Whether the FPGA needs to be used can be monitored by the CPU, and if it is not needed, continue monitoring, keep the state of S202, and jump to S204 if it needs to be used.

S204, load the remaining content of the FPGA;

After detecting that the FPGA needs to be used, start loading the remaining content of the FPGA. Since the remaining content of the FPGA is relatively small, the loading time is relatively short and will not affect the customer experience.

S206, initializing the FPGA;

After the loading of the remaining content of the FPGA is completed, the initialization operation of the FPGA can be performed, for example, the CPU writes the FPGA registers, etc.

After initialization, more functions can be realized, and existing technologies can be adopted, so details will not be repeated here.

S208, configure the FPGA.

It may be the configuration of related services, and the related services may be the types of services supported by the single board where the FPGA is located.

After configuration, more functions can be realized, and existing technologies can be adopted, so details will not be repeated here.

In this embodiment, before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. Loading is done, reducing FPGA power consumption without sacrificing efficiency.

As shown in Figure 3, a kind of FPGA loading method provided for the embodiment of the present invention includes:

S300, loading part of the content of the FPGA;

Only part of the content is loaded, and the FPGA's power consumption and erase state are basically the same, and it is in a low power consumption state.

S302, monitor whether the FPGA needs to be used, if yes, jump to S304, if not, continue monitoring;

Whether the FPGA needs to be used can be monitored by the CPU. If it is not needed, continue to monitor and keep the state of S302. If it needs to be used, jump to S304.

S304, load the remaining content of the FPGA;

After detecting that the FPGA needs to be used, start loading the remaining content of the FPGA. Since the remaining content of the FPGA is relatively small, the time to complete the loading is relatively short and will not affect the customer experience.

S306, initialize the FPGA;

After the loading of the remaining content of the FPGA is completed, the initialization operation of the FPGA can be performed, for example, the CPU writes the FPGA registers, etc.

More functions can be realized after initialization.

S308, configure the FPGA.

It may be the configuration of related services, and the related services may be the types of services supported by the single board where the FPGA is located.

More functions can be realized after configuration.

S310, monitor whether the FPGA needs to be used, if not, jump to S312;

If not, jump to S312, if yes, continue monitoring.

S312. Erase the content of the FPGA, and jump to S300.

Erase the contents of the FPGA. Generally, the FPGA has a hardware pin for erasing the contents. Enabling this pin can erase the contents of the FPGA.

Jump to S300 after erasing the content of the FPGA, and reload part of the content of the FPGA, which can be quickly loaded when the FPGA is needed.

In this embodiment, before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. Loading is done, reducing FPGA power consumption without sacrificing efficiency.

As shown in Figure 4, a kind of FPGA loading method provided for the embodiment of the present invention comprises:

S400, loading part of the content of the FPGA;

Only part of the content is loaded, and the FPGA's power consumption and erase state are basically the same, and it is in a low power consumption state.

S402, monitor whether the FPGA needs to be used, if yes, jump to S404, if not, continue monitoring;

Whether the FPGA needs to be used can be monitored by the CPU, if not used, continue to monitor, keep the state of S402, and jump to S404 if needed.

S404, load the remaining content of the FPGA;

After detecting that the FPGA needs to be used, start loading the remaining content of the FPGA. Since the remaining content of the FPGA is relatively small, the time to complete the loading is relatively short and will not affect the customer experience.

S406, initializing the FPGA;

After the loading of the remaining content of the FPGA is completed, the initialization operation of the FPGA can be performed, for example, the CPU writes the FPGA registers, etc.

More functions can be realized after initialization.

S408, configure the FPGA.

It may be the configuration of related services, and the related services may be the types of services supported by the single board where the FPGA is located.

More functions can be realized after configuration.

S410, monitor whether the FPGA needs to be used, if not, jump to S412;

S412, judging whether the time when the FPGA does not need to be used exceeds a preset value, if yes, jump to S414, if not, continue judging;

The preset value can be set according to requirements, for example, it can be one minute or one hour.

S414, erase the content of the FPGA, and jump to S400.

Erase the contents of the FPGA. Generally, the FPGA has a hardware pin for erasing the contents. Enabling this pin can erase the contents of the FPGA.

Jump to S400 after erasing the content of the FPGA, and reload part of the content of the FPGA, which can be quickly loaded when the FPGA is needed.

In this embodiment, before the FPGA needs to be used, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. Loading is done, reducing FPGA power consumption without sacrificing efficiency.

As shown in Figure 5, a loading device for FPGA provided by the embodiment of the present invention includes:

The first loading unit 500 is used to load part of the content of the FPGA, and now the FPGA cannot complete the inspection of the loaded content;

The first monitoring unit 502 is used to monitor whether the FPGA loaded by the first loading unit 500 needs to be used;

The second loading unit 504 is configured to load the remaining content of the FPGA when the first monitoring unit 502 detects that the FPGA needs to be used.

In this embodiment, before the FPGA loading device needs to use the FPGA, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. The loading is completed in a short time, which reduces the power consumption of the FPGA without sacrificing efficiency.

As shown in Figure 6, a loading device for FPGA provided by the embodiment of the present invention includes:

The first loading unit 600 is used to load part of the content of the FPGA, and now the FPGA cannot complete the inspection of the loaded content;

The first monitoring unit 602 is used to monitor whether the FPGA loaded by the first loading unit 600 needs to be used;

The second loading unit 604 is configured to load the remaining content of the FPGA when the first monitoring unit 602 detects that the FPGA needs to be used;

An initialization unit 606, configured to initialize the FPGA loaded by the second loading unit 604;

The configuration unit 608 is configured to configure the FPGA after initialization by the initialization unit 606 .

In this embodiment, before the FPGA loading device needs to use the FPGA, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. The loading is completed in a short time, which reduces the power consumption of the FPGA without sacrificing efficiency.

As shown in Figure 7, a loading device for FPGA provided by the embodiment of the present invention includes:

The first loading unit 700 is used to load part of the content of the FPGA, and at this time the FPGA cannot complete the inspection of the loaded content;

The first monitoring unit 702 is used to monitor whether the FPGA loaded by the first loading unit 700 needs to be used;

The second loading unit 704 is configured to load the remaining content of the FPGA when the first monitoring unit 702 detects that the FPGA needs to be used;

An initialization unit 706, configured to initialize the FPGA loaded by the second loading unit 704;

The configuration unit 708 is configured to configure the FPGA after initialization by the initialization unit 706;

The second monitoring unit 710 is used to monitor whether the configuration unit 708 needs to be used to configure the FPGA;

The first erasing unit 712 is configured to erase the contents of the FPGA when the second monitoring unit 710 detects that the FPGA is not needed.

The third loading unit 714 is used to load part of the content of the FPGA after erasing the content. At this time, the FPGA cannot complete the inspection of the loaded content;

The fourth monitoring unit 716 is used to monitor whether the FPGA loaded by the third loading unit 714 needs to be used;

The fourth loading unit 718 is configured to load the remaining content of the FPGA when the fourth monitoring unit 716 detects that the FPGA needs to be used.

Wherein, the third loading unit 714 and the first loading unit 700 may be the same unit or different units, and the sizes of the loaded partial contents may be different; the fourth monitoring unit 716 and the first monitoring unit 702 may be the same The units may also be different units; the fourth loading unit 718 and the second loading unit 704 may be the same unit or different units.

In this embodiment, before the FPGA loading device needs to use the FPGA, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. The loading is completed in a short time, which reduces the power consumption of the FPGA without sacrificing efficiency.

As shown in Figure 8, a loading device for FPGA provided by the embodiment of the present invention includes:

The first loading unit 800 is used to load part of the content of the FPGA. At this time, the FPGA cannot complete the inspection of the loaded content;

The first monitoring unit 802 is used to monitor whether the FPGA loaded by the first loading unit 800 needs to be used;

The second loading unit 804 is configured to load the remaining content of the FPGA when the first monitoring unit detects that the FPGA needs to be used;

An initialization unit 806, configured to initialize the FPGA loaded by the second loading unit 804;

The configuration unit 808 is configured to configure the FPGA after initialization by the initialization unit 806;

The third monitoring unit 810 is used to monitor whether the FPGA needs to be configured using the configuration unit 808;

The second erasing unit 812 is configured to erase the contents of the FPGA according to the monitoring result of the third monitoring unit 810 if the time that the FPGA is not required to be used exceeds a preset value.

The third loading unit 814 is used to load part of the content of the FPGA after erasing the content. At this time, the FPGA cannot complete the inspection of the loaded content;

The fourth monitoring unit 816 is used to monitor whether the FPGA loaded by the third loading unit 814 needs to be used;

The fourth loading unit 818 is configured to load the remaining content of the FPGA when the fourth monitoring unit detects that the FPGA needs to be used.

Wherein, the third loading unit 814 and the first loading unit 800 may be the same unit or different units; the fourth monitoring unit 816 and the first monitoring unit 802 may be the same unit or different units; The fourth loading unit 818 and the second loading unit 804 may be the same unit or different units.

In this embodiment, before the FPGA loading device needs to use the FPGA, the FPGA only loads part of the content. At this time, the power consumption of the FPGA is very small. When it is detected that the FPGA needs to be used, only the remaining content of the FPGA needs to be loaded. The loading is completed in a short time, which reduces the power consumption of the FPGA without sacrificing efficiency.

The information interaction between modules in the above-mentioned device, the execution process, etc., are based on the same concept as the method embodiment of the present invention, and the specific content can refer to the description in the method embodiment of the present invention, and will not be repeated here.

Through the above description of the implementations, those skilled in the art can clearly understand that each implementation can be implemented by means of software plus a necessary general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (11)

1. a loading method of field programmable gate array FPGA, is characterized in that, comprises: Loading part of the content of the FPGA, at this time the FPGA cannot complete the inspection of the loaded content; It is monitored whether the FPGA needs to be used, and if so, the remainder of the FPGA is loaded. 2. The method according to claim 1, characterized in that the size of the remaining content is determined according to the requirements of the FPGA for the check field length. 3. method according to claim 1, is characterized in that, after loading the remainder content of described FPGA also comprises: initializing the FPGA; Configure the FPGA. 4. method according to claim 3, is characterized in that, also comprises after carrying out the configuration of FPGA: monitoring whether the FPGA needs to be used; If not, the contents of the FPGA are erased. 5. method according to claim 3, is characterized in that, also comprises after carrying out the configuration of FPGA: monitoring whether the FPGA needs to be used; If the time that the FPGA does not need to be used exceeds a preset value, the content of the FPGA is erased. 6. according to the method described in claim 4 or 5, it is characterized in that, after erasing the content of described FPGA, also comprise: Loading part of the content of the FPGA, at this time the FPGA cannot complete the inspection of the loaded content; It is monitored whether the FPGA needs to be used, and if so, the remainder of the FPGA is loaded. 7. a loading device of FPGA, is characterized in that, comprises: The first loading unit is used to load part of the content of the FPGA, and now the FPGA cannot complete the inspection of the loaded content; The first monitoring unit is used to monitor whether the FPGA loaded by the first loading unit needs to be used; The second loading unit is configured to load the remaining content of the FPGA when the first monitoring unit detects that the FPGA needs to be used. 8. The device according to claim 7, further comprising: The initialization unit is used to initialize the FPGA after the second loading unit is loaded; The configuration unit is used to configure the FPGA after initialization by the initialization unit. 9. The device according to claim 8, further comprising: The second monitoring unit is used to monitor whether the configuration unit needs to be used to configure the FPGA; The first erasing unit is used for erasing the contents of the FPGA when the second monitoring unit detects that the FPGA is not needed. the 10. The device according to claim 8, further comprising: The third monitoring unit is used to monitor whether the configuration unit needs to be used to configure the FPGA; The second erasing unit is configured to, according to the monitoring result of the third monitoring unit, erase the content of the FPGA if the time that the FPGA is not required to be used exceeds a preset value. the 11. The device according to claim 9 or 10, further comprising: The third loading unit is used to load part of the content of the FPGA after erasing the content. At this time, the FPGA cannot complete the inspection of the loaded content; The fourth monitoring unit is used to monitor whether the FPGA loaded by the third loading unit needs to be used; The fourth loading unit is configured to load the remaining content of the FPGA when the fourth monitoring unit detects that the FPGA needs to be used. the

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