CN102118151A - Clock circuit of integrated circuit - Google Patents

Abstract

The invention provides an integrated circuit clock circuit having a capability of withstanding variations in temperature, ground voltage, or power supply voltage, for example. An improved clock integrated circuit can address one or more of temperature, ground voltage, or supply voltage variations in various embodiments.

Description

IC clock circuit

technical field

The present invention relates to integrated circuits with clock circuits that are tolerant to variations such as temperature, ground noise, power supply noise, and the like.

Background technique

The operation of the clock circuit of an integrated circuit will vary with factors such as temperature, ground noise, and power supply noise. Since these variations will affect the final timing of the output clock signal, a number of studies have been conducted to address this issue and produce a more uniform output clock signal in the presence of the above variations.

For example, US Pat. No. 7,142,005 to Gaboury uses a buffer circuit with an active load, independent bias circuitry, and bias circuitry to isolate the clock signal from power fluctuations. In order to isolate the impact of power supply fluctuations on the clock signal, these relatively complex buffer circuits cause a significant increase in die area and cost.

Hence the need to address these variations, but with a less complex structure and less cost

Contents of the invention

The present invention is a technique to provide a device with a clock integrated circuit.

The clock integrated circuit has a latch for generating a clock signal output of the clock integrated circuit. The latch includes cross-coupled logic gates such that an output of the cross-coupled logic gate in the latch is coupled to an input of a different cross-coupled logic gate in the latch.

The clock IC also has a timing circuit coupled to an output of the latch, an output of the timing circuit switches between a first reference signal and a second reference signal at a rate determined by a Determined by the temperature-dependent time constant. The output of the timing circuit determines the timing of the clock signal output.

The clock integrated circuit also has an inverting circuit for comparing an output of the timing circuit with a temperature compensation reference value, so that the timing of the clock signal output of the clock integrated circuit can withstand temperature fluctuations, and an output of the inverting circuit coupled with an input of the latch.

In some embodiments, the time constant is an exponential signal.

In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the timing circuit is charged from the first reference voltage to the second reference voltage state and a state of discharging from the second reference voltage to the first reference voltage.

In some embodiments, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the sequential circuit, in response to the inverting circuit, The state of charging to the second reference voltage is switched between the state of discharging from the second reference voltage to the first reference voltage. Wherein the temperature compensation trigger point of the inverting circuit is a third reference voltage, which decreases with increasing temperature. In one embodiment, the temperature-compensated trigger point of the inverter circuit is generated by a temperature-compensated power supply.

Another object of the present invention is to provide a device with a clock integrated circuit in which the inverter is replaced by a Schmitt trigger circuit.

Another object of the present invention is to provide a device with a clock integrated circuit, the inverter is replaced by an operational amplifier circuit, and a current generator type reference circuit is added to generate the temperature compensation reference value.

In many different embodiments, the reference circuit of the current generator type is a current generator and a resistive characteristic device including any of a resistor, a diode, and a metal-oxide-semiconductor transistor; and some other device such as a A device having at least one of CTAT (inversely proportional to temperature) and PTAT (proportional to temperature) characteristics.

Another object of the present invention is to provide a device with a clock integrated circuit, including a latch to generate a clock signal output of the clock integrated circuit. The latch includes a first logic gate and a second logic gate mutually coupled to each other. An output of the first logic gate is coupled to a first input of the second logic gate. An output of the second logic gate is coupled to a first input of the first logic gate. The output of the second logic gate is coupled to a second input of the first logic gate through at least one first sequential circuit and a first inverter. The output of the first logic gate is coupled to a second input of the second logic gate via at least a second sequential circuit and a second inverter.

The first sequential circuit has an output that switches between a first reference signal and a second reference signal at a first rate determined by a first temperature-dependent time constant.

The second timing circuit has an output that switches between the first reference signal and the second reference signal at a second rate determined by a second time constant that is temperature dependent.

The outputs of the first timing circuit and the second timing circuit determine the timing of the clock signal output.

The first inverter compares an output of the first sequential circuit with a first temperature compensation reference value, which is a first temperature compensation trigger point of the first inverter.

The second inverter compares an output of the second timing circuit with a second temperature compensation reference value, which is a second temperature compensation trigger point of the second inverter.

In one embodiment, the first reference signal is a first reference voltage, the second reference signal is a second reference voltage, and the first timing circuit and the second timing circuit are charging from the first reference voltage Switching between a state to the second reference voltage and a state of discharging from the second reference voltage to the first reference voltage. In one embodiment, the temperature compensation reference value is a third reference voltage which decreases with increasing temperature.

In one embodiment, the first and second time constants are an exponential signal.

In one embodiment, the first and second temperature compensation reference values are generated from a common reference circuit.

In one embodiment, the first and second temperature compensation reference values are generated from different reference circuits.

Another object of the present invention is to provide a device with a clock integrated circuit in which the array inverter is replaced by an array Schmitt trigger circuit.

Another object of the present invention is to provide a device with a clock integrated circuit, in which the array inverter is replaced by an array operational amplifier circuit, and a current generator type reference circuit is added to generate the temperature compensation reference value.

Description of drawings

Objects, features and embodiments of the present invention are described in the accompanying drawings in the following embodiments section, in which:

FIG. 1 shows a schematic block diagram of an integrated circuit clock circuit with tolerance to variations such as temperature, ground voltage, or supply voltage.

Figure 2A and Figure 2B show a schematic circuit diagram of an integrated circuit clock circuit with the ability to withstand temperature fluctuations, which includes an inverter circuit to evaluate the output of the timing circuit, wherein Figure 2A has a capacitive timing circuit coupled to ground and 2B Figure has a capacitive sequential circuit coupled to a power supply.

Figure 2C shows a schematic circuit diagram of an integrated circuit clock circuit with tolerance to temperature fluctuations, similar to Figure 2A, but receiving power from a PTAT power supply instead of a CTAT power supply.

FIG. 2D shows a schematic circuit diagram of an integrated circuit clock circuit capable of withstanding temperature fluctuations, which includes a Schmitt trigger circuit to evaluate the output of the timing circuit.

FIG. 2E shows a schematic diagram of a Schmitt trigger circuit, such as that in FIG. 2D.

3A and 3B show a schematic circuit diagram of an integrated circuit clock circuit with the ability to withstand temperature fluctuations, which includes an operational amplifier circuit to perform level detection of the output of the timing circuit by comparing the output with a reference value, where the figure 3A has the capacitive timing circuit coupled to ground and FIG. 3B has the capacitive sequential circuit coupled to power.

FIG. 4A shows a schematic circuit diagram of a reference signal for a level detection circuit, which includes a PTAT current source with a current output that decreases as temperature increases.

FIG. 4B shows a schematic circuit diagram of a reference signal for a level detection circuit, which includes a CTAT current source with an output current that increases with temperature.

4C shows a schematic circuit diagram of a reference signal of a level detection circuit, which includes a PTAT current source with a current output that decreases as temperature increases, and further has a capacitor connected in parallel with a load resistor of a current mirror.

4D is a schematic diagram of a current generator that provides PTAT current from a PMOS device according to a reference circuit.

4E is a schematic diagram of a current generator that provides PTAT current from an NMOS device according to a reference circuit.

4F is a schematic diagram of a current generator that provides CTAT current from a PMOS device according to a reference circuit.

4G is a schematic diagram of a current generator that provides CTAT current from an NMOS device according to a reference circuit.

FIG. 5A shows a schematic circuit diagram of a reference signal of a level detection circuit, which includes a current source with a current output that decreases with increasing temperature, and an output that decreases with increasing temperature.

FIG. 5B shows a circuit diagram of a reference signal of a level detection circuit, which includes a current source with an output that increases with temperature, and an output that increases with temperature.

5C shows a schematic circuit diagram of a reference signal for a level detection circuit, which includes a current source with a current output that decreases as temperature increases, and an output that increases as temperature increases.

5D shows a schematic circuit diagram of a reference signal for the level detection circuit of FIG. 5C, but including a current source with a current output that increases with temperature.

FIG. 5E is a variation of the circuit of FIG. 5C in which CTAT_I constant current source 526 is replaced by resistor RES524.

FIG. 6A shows a set of trajectory curves of the relationship between time and rise, which shows how the clock circuit has the ability to withstand temperature fluctuations, and the timing of its generated clocks can be greatly changed as the temperature changes.

Figure 6B shows a set of time vs. ramp magnitude traces showing how this clock circuit is tolerant to temperature fluctuations, since using the circuits shown in Figures 2 to 5 produces clock timing that is substantially independent of temperature. Change to change.

FIG. 7A shows a set of trajectory curves of the relationship between time and drop magnitude, which shows how the clock circuit has the ability to withstand temperature fluctuations, and the timing of its generated clocks can be greatly changed as the temperature changes.

Figure 7B shows a set of time vs. droop magnitude traces showing how this clock circuit is tolerant to temperature fluctuations, since using the circuits shown in Figures 2 to 5, it produces clock timing that does not vary substantially with temperature. Change and change.

8A and 8B show a schematic circuit diagram of an integrated circuit clock circuit with the ability to withstand fluctuations in ground noise, which includes a transistor selectively coupled to ground noise as a reference signal for level detection output by the timing circuit A portion of FIG. 8A where FIG. 8A has a capacitive sequential circuit coupled to ground and FIG. 8B has a capacitive sequential circuit coupled to power.

FIG. 9 is a set of voltage versus time graphs showing how the clock circuit is tolerant to variations in ground noise, generating clock timings that can vary significantly with respect to ground noise that varies over time.

Figure 10 is a set of voltage versus time graphs showing how this clock circuit is tolerant to variations in ground noise, which because of the circuit in Figure 8 can produce a relatively stable response to ground noise that varies over time clock timing.

11A and 11B show a schematic circuit diagram of an integrated circuit clock circuit with power supply noise tolerance capability, which includes a transistor and the power supply noise of the sequential circuit power supply and the power supply noise of the reference signal for level detection output by the sequential circuit. Shared noise phase where FIG. 11A has the capacitive timing circuit coupled to ground and FIG. 11B has the capacitive timing circuit coupled to power.

FIG. 12 shows a circuit diagram of a power supply circuit, which shares the same noise phase with the power supply noise of the sequential circuit power supply and the power supply noise of the level detection reference signal output by the sequential circuit.

FIG. 13 is a set of relationship diagrams of voltage and time, which shows how to have the same relationship between the power supply of the sequential circuit and the reference signal used for the level detection of the output of the sequential circuit because of the circuit relationship in FIG. 11 or FIG. 12 noise phase.

FIG. 14 is a set of voltage versus time graphs showing how the clock circuit is tolerant to power supply noise variations, which can generate clock timing in response to power supply noise that varies greatly over time.

Figure 15 is a set of voltage versus time graphs showing how this clock circuit is tolerant to variations in power supply noise, because the circuits in Figures 11 and 12 can withstand large variations in power supply noise over time produces relatively stable clock timings.

16A and 16B show a schematic circuit diagram of an integrated circuit clock circuit with power supply noise tolerance capability, which includes a transistor and the power supply noise of the sequential circuit power supply and the power supply noise of the reference signal for level detection output by the sequential circuit. Shared noise phase, similar to Figure 11, with the addition of switching circuitry to selectively bypass the noise tolerant circuitry, for example at power-on.

FIG. 17 is a schematic block diagram of a memory circuit with an improved integrated circuit clock circuit to which the present invention can be applied.

FIG. 18 is a circuit diagram, similar to FIG. 16, showing a schematic circuit diagram of an integrated circuit clock circuit with tolerance to power supply noise variations, and also includes switching circuits between the reference generator and the operational amplifier.

Detailed ways

FIG. 1 shows a schematic block diagram of an integrated circuit clock circuit with tolerance to variations such as temperature, ground voltage, or supply voltage.

The integrated circuit clock circuit is usually a one-loop structure with a timing circuit 102 , a level switching circuit 104 and a latch circuit 106 . The latch circuit latch circuit 106 generates a feedback signal from the latch circuit latch circuit 106 to the sequential circuit 102 and a clock output signal 110 . The timing circuit 102 switches between the two reference signals according to a time constant. This time constant thus determines the timing of the integrated circuit clock circuit. A typical example of a time constant is an exponential time constant, which characterizes the rise and fall times of an RC circuit or RL circuit. The level switching circuit monitors the output of the timing circuit 102 and changes its output according to whether the timing circuit 102 is high or low enough. Examples of the latch circuit 106 are SR latches, SR NAND latches, JK latches, gated SR latches, gated D latches, gated trigger latches, and the like. The latch circuit 106 has two stable states and switches between these two stable states to generate a clock output signal 110 .

The two reference signals that the timing circuit 102 relies on are generated by the circuit 116 , which also generates the level switching reference signal that the level switching circuit 104 relies on. By simultaneously generating the dependent reference signal for the sequential circuit 102 and the dependent level switching reference signal for the level switching circuit 104, the circuit 116 can reduce the number of reference signals that the sequential circuit 102 depends on and the level switching circuit 104. Level-dependent switching of the noise phase of the noise signal shared by the reference signal. Because any noise phase is very small, the peaks and valleys of the noise signal in the reference signal on which the timing circuit 102 depends are synchronized with the peaks and valleys of the noise signal in the level switching reference signal that the level switching circuit 104 depends on .

The level switching reference signal 112 that the level switching circuit 104 relies on is selected by the circuit 118 and coupled to the level switching circuit 104 . In some embodiments, this will hold ground noise as a sample, so the same ground noise will be held by the sequential circuit 102 and will be held by the level switching reference circuit on which the level switching circuit 104 relies. live.

While the block diagrams shown here can account for variations in temperature, ground voltage, or supply voltage, an improved clock circuit in various embodiments of the present invention addresses only one of these variable parameters (eg, only for temperature noise, ground voltage noise only, or supply voltage noise only), or just two of these varying parameters (e.g., temperature and supply voltage noise only, temperature and ground voltage noise only, or supply voltage noise only and ground voltage noise).

2A and 2B show a circuit diagram of an integrated circuit clock circuit capable of withstanding temperature fluctuations, which includes an inverting circuit to evaluate the output of the timing circuit.

The figure shows sequential circuits 202A and 202B placed in parallel, inverting circuits 204A and 204B placed in parallel, and a latch circuit 206 . The timing circuits 202A and 202B are generally an inverter with a resistor RX or RY, which charges or discharges from a capacitor CX or CY to change the output voltage of OX or OY.

FIG. 2A shows an embodiment in which capacitor CX or CY is coupled to a common ground. Although not all possible variations are shown in the figure, the technique of the present invention includes sequential circuits with capacitors CX or CY in all embodiments, wherein the sequential circuits can be modified to couple the capacitors CX or CY to a common ground.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor with opposite terminals decoupled from the common ground of the inverter.

FIG. 2B shows an embodiment in which the capacitor CX or CY is coupled to a common power source. Although not all possible variations are shown in the figure, the technology of the present invention includes the sequential circuit with capacitor CX or CY in all embodiments, wherein the sequential circuit can be modified to couple the capacitor CX or CY to a common power source.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor with opposite terminals decoupled from the common power supply terminal of the inverter.

The inverting circuits 204A and 204B are driven by a CTAT power supply or a power supply that is inversely proportional to temperature, which decreases as temperature increases.

This inverter is very different from the op amp version. In the op-amp version, a Vref is compared to the output of a sequential circuit (such as the rise/fall of an RC circuit). And in the inverter version, the power supply of the inverter is controlled to change the stroke of the inverter and thus detect the output of the sequential circuit (such as rising/falling of the RC circuit). In this inverter version, an additional temperature dependence of the power supply versus the inverter trip is taken into account.

This inverter has the following advantages over the op-amp version: (1) lower operating voltage VDD; (2) smaller circuit size (the inverter has only two MOS transistors while the op-amp has five MOS transistors or more); (3) simpler design; (4) lower active current (inverters have one current path, while op amps have two or three current paths and include an additional current mirror); and (5) higher operating speed (an inverter has a delay of one stage, while an operational amplifier has a delay of two or three stages).

The latch circuit 206 is reciprocally coupled such that the output of one logic gate is coupled to the input of another logic gate. One input of a logic gate is directly coupled with the output of another logic gate, and the other input of the logic gate is directly coupled with the output of another logic gate via a timing circuit and a level detection circuit.

FIG. 2C shows another embodiment of the sequential circuit. Although largely similar to FIG. 2A, sequential circuits 202A and 202B placed in parallel in FIG. 2C are driven by a PTAT power supply or a temperature-proportional power supply that increases with temperature. Although not all possible variations are shown in the figure, the technique of the present invention includes sequential circuits with CTAT power in all embodiments, wherein the CTAT power can be replaced by a PTAT power.

Similarly, although not all possible variations are shown in the figure, the technology of the present invention includes sequential circuits with PTAT power in all embodiments, wherein the PTAT power can be replaced by CTAT power.

FIG. 2D shows a schematic circuit diagram of an integrated circuit clock circuit capable of withstanding temperature fluctuations, which includes a Schmitt trigger circuit to evaluate the output of the timing circuit.

Although similar in FIG. 2B , the Schmitt trigger circuits of level switching circuits 210A and 210B in FIG. 2D are driven by a CTAT power supply and include operational amplifiers with closed loop positive feedback through resistors.

FIG. 2E shows a schematic diagram of a Schmitt trigger circuit.

FIG. 3 shows a schematic circuit diagram of an integrated circuit clock circuit capable of withstanding temperature fluctuations, which includes an operational amplifier circuit to perform level detection of the output of the timing circuit by comparing the output with a reference value.

The figure shows timing circuits 302A and 302B placed in parallel, level switching circuits 304A and 304B placed in parallel, and a latch circuit 306 . The level switching circuits 304A and 304B are operational amplifier comparators with a reference voltage CTAT_REF. Otherwise, the clock circuit is roughly similar to that of FIG. 2A.

FIG. 4A shows a schematic circuit diagram of a reference signal of a level detection circuit, which includes a current source with an output current that increases with temperature.

FIG. 4A shows how the CTAT power supply signal, shown as CTAT_REF 428 in this figure, is generated depending on the level detection circuit. A PTAT_I current source 426 with quantitative output will generate a current proportional to the temperature from the power regulator 422 through the resistor RES 424, which increases as the temperature increases. The power regulator 422 outputs a constant voltage independent of temperature. This regulated power supply provides certain power and does not change with VDD and temperature. For example, the output of the regulator has a band reference value. The output is inversely proportional to temperature, since the voltage drop across the resistor increases as temperature increases, and the offset of the output terminal below this voltage drop decreases. An example of this current source is shown in Figure 4E.

4B is a variation of the circuit of FIG. 4A, wherein the PTAT_I constant current source 426 is replaced by a CTAT_I constant current source 430, and the CTAT_REF 428 dependent on the CTAT power signal of the level detection circuit is replaced by the PTAT power signal of the level detection circuit. PTAT_REF 432 superseded. An example of this current source is shown in Figure 4G.

Figure 4C is a variation of the circuit of Figure 4A with a bypass capacitor 434 in parallel with resistor RES 424 to reduce noise. Additionally, the current source includes a current mirror. An example of this current source is shown in Figure 4D.

4D is a schematic diagram of a current generator that provides PTAT current from a PMOS device according to a reference circuit.

4E is a schematic diagram of a current generator that provides PTAT current from an NMOS device according to a reference circuit.

In Figures 4D and 4E, this circuit uses delta_Vg between two NMOS transistors with the same current proportional to temperature. So delta_Vg/resistance = PTAT_I. In Figure 4D and Figure 4E, the two transistors with circles are the same.

4F is a schematic diagram of a current generator that provides CTAT current from a PMOS device according to a reference circuit.

4G is a schematic diagram of a current generator that provides CTAT current from an NMOS device according to a reference circuit.

A current generator according to the reference circuit described here is preferred because in many embodiments a single temperature-dependent parameter can be controlled rather than two temperature-dependent material-dependent parameters with different temperature dependence.

FIG. 5A shows a schematic circuit diagram of a reference signal for a level detection circuit, which includes a current source with a current output that decreases as temperature increases.

FIG. 5A shows how the CTAT power signal, shown as CTAT_REF 528 in this figure, is generated depending on the level detection circuit. A PTAT_I current source 526 with quantitative output will generate a current that is inversely proportional to temperature from the power regulator 522 through the resistor RES 524, and decreases as the temperature increases. This output is inversely proportional to temperature, since the voltage drop across the resistor decreases as temperature increases, and the offset of the output terminal above this voltage drop also decreases.

One example of the current source shown is a cascaded current source.

5B, 5C, 5D and 5E are other examples of generating the reference voltage signal.

5B is a variation of the circuit of FIG. 5A, wherein the CTAT_I constant current source 526 is replaced by the PTAT_I constant current source 530, and the CTAT_REF 528 dependent on the CTAT power signal of the level detection circuit is replaced by the PTAT power signal of the level detection circuit. PTAT_REF 532 superseded.

FIG. 5C is a variation of the circuit of FIG. 5A in which resistor RES 524 is replaced by diode DIO 530. An example of this current source is shown in Figure 4F.

5D is a variation of the circuit of FIG. 5A, wherein CTAT_I constant current source 526 is replaced by PTAT_I constant current source 530, and the offset of the output terminals is moved from the voltage drop across the upper end of the constant current source to the voltage drop across the lower end of the constant current source. pressure drop.

FIG. 5E is a variation of the circuit of FIG. 5, wherein CTAT_I constant current source 526 is replaced by resistor RES524.

FIG. 6A shows a set of trace curves of the relationship between time and magnitude, which shows how the clock circuit has the ability to withstand temperature fluctuations, and the timing of its generated clocks can be greatly changed as the temperature changes.

Figure 6A shows a high temperature, a low temperature and a medium temperature trajectory interval. The lower the temperature, the faster the sequential circuit becomes, and the higher the temperature, the slower the sequential circuit becomes. Due to the common reference signal of the sequential circuit, the sequential circuit will reach the reference value faster at low temperature than at high temperature. Therefore, the timing of this clock circuit will be faster at low temperatures than at high temperatures.

Figure 6B shows a set of time versus magnitude traces showing how this clock circuit is tolerant to temperature fluctuations, since using the circuits shown in Figures 2 to 5, it produces clock timing that does not substantially change with temperature And change.

Figure 6B shows a high temperature, a low temperature and a medium temperature trajectory interval. As shown in FIG. 6A , the lower the temperature, the faster the sequential circuit becomes, and the higher the temperature, the slower the sequential circuit becomes. However, because a different sequential circuit is used in FIG. 6B, it is different from the sequential circuit used in FIG. 6A. Although the sequential circuit reaches the reference value faster at low temperature than at high temperature, the reference value of the sequential circuit is relatively higher. Therefore, the timing of the clock circuit exhibits little temperature variation, but results in a speed variation of the clock circuit.

Figures 7A and 7B are other embodiments showing a falling signal instead of the rising signal in Figures 6A and 6B, but still showing the same time constant.

A clock signal depends on the rising signal in FIGS. 6A and 6B or the falling signal in FIGS. 7A and 7B, and is based on whether the capacitor CX or CY is coupled to the ground in FIG. 2A or to the power supply in FIG. 2B. It depends.

8A and 8B show a schematic circuit diagram of an integrated circuit clock circuit with the ability to withstand fluctuations in ground noise, which includes a transistor selectively coupled to ground noise as a reference signal for level detection output by the timing circuit a part of.

The figure shows timing circuits 802A and 802B placed in parallel, level switching circuits 804A and 804B placed in parallel, and a latch circuit 806 . The level-switching circuits 804A and 804B are selectively coupled to ground noise from the level-switching reference circuits 816A and 816B and stored at capacitor nodes REF X or REF Y, respectively, according to switching transistors turned on by signal ENX 818A and the switching behavior of the switching transistor 818B turned on by the signal ENY is determined. This will hold the ground noise as a sample, so the same ground noise will be held by the sequential circuit 802A or 802B, and will be held by the node REF X or REF of the level switching reference circuit on which the level switching circuit 104 depends. Y is kept.

In one embodiment, the capacitor CX or CY is actually a PMOS transistor with opposite terminals decoupled from a common power supply connected to RX or RY.

OX remains grounded when ENX is high. Afterwards, ENX goes low to turn off the NMOS; at this time the ground noise is kept at OX. If the noise is high, the precharge is fast; if the noise is low, the precharge is slow. This circuit allows REFX or REFY to maintain the same ground noise at the same time.

In FIG. 8A, the switching reference circuit is referenced to node REFX or REFY, and includes a capacitor circuit coupled to ground. In FIG. 8B, the switching reference circuit is referenced to node REFX or REFY, and includes a capacitor circuit coupled to a power supply.

In different embodiments, the level switching reference circuits 816A and 816B can be two different groups of circuits or the same group of circuits can be shared by parallel sequential circuits and multiple level switching circuits 804A and 804B.

FIG. 9 is a set of voltage versus time graphs showing how the clock circuit is tolerant to variations in ground noise, generating clock timings that can vary significantly with respect to ground noise that varies over time.

Figure 9 shows how traces OX and OY are affected by ground noise, in this case the REF_LO signal. When there is a peak of the ground noise, the timing circuit will start charging from REF_LO to REF_HI, so that the timing circuit only takes less time to charge from REF_LO to REF_HI. Therefore, the clock signal output 910 has a wider variation in the clock cycle.

When ENX is high, OX remains grounded and the voltage varies with ground noise. When ENX is low and NMOS is turned off, the ground noise is kept at OX. But the reference level still fluctuates with ground noise. The worst case is that OX maintains a high level of ground noise and the reference circuit suffers a negative ground level during charging; then the reference value will be much lower than expected. Thus a similar sample and hold structure maintains the same ground noise at REFX or REFY.

Figure 10 is a set of voltage versus time graphs showing how this clock circuit is tolerant to variations in ground noise, which because of the circuit in Figure 8 can produce a relatively stable response to ground noise that varies over time clock timing.

Figure 10 shows how traces OX and OY are affected by ground noise, in this case the REF_LO signal. When the ground noise has a peak or other change, the peak or other change will be stored at the capacitor node REF X or REF Y in FIG. 8 . Because the influence of ground noise on the REF_LO signal is tracked by the sample-and-hold reference circuit, the level detection circuit is self-level detection reference circuit and the sequential circuit compares the same ground noise. After the ground noise is taken in this sample-and-hold manner, the ground noise, which continues to change, is decoupled from the sampling circuit. Therefore, the timing circuit does not start early in the process of charging from REF_LO to REF_HI. Although there is ground noise, the timing circuit still needs the same time to charge from REF_LO to REF_HI. As a result, the clock signal output 910 has the same clock period over a widely varying ground noise.

In another embodiment, the ground noise is sampled and then decoupled from the sampling circuit during discharge, instead of decoupling the ground noise from the sampling circuit during charging as shown in Figures 9 and 10. Decoupling. This embodiment creates additional problems because the power supply noise generated by the noisy power supply regulator must be addressed.

In another embodiment (similar to FIG. 2C ), the sample and hold circuit would hold power supply noise instead of ground noise.

11A and 11B show a schematic circuit diagram of an integrated circuit clock circuit with power supply noise tolerance capability, which includes a transistor and the power supply noise of the sequential circuit power supply and the power supply noise of the reference signal for level detection output by the sequential circuit. shared noise phase.

The figure shows timing circuits 1102A and 1102B placed in parallel, level switching circuits 1104A and 1104B placed in parallel, and a latch circuit 1106 . As shown in the figure, it also includes timing power supply and level switching reference value generators 1116A and 1116B, which generate the same noise phase as the power supply noise of the timing circuit power supply and the power supply noise of the level detection reference signal output by the timing circuit.

In FIG. 11A, the capacitive circuit CX or CY is coupled to ground. In FIG. 11B , the capacitive circuit CX or CY is coupled to a power source 1116A or 1116B.

FIG. 12 shows a circuit diagram of a power supply circuit, which shares the same noise phase with the power supply noise of the sequential circuit power supply and the power supply noise of the level detection reference signal output by the sequential circuit.

FIG. 12 shows a power supply 1236 driving an operational amplifier 1232 . The operational amplifier has a reference signal REF_OP 1234 at its non-inverting input. An example of this REF_OP 1234 is a bandgap reference circuit at 1.3V. A MOSFET 1238 has a logic gate coupled to the output of the operational amplifier 1232 , a drain coupled to the power supply 1236 , and a source coupled to the sequential power output 1246 . The timing power output 1246 and the level switching reference value 1248 are separated by a resistor R1 1240. The level switching reference value 1248 is separated from the negative feedback point of the operational amplifier 1232 by a resistor R2 1242. Finally, resistor R3 couples this negative feedback point to ground.

Another embodiment uses capacitive coupling of floating nodes to maintain the same noise phase between timing power output 1246 and level switching reference 1248 , where one of timing power output 1246 and level switching reference 1248 is floating. .

While the above embodiments are specifically designed to maintain the same noise phase between the sequential power output 1246 and the level switch reference 1248 , this is not the case in other designs. Other designs have different noise phases between the timing power output 1246 and the level switching reference 1248 for one or more of the following reasons: (1) because the die configuration makes the reference circuit not close to the timing circuit; (2) the reference circuit in the regulator has a better Power Supply Rejection Ratio (PSRR) than the VDD supply; and (3) even with an RC supply with a power regulator, a noise phase difference still remains due to different output loads and transitions. will be maintained, and the power regulator must support larger currents and larger output transitions.

FIG. 13 is a set of relationship diagrams of voltage and time, which shows how to have the same relationship between the power supply of the sequential circuit and the reference signal used for the level detection of the output of the sequential circuit because of the circuit relationship in FIG. 11 or FIG. 12 noise phase.

FIG. 13 shows that the power supply noise between the sequential circuit power supply 1301 and the reference signal used for the level detection of the sequential circuit output 1302 has the same noise phase. Placing trace 1303 on top of traces 1301 and 1302 shows that although the magnitude of the power supply noise varies, the peaks and valleys of the power supply noise for traces 1301 and 1302 are synchronized.

FIG. 14 is a set of voltage versus time graphs showing how the clock circuit is tolerant to power supply noise variations, which can generate clock timing in response to power supply noise that varies greatly over time.

FIG. 14 shows how traces OX and OY are affected by power supply noise 1401 . When the power supply noise drops sharply, the timing circuit will start charging from REF_LO to REF_HI, so that the timing circuit can charge from REF_LO to REF_HI in less time. Similarly, when the power supply noise has a peak value, the charging process of the timing circuit from REF_LO to REF_HI will become slower, causing the timing circuit to take more time to charge from REF_LO to REF_HI. These changes occur after a stable (fixed) level switching reference. Therefore, the clock signal output 1410 has a wider variation in the clock cycle.

Figure 15 is a set of voltage versus time graphs showing how this clock circuit is tolerant to variations in power supply noise, because the circuits in Figures 11 and 12 can withstand large variations in power supply noise over time produces relatively stable clock timings.

FIG. 15 shows how traces OX and OY are affected by ground noise 1401 . The difference from FIG. 14 is that when the power supply noise 1501 has a peak or other changes, the level switching reference value has a synchronous peak or other changes. Although the peak or other variation in the level switching reference will have a small magnitude compared to the power supply noise, the synchronous nature between the sequential circuit power supply 1501 and the level switching reference greatly reduces the clock signal changes. Therefore, the clock signal output 1510 still has a common clock period in the presence of wide variations in ground noise.

16A and 16B show a schematic circuit diagram of an integrated circuit clock circuit with the ability to withstand power supply noise fluctuations to switch the power supply of the clock. When the power supply is turned on, if it has not yet reached a stable power supply and needs this VDD power supply to generate a clock for the logic circuit. The logic circuit waits for a settling time for a stable power supply. When a stable power supply is reached, the clock is switched to a stable clock.

The figure shows timing circuits 1602A and 1602B placed in parallel, level switching circuits 1604A and 1604B placed in parallel, and a latch circuit 1606 . As shown in the figure, it also includes timing power supply and level switching reference value generators 1616A and 1616B, which generate the same noise phase as the power supply noise of the timing circuit power supply and the power supply noise of the level detection reference signal output by the timing circuit. The diagram also includes a switch 1620A between VDD and the timing power supply and level switching reference value generator 1616A, a switching switch 1620B between VDD and the timing power supply and level switching reference value generator 1616B, and a switching switch 1620B between VDD and the timing power supply and level switching reference value generator 1616B. A switch 1620C between the level switching circuit 1604A and the latch circuit 1606 , and a switch 1620D between the level switching circuit 1604B and the latch circuit 1606 .

In FIG. 16A, this capacitive circuit CX or CY is coupled to ground. In FIG. 16B, the capacitive circuit CX or CY is coupled to a power source 1616A or 1616B.

FIG. 17 is a schematic block diagram of a memory circuit with an improved integrated circuit clock circuit to which the present invention can be applied.

FIG. 17 is a simplified block diagram of an integrated circuit 1700 including a memory array 1712 . A word line/block select decoder and driver 1714 is coupled to, and in electrical communication with, a plurality of word lines 1716 and string select lines arranged along the column direction of the memory cell array 1712 . The bit line (row) decoder 1718 is coupled to a plurality of bit lines 1720 arranged along the rows of the memory array 1712 and is in electrical communication with them for reading data from or writing data to, the memory cell array 1712 storage unit. Addresses are provided to word line and block select decoder 1714 and bit line decoder 1718 via bus 1722 . Sense amplifiers and data input structures in block 1724 , including current sources for read, program and erase modes, are coupled to bit line decoder 1718 via bus 1726 . Data is sent from I/O ports on integrated circuit 1710 to the data input structure of block 1724 via data input line 1728 . In the illustrated embodiment, other circuits 1730 are also included in the integrated circuit 1710, such as general purpose processors or special purpose circuits, or combination modules supported by the memory array to provide system-on-a-chip functionality. Data is sent by the sense amplifier in block 1724 via data output line 1732 to an input/output port on integrated circuit 1700 or other data destination within or outside integrated circuit 1700 . The state machine and improved clocking circuitry (as discussed herein) are in circuit 1734 .

FIG. 18 is a circuit diagram, similar to FIG. 16, showing a schematic circuit diagram of an integrated circuit clock circuit with tolerance to power supply noise variations, and also includes switching circuits between the reference generator and the operational amplifier. As shown in FIG. 8, the switching transistor 818A is turned on by the signal ENX and the switching transistor 818B is turned on by the signal ENY. Similar to FIG. 8 , the ground noise from the sequential power supply and level switching generators 1616A and 1616B is stored in the capacitive node REFX or REFY.

Although the present invention has been described with reference to the embodiments, the inventive concept is not limited by the detailed description. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. In particular, all combinations of components that are substantially the same as those of the present invention to achieve substantially the same results as the present invention do not depart from the scope of the present invention. Therefore, all such alternatives and modifications are intended to fall within the category defined by the claims of the present invention and their equivalents.

Claims (38)

1. integrated circuit (IC) apparatus comprises:

One clock integrated circuit comprises:

One bolt lock device, produce the clock signal output of this integrated circuit of clock, this bolt lock device comprises the gate that couples alternately, and so the input of the output of this gate that couples alternately in this bolt lock device and this Different Logic door that couples alternately in this bolt lock device couples;

Sequence circuit, couple with an output of this bolt lock device, one output of this sequence circuit is switched between one first reference signal and one second reference signal, one speed of this switching is to decide with the time constant of temperature correlation by one, wherein the sequential of this this clock signal output of output decision of this sequence circuit;

Negative circuit, relatively this output and a temperature-compensating trigger point of this negative circuit of this sequence circuit, so this sequential of this clock signal output of this integrated circuit of clock can be kept out temperature change, and an output of this negative circuit couples with an input of this bolt lock device.

2. integrated circuit (IC) apparatus as claimed in claim 1, wherein this time constant is an exponential signal.

3. integrated circuit (IC) apparatus as claimed in claim 1, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit responds this negative circuit, and charge to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage.

4. integrated circuit (IC) apparatus as claimed in claim 1, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage, and

Wherein this temperature-compensating trigger point of this negative circuit is one the 3rd reference voltage, and it increases and reduce along with temperature.

5. integrated circuit (IC) apparatus as claimed in claim 1, wherein this temperature-compensating trigger point of this negative circuit is produced by a temperature-compensating power supply.

6. integrated circuit (IC) apparatus comprises:

One clock integrated circuit comprises:

One bolt lock device, produce the clock signal output of this integrated circuit of clock, this bolt lock device comprises the gate that couples alternately, and so the input of the output of this gate that couples alternately in this bolt lock device and this Different Logic door that couples alternately in this bolt lock device couples;

Sequence circuit, couple with an output of this bolt lock device, one output of this sequence circuit is switched between one first reference signal and one second reference signal, one speed of this switching is to decide with the time constant of temperature correlation by one, wherein the sequential of this this clock signal output of output decision of this sequence circuit;

Schmidt trigger circuit, relatively this output and a temperature-compensating reference value of this sequence circuit, so this sequential of this clock signal output of this integrated circuit of clock can be kept out temperature change, and an output of this Schmidt trigger circuit couples with an input of this bolt lock device.

7. integrated circuit (IC) apparatus as claimed in claim 6, wherein this time constant is an exponential signal.

8. integrated circuit (IC) apparatus as claimed in claim 6, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage.

9. integrated circuit (IC) apparatus as claimed in claim 6, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage, and

Wherein this temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

10. integrated circuit (IC) apparatus comprises:

One clock integrated circuit, it comprises:

One bolt lock device, produce the clock signal output of this integrated circuit of clock, this bolt lock device comprises the gate that couples alternately, and described in this bolt lock device couples the output of gate alternately and the described input that couples another person of gate alternately in this bolt lock device couples;

Sequence circuit, couple with an output of this bolt lock device, one output of this sequence circuit is switched with a speed between one first reference signal and one second reference signal, this speed is to decide with a time constant of temperature correlation by one, the sequential of this this clock signal output of output decision of this sequence circuit;

Operational amplification circuit is this output and a temperature-compensating reference value of this sequence circuit relatively, so this sequential of this clock signal output of this integrated circuit of clock can be resisted the variation of temperature, and an output of this operational amplification circuit couples with an input of this bolt lock device; And

The reference circuit of one current generator type is for producing this temperature-compensating reference value.

11. integrated circuit (IC) apparatus as claimed in claim 10, wherein this time constant is an exponential signal.

12. integrated circuit (IC) apparatus as claimed in claim 10, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage.

13. integrated circuit (IC) apparatus as claimed in claim 10, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this sequence circuit charges to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage, and

Wherein this temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

14. integrated circuit (IC) apparatus as claimed in claim 10, wherein the reference circuit of this current generator type comprises a current generator and a resistance characteristic device, this resistance characteristic device comprise a resistance, diode and a metal-oxide semiconductor transistorized any.

15. integrated circuit (IC) apparatus as claimed in claim 10, wherein the reference circuit of this current generator type be one have with temperature inverse ratio characteristic and with the positive specific characteristic of temperature device one of at least.

16. integrated circuit (IC) apparatus as claimed in claim 10, wherein the reference circuit of this current generator type comprises a diode, its critical voltage have one with temperature inverse ratio characteristic.

17. integrated circuit (IC) apparatus as claimed in claim 1, wherein this bolt lock device comprises one first gate and one second gate couples each other alternately, and is coupled to:

One output of this first gate couples with one first input of this second gate;

One output of this second gate couples with one first input of this first gate;

One second input of this output of this second gate and this first gate couples via at least one first sequence circuit and one first inverter;

One second input of this output of this first gate and this second gate couples via at least one second sequence circuit and one second inverter;

This sequence circuit comprises:

This first sequence circuit has an output and switches with a first rate between one first reference signal and one second reference signal, this first rate be by one and the very first time constant of temperature correlation decide;

This second sequence circuit has an output and switches with one second speed between this first reference signal and this second reference signal, this second speed be by one and one second time constant of temperature correlation decide;

Wherein the described output of this first sequence circuit and this second sequence circuit determines the sequential of this clock signal output;

This negative circuit comprises:

This first inverter is this output and one first temperature-compensating reference value of this first sequence circuit relatively; And

This second inverter is this output and one second temperature-compensating reference value of this second sequence circuit relatively.

18. integrated circuit (IC) apparatus as claimed in claim 17, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage.

19. integrated circuit (IC) apparatus as claimed in claim 17, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage one from this first reference voltage, and one switches between this second reference voltage is discharged to the state of this first reference voltage, and

Wherein this first and second temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

20. integrated circuit (IC) apparatus as claimed in claim 17, wherein this first and second time constant is an exponential signal.

21. integrated circuit (IC) apparatus as claimed in claim 17, wherein this first and second temperature-compensating reference value is to produce from a common reference circuit.

22. integrated circuit (IC) apparatus as claimed in claim 17, wherein this first and second temperature-compensating reference value is to produce from different reference circuits.

23. integrated circuit (IC) apparatus as claimed in claim 6, wherein:

This bolt lock device comprises one first and one second and couples alternately each other, and is coupled to:

One output of this first gate couples with one first input of this second gate;

One output of this second gate couples with one first input of this first gate;

One second input of this output of this second gate and this first gate couples via at least one first sequence circuit and one first Schmidt trigger circuit;

One second input of this output of this first gate and this second gate couples via at least one second sequence circuit and one second Schmidt trigger circuit;

This sequence circuit comprises:

This first sequence circuit has an output and switches with a first rate between one first reference signal and one second reference signal, this first rate be by one and the very first time constant of temperature correlation decide;

This second sequence circuit has an output and switches with one second speed between this first reference signal and this second reference signal, this second speed be by one and one second time constant of temperature correlation decide;

Wherein the described output of this first sequence circuit and this second sequence circuit determines the sequential of this clock signal output;

This Schmidt trigger circuit comprises:

This first Schmidt trigger circuit is this output and one first temperature-compensating reference value of this first sequence circuit relatively; And

This second Schmidt trigger circuit is this output and one second temperature-compensating reference value of this second sequence circuit relatively.

24. integrated circuit (IC) apparatus as claimed in claim 23, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and are discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch.

25. integrated circuit (IC) apparatus as claimed in claim 23, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and are discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch, and

Wherein this first and second temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

26. integrated circuit (IC) apparatus as claimed in claim 23, wherein this first and second time constant is an exponential signal.

27. integrated circuit (IC) apparatus as claimed in claim 23, wherein this first and second temperature-compensating reference value is to produce from a common reference circuit.

28. integrated circuit (IC) apparatus as claimed in claim 23, wherein this first and second temperature-compensating reference value is to produce from different reference circuits.

29. integrated circuit (IC) apparatus as claimed in claim 10, wherein

This bolt lock device comprises one first gate and one second gate couples each other alternately, and is coupled to:

One output of this first gate couples with one first input of this second gate;

One output of this second gate couples with one first input of this first gate;

One second input of this output of this second gate and this first gate couples via at least one first sequence circuit and one first operational amplifier;

One second input of this output of this first gate and this second gate couples via at least one second sequence circuit and one second operational amplifier;

This sequence circuit comprises:

This first sequence circuit has an output and switches with a first rate between one first reference signal and one second reference signal, this first rate be by one and the very first time constant of temperature correlation decide;

This second sequence circuit has an output and switches with one second speed between this first reference signal and this second reference signal, this second speed be by one and one second time constant of temperature correlation decide;

Wherein the described output of this first sequence circuit and this second sequence circuit determines the sequential of this clock signal output;

This operation amplifier circuit comprises:

This first operational amplifier is this output and one first temperature-compensating reference value of this first sequence circuit relatively; And

This second operational amplifier is this output and one second temperature-compensating reference value of this second sequence circuit relatively; And

Wherein the reference circuit of this current generator type produces this first temperature-compensating reference value and this second temperature-compensating reference value.

30. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and are discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch.

31. integrated circuit (IC) apparatus as claimed in claim 29, wherein the reference circuit of this current generator type is that a current generator has a resistance characteristic device, this resistance characteristic device comprise a resistance, diode and a metal-oxide semiconductor transistorized any.

32. integrated circuit (IC) apparatus as claimed in claim 29, wherein the reference circuit of current generator type be one have with temperature inverse ratio characteristic and with the positive specific characteristic of temperature device one of at least.

33. integrated circuit (IC) apparatus as claimed in claim 29, wherein the reference circuit of this current generator type be a diode have a critical voltage have one with temperature inverse ratio characteristic.

34. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first reference signal is one first reference voltage, this second reference signal is one second reference voltage, and this first sequence circuit and this second sequence circuit charge to the state of this second reference voltage and are discharged to from this second reference voltage between the state of this first reference voltage at this first reference voltage certainly and switch, and

Wherein this first and second temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

35. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first and second temperature-compensating reference value is one the 3rd reference voltage, and it increases and reduce along with temperature.

36. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first and second time constant is an exponential signal.

37. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first and second temperature-compensating reference value is to produce from a common reference circuit.

38. integrated circuit (IC) apparatus as claimed in claim 29, wherein this first and second temperature-compensating reference value is to produce from different reference circuits.

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