CN102117796A - Copper interconnection structure of integrated circuit and preparation method thereof - Google Patents
Copper interconnection structure of integrated circuit and preparation method thereof Download PDFInfo
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- CN102117796A CN102117796A CN2011100306278A CN201110030627A CN102117796A CN 102117796 A CN102117796 A CN 102117796A CN 2011100306278 A CN2011100306278 A CN 2011100306278A CN 201110030627 A CN201110030627 A CN 201110030627A CN 102117796 A CN102117796 A CN 102117796A
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Abstract
本发明属于微电子技术领域，具体为一种集成电路铜互连结构及其制备方法。本发明利用CoxMoy合金层作为Cu扩散阻挡层/粘附层/籽晶层，x、y的取值范围为0.1-0.9,x和y之和为1。制备步骤为：在衬底上直接用PVD，CVD或者ALD技术淀积一层CoxMoy合金，然后沉积Cu籽晶层或直接电镀铜，得到铜互连结构。调节Co、Mo配比可获得较佳的Cu扩散阻挡性能和粘附性能。本发明利用Co、Mo合金做扩散阻挡层，粘附层和电镀籽晶层，不仅提高了Cu阻挡和粘附性能，并保证其在集成电路铜互连应用中的可靠性。所用方法简单、方便、实用性强。
The invention belongs to the technical field of microelectronics, in particular to an integrated circuit copper interconnection structure and a preparation method thereof. The present invention utilizes the Co x Mo y alloy layer as the Cu diffusion barrier layer/adhesion layer/seed layer, the value range of x and y is 0.1-0.9, and the sum of x and y is 1. The preparation steps are as follows: directly depositing a layer of Co x Mo y alloy on the substrate by PVD, CVD or ALD technology, and then depositing a Cu seed layer or directly electroplating copper to obtain a copper interconnection structure. Adjusting the ratio of Co and Mo can obtain better Cu diffusion barrier performance and adhesion performance. The invention uses Co and Mo alloys as the diffusion barrier layer, adhesion layer and electroplating seed layer, which not only improves Cu barrier and adhesion performance, but also ensures its reliability in the application of copper interconnection in integrated circuits. The method used is simple, convenient and practical.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of novel integrated circuit copper interconnecting structure and preparation method thereof.
Background technology
Along with device size further dwindles, for attenuate Cu diffusion barrier layer thickness, increase the interconnection line conductivity, the research of ultra-thin Cu diffusion impervious layer/adhesion layer/inculating crystal layer more and more comes into one's own.The TaN/Ta double-decker has been used as Cu diffusion impervious layer/adhesion layer/inculating crystal layer widely in large scale integrated circuit.Yet, along with the integrated circuit size continue reduce, in order to make that electroplating Cu can have good filling characteristic, and assurance good reliability, the thickness of diffusion impervious layer/adhesion layer/inculating crystal layer of requirement Cu is extremely thin, according to international semiconductor development course ITRS2009 upgraded edition, at the 32nm technology node, about the thickness 2.6nm of diffusion impervious layer, be further reduced to about 1.3nm at the 15nm node.Seek existing good Cu diffusion barrier performance, the material that good Cu adhesion property is arranged again is the focus of studying at present.Alloy diffusion barrier layer // adhesion layer is very potential material.
Summary of the invention
The purpose of this invention is to provide a kind of novel integrated circuit copper interconnecting structure and preparation method thereof.
Integrated circuit copper interconnecting structure provided by the invention is to utilize the alloy of Co and Mo as Cu diffusion impervious layer/adhesion layer/inculating crystal layer, and wherein, the expression formula of the alloy of Co and Mo is Co
xMo
y, x and y are respectively the constituent contents of Co and Mo, span is 0.05-0.95, X and Y's and be 1.
The preparation method of integrated circuit copper interconnecting structure provided by the invention, its concrete steps are: directly use PVD, CVD or ALD deposition techniques one deck Co on substrate
xMo
yAlloy deposits Cu inculating crystal layer or Direct Electroplating copper then, obtains copper interconnection structure.
In the said method, also can on substrate, utilize PVD, CVD or ALD deposition techniques one deck diffusion impervious layer earlier, such as TaN, nitride such as TiN; And then deposit one deck Co
xMo
yAlloy deposits Cu inculating crystal layer or Direct Electroplating copper at last, obtains copper interconnection structure.
In the said method, at deposit Co
xMo
yDuring alloy-layer, can adopt Co target and Mo target co-sputtering technology, or adopt Co, Mo alloy target material, perhaps in the first body of atomic layer deposition, use the first body of two kinds of metal Co, Mo, by the method acquisition alloy in mixed source.
Co of the present invention
xMo
yThe alloy diffusion barrier layer is at medium or Si or SiO
2Deposit Co on the substrate
xMo
yAlloy is as Cu diffusion impervious layer/adhesion layer/inculating crystal layer, and the method for deposit comprises any methods such as atomic layer deposition, chemical vapor deposition, physical vapor deposition.As when adopting this physical vapor deposition method of sputter, can adopt the method for many target co-sputterings, promptly Co target and Mo target both can adopt the RF rf magnetron sputtering, also can adopt the DC magnetically controlled DC sputtering.Also can adopt single Co
xMo
yAlloys target is as the target source.Sputter remains the method that present lsi technology prepares the main flow of interconnect barrier/inculating crystal layer.When adopting the atomic layer deposition method, when first body adopts organic metal oxide source, adopt the first body of two kinds of metals, utilize the method for mixing first body to prepare Co, Mo alloy.Continue preparation copper film with sputtering method or electro-plating method at last, finish one deck interconnection process.
The present invention can obtain best Cu diffusion barrier performance and adhesion property by adjusting Co, Mo proportioning according to actual needs, and this layer can be used as Cu and electroplates inculating crystal layer simultaneously.
If system wishes to have better diffusion impervious layer characteristic, also can be at Co
xMo
yThe diffusion impervious layer for preparing the ultra-thin TaN of one deck or other nitride between alloy-layer and the dielectric layer with PVD or ALD.Every Co that utilizes
xMo
yAlloy is in the Cu sandwich construction, all in protection range of the present invention.
Description of drawings
Fig. 1. sample structure schematic diagram, Cu/Co
xMo
yAlloy/Si or medium.
Fig. 2. sample structure schematic diagram, Cu/Co
xMo
yAlloy/TaN/Si or medium.
Fig. 3. sample Cu (30nm)/Co (5nm)/TaN (5nm)/Si surface C u is at (a) 400
oC (b) 500
oC (c) 600
oC 30 min N
2SEM figure after the atmosphere annealing.
Fig. 4. sample Cu (30nm)/Co
0.5Mo
0.5(5nm)/TaN (5nm)/Si surface C u is at (a) 400
oC (b) 500
oC (c) 600
oC 30 min N
2SEM figure after the atmosphere annealing.
Fig. 5. sample Cu (50nm)/Co (5nm)/Si, Cu (50nm)/Co
0.3Mo
0.7(5nm), Cu (50nm)/Co
0.3Mo
0.7(10nm)/Si, and the sheet resistance change of Cu (50nm)/Mo (5nm)/Si after different temperatures annealing.
Fig. 6. substrate Cu (3nm)/Co
0.5Mo
0.5(10nm)/Si electroplates the SEM of inculating crystal layer after electroplating Cu as Cu and schemes.
Embodiment
Below in conjunction with accompanying drawing enforcement of the present invention is further described by way of example, but the present invention is not limited only to example.
(1) at Si or SiO
2Perhaps on the dielectric substrate, deposit TaN/Co
xMo
yDouble-layer alloy diffusion impervious layer/adhesion layer/inculating crystal layer, in the sputter procedure, the film of the low more preparation of base vacuum has good more quality.The base vacuum degree that this example provides is 3 * 10
-5Pa.Feed Ar gas during deposit.Operating air pressure is between 0.1Pa – 1Pa.In deposit TaN, feed N
2As reacting gas, operating air pressure is between 0.1Pa – 1Pa.The ratio of Co/Mo obtains by the sputtering power of regulating Co target and Mo target.This example has adopted three ratios, and Co:Mo is 0.3:0.7,0.5:0.5; 0.7:0.3.Control film thickness by the control deposition time.The thickness of diffusion impervious layer is relevant with the semiconductor technology requirement, can be from 50 nanometers-3 nanometer.The film thickness that this example adopts is TaN (5nm)/Co
xMo
y(5nm).
(2) use the sputtering method cement copper again.The thickness of copper film is between the 30-100 nanometer.The structure that above-mentioned three step backs form is seen accompanying drawing 1.
Adopt Co
xMo
yDo the Cu adhesion layer, comparison diagram 3 and SEM shown in Figure 4 scheme as can be seen, and after Cu on the Co layer was annealed, the cavity appearred in the surface, and at Co
xMo
yThe Cu of layer has the surface of good pattern, shows Co
xMo
yLayer has good adhesion property to Cu.
(3) at Si or SiO
2Perhaps on the dielectric substrate, deposit Co
xMo
ySingle layer alloy diffusion impervious layer/adhesion layer/inculating crystal layer, in the sputter procedure, base vacuum is low more, and the film of preparation has good more quality.The base vacuum degree that this example provides is 3 * 10
-5Pa.Feed Ar gas during deposit.Operating air pressure is between 0.1Pa – 1Pa.The ratio of Co/Mo obtains by the sputtering power of regulating Co target and Mo target.The ratio that Fig. 5 adopts in this example is Co
0.3Mo
0.7Control film thickness by the control deposition time.The thickness of diffusion impervious layer is relevant with the semiconductor technology requirement, can be from 50 nanometers-3 nanometer.The film thickness that this example adopts is 5nm.
(4) use the sputtering method cement copper again.The thickness of copper film is between the 30-100 nanometer.The structure that above-mentioned three step backs form is seen accompanying drawing 2.
Adopt Co
xMoy does the Cu diffusion impervious layer, from the sample of Fig. 5 sheet resistance after different temperatures annealing as can be seen, and Co
xMo
yFilm obviously is better than Co, Mo single-layer metal film to the Cu diffusion barrier performance.
(5) at Si or SiO
2Perhaps on the dielectric substrate, deposit Co
xMo
ySingle layer alloy, in the sputter procedure, the film of the low more preparation of base vacuum has good more quality.The base vacuum degree that this example provides is 3 * 10
-5Pa.Feed Ar gas during deposit.Operating air pressure is between 0.1Pa – 1Pa.The ratio of Co/Mo obtains by the sputtering power of regulating Co target and Mo target.Control film thickness by the control deposition time.The thickness of diffusion impervious layer is relevant with the semiconductor technology requirement, can be from 50 nanometers-3 nanometer.The film thickness that this example adopts is 10nm.
(6) use the extremely thin copper of sputtering method deposit again, in order to protection Co
xMo
yThe surface.That adopt in this example is Co
0.5Mo
0.5Alloy.The thickness of copper film is between the 1-10 nanometer.The thickness that this example adopted is 3nm.
(7) utilize electric plating method deposit Cu again.The sample overall structure is similar with Fig. 1.
Adopt Co
xThe Moy alloy is done the Cu diffusion impervious layer, and the SEM figure after electroplating Cu finds out from Fig. 6 sample, and CoMo can be used as good Cu and electroplates inculating crystal layer.
Comparative example 1
After having prepared diffusion barrier material TaN, under the situation of uninterrupted vacuum, utilize physical vapor deposition (PVD) method cosputtering Co film.Base vacuum is low more good more, and the base vacuum degree that this example provides is 5 * 10
-5Pa.Feed Ar gas during deposit, operating air pressure is 0.22 Pa.Come control thickness by the control deposition time, the Co film thickness that adopts in this example is 5nm.Cement copper 30nm-50nm then.The SEM test result of sample as shown in Figure 3.The sheet resistance test result of sample as shown in Figure 5, Co as can be seen
xMo
y(5nm) individual layer is better than Co to the diffusion barrier performance of Cu (5nm is as diffusion impervious layer.From the SEM picture of sample as can be seen, Co is bad to the adhesiveness of Cu, and a large amount of holes appear in the copper surface after annealing.
Claims (4)
1. an integrated circuit copper interconnecting structure is characterized in that, the alloy that utilizes Co and Mo is as Cu diffusion impervious layer/adhesion layer/inculating crystal layer, and wherein, the expression formula of Co and Mo alloy is Co
xMo
y, x and y are respectively the constituent contents of Co and Mo, and span is 0.05-0.95, and x and y sum are 1.
2. the preparation method of an integrated circuit copper interconnecting structure as claimed in claim 1 is characterized in that concrete steps are: directly use PVD, CVD or ALD deposition techniques one deck Co on substrate
xMo
yAlloy deposits Cu inculating crystal layer or Direct Electroplating copper then, obtains copper interconnection structure.
3. the preparation method of integrated circuit copper interconnecting structure according to claim 2 is characterized in that at substrate and Co
xMo
yGo back deposit one diffusion impervious layer between the alloy-layer, this diffusion barrier material is a nitride.
4. according to the preparation method of claim 2 or 3 described integrated circuit copper interconnecting structures, it is characterized in that at deposit Co
xMo
yDuring alloy-layer, adopt Co target and Mo target co-sputtering technology, or adopt Co, Mo alloy target material, perhaps in the first body of atomic layer deposition, use the first body of two kinds of metal Co, Mo, by the method acquisition alloy in mixed source.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299598A (en) * | 2020-02-24 | 2021-08-24 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method |
Citations (5)
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|---|---|---|---|---|
| CN1233856A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | Copper interconnection structure incorporating metal seed layer |
| US6144096A (en) * | 1998-10-05 | 2000-11-07 | Advanced Micro Devices, Inc. | Low resistivity semiconductor barrier layers and manufacturing method therefor |
| US6420189B1 (en) * | 2001-04-27 | 2002-07-16 | Advanced Micro Devices, Inc. | Superconducting damascene interconnected for integrated circuit |
| US20060251872A1 (en) * | 2005-05-05 | 2006-11-09 | Wang Jenn Y | Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof |
| CN101714521A (en) * | 2008-09-30 | 2010-05-26 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
-
2011
- 2011-01-28 CN CN2011100306278A patent/CN102117796A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1233856A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | Copper interconnection structure incorporating metal seed layer |
| US6144096A (en) * | 1998-10-05 | 2000-11-07 | Advanced Micro Devices, Inc. | Low resistivity semiconductor barrier layers and manufacturing method therefor |
| US6420189B1 (en) * | 2001-04-27 | 2002-07-16 | Advanced Micro Devices, Inc. | Superconducting damascene interconnected for integrated circuit |
| US20060251872A1 (en) * | 2005-05-05 | 2006-11-09 | Wang Jenn Y | Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof |
| CN101714521A (en) * | 2008-09-30 | 2010-05-26 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113299598A (en) * | 2020-02-24 | 2021-08-24 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method |
| US12119260B2 (en) | 2020-02-24 | 2024-10-15 | Changxin Memory Technologies, Inc. | Methods for manufacturing semiconductor structures including isolation layer and semiconductor structures including isolation layer |
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Application publication date: 20110706 |