CN102117261B - Communication method between inner processors of chip - Google Patents
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- CN102117261B CN102117261B CN200910250832.8A CN200910250832A CN102117261B CN 102117261 B CN102117261 B CN 102117261B CN 200910250832 A CN200910250832 A CN 200910250832A CN 102117261 B CN102117261 B CN 102117261B
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Abstract
The invention discloses a communication method between inner processors of a chip. As the communication between the processors is realized by a shared data region formed by a plurality of data storage blocks, each shared data region is provided with a read pointer, a write pointer and an interrupt resource, wherein a transmitting data processor can write data in an idle data storage block of the shared data region, modifies the write pointer to direct at the next idle data storage block, and transmits interrupts to inform a receiving data processor; and the receiving data processor responds to the interrupts, processes data in unprocessed data storage blocks in the shared data region according to instructions of the read pointer and the write pointer, modifies the read pointer and finishes the data receiving. The technical scheme of the invention can realize the data communication between two processors by utilizing a pair of interrupts, reduces the occupancy of interrupt resources in a system, and avoids delay data processing or data loss caused by coverage or loss of the interrupts.
Description
Technical field
The present invention relates to a kind of communication means between inner processors of chip.
Background technology
Along with the development of chip technology; arrange multiple processor at single chip internal to be widely used in present chip technology to run different application software respectively; such as; in the baseband chip of mobile terminal; usually an arm processor and multiple dsp processor can be comprised; wherein, arm processor is used for operation system, application layer software, protocol stack sofeware etc., and dsp processor is for running physical layer software.
Usually interaction data is needed between different application software, if multiple application software is run on the different processors respectively, the data interaction realized between them just needs to realize the communication between different processors, for the baseband chip of mobile terminal, need between protocol stack and Physical layer to carry out data interaction frequently, and generally operate on arm processor due to protocol stack, and physical layer software generally operates on dsp processor, therefore, in fact the data interaction between protocol stack and Physical layer depends on the communication between ARM and DSP.
Communication between existing techniques in realizing chip internal different processor adopts the mode of sharing data area to realize usually:
1, the sharing data area of multiple DSB data store block composition is set between the processor needing interaction data;
2, for each DSB data store block distributes an interrupt resources;
3, send the processor of data and data are write an idle DSB data store block;
4, send the processor of data and send interruption corresponding to this DSB data store block to the processor receiving data;
5, the interruption that the processor that the processor response receiving data sends data sends;
6, the data in the DSB data store block of the processor process interruption correspondence of data are received;
There are following 2 problems in the implementation method of prior art:
1, mutual between processor data volume is very large, time very intensive, also corresponding meeting is a lot of for the DSB data store block needed, and above-mentioned implementation method distributes an interrupt resources for each DSB data store block, like this, a lot of system break resources can be taken, cause the waste of system break resource.
2, when the data throughout of inter-processor communication is very large, system break can be very frequent, like this, may there is the situation of interrupting losing, covering, above-mentioned implementation method may cause the data in some or multiple DSB data store block can not be received the problem that even cannot be received in time in this case.
Such as, with the HSPA business in TDSCDMA system, in data interaction extreme case data transportation requirements 5 milliseconds between the arm processor of the baseband chip in data service procedures and dsp processor, data throughout is at 15kbits, the primitives interoperation number of times limit 6 times between every 5 milliseconds, two-way each 3 times.This intensive primitives interoperation causes the situation interrupting covering, losing possibly, thus causes primitive not to be received in time even to lose primitive.
Summary of the invention
In view of this, the present invention proposes the communication means between a kind of inner processors of chip, take too much system break resource and data can not be timely received the problem of even losing to solve in prior art to exist.
Technical scheme of the present invention comprises,
A kind of inner processors of chip sends the method for data to other processors:
Steps A, between processor and each processor that need receive the data that it sends, be respectively provided to few 1 sharing data area, each sharing data area is made up of n DSB data store block;
Wherein, n be greater than 1 integer;
Step B, a read pointer, a write pointer and an interrupt resources are set for each sharing data area;
The DSB data store block that wherein read pointer instruction is next pending, write pointer indicates next idle data storage block;
According to read pointer and write pointer, step C, processor judge whether corresponding sharing data area also has idle data storage block;
If the available free DSB data store block in step D sharing data area, data are write idle data storage block according to the instruction of write pointer and revise write pointer by processor;
Step e, processor send and interrupt, and the processor that notice need receive data receives data.
Further, described step C comprises:
Processor judges that whether DSB data store block that read pointer points to is the next DSB data store block of the DSB data store block pointed by write pointer, if so, judges in sharing data area without idle data storage block; If not, judge the available free DSB data store block in sharing data area.
Wherein, if the DSB data store block pointed by write pointer is last DSB data store block of sharing data area, its next DSB data store block is first DSB data store block of sharing data area.
Further, described step D comprises:
Data are write the DSB data store block pointed by write pointer by processor;
Amendment write pointer makes it point to next DSB data store block;
Wherein, if the DSB data store block pointed by write pointer is last DSB data store block of sharing data area, its next DSB data store block is first DSB data store block of sharing data area.
A kind of inner processors of chip receives the method for data from other processors:
Processor reads data from sending the sharing data area of data processor to its transmission data;
The response of steps A, processor sends the interruption that data processor sends over;
Step B, processor judge whether there are untreated data in this sharing data area according to the read pointer and write pointer that interrupt corresponding sharing data area;
If step C has untreated data, processor, according to the data in the DSB data store block of read pointer sharing data area corresponding to write pointer process, revises read pointer;
If step D does not have untreated data, processor does not process.
Further, described step B comprises:
Processor compares read pointer and the write pointer of this sharing data area;
If read pointer is less than write pointer, untreated DSB data store block comprises a upper DSB data store block of DSB data store block pointed by DSB data store block pointed by read pointer to write pointer; If read pointer is greater than write pointer, untreated DSB data store block comprises data block that read pointer the points to upper DSB data store block to DSB data store block pointed by last data block in territory, sharing data area and first data block to write pointer in territory, sharing data area; If read pointer equals write pointer, there is no untreated data block.
Further, described step C comprises: processor compares read pointer and the write pointer of this sharing data area;
Processor reads the data in all untreated DSB data store block; Amendment read pointer is the DSB data store block number of read pointer+this process.
Further, described step C comprises:
Data in processor process untreated DSB data store block;
Judge whether read pointer points to this DSB data store block;
If read pointer points to this DSB data store block, judge whether untreated DSB data store block in addition; If there is untreated DSB data store block, amendment read pointer, makes it point to next untreated DSB data store block; If do not have untreated DSB data store block, amendment read pointer, makes it point to DSB data store block pointed by write pointer;
If read pointer does not point to this DSB data store block, be processed by this data block identifier;
Wherein, whether in addition the determination range of described untreated DSB data store block is, if read pointer is less than write pointer, and a upper DSB data store block of determination range DSB data store block pointed by this DSB data store block to write pointer; If read pointer is greater than write pointer, a upper DSB data store block of determination range DSB data store block pointed by this DSB data store block to last data block in territory, sharing data area and first data block to write pointer in territory, sharing data area.
Technical scheme of the present invention is that each sharing data area arranges a read pointer and a write pointer respectively to indicate the service condition of each DSB data store block in this sharing data area, be only each sharing data area and distribute an interrupt resources, send the processor of data after each DSB data store block data write in sharing data area, send the processor that same interrupt notification receives data, when the processor of reception data responds this interruption, the all untreatment data storage blocks in data sharing data field can be processed, like this, even if larger in data interaction handling capacity, there is the covering interrupted, during loss, also the situation that maybe cannot receive data not in time of data receiver can effectively be avoided.
Accompanying drawing explanation
Fig. 1 is communication means process flow diagram between prior art chip internal different processor
Fig. 2 is the specific embodiment of the invention 1 process flow diagram
Fig. 3 is the specific embodiment of the invention 2 process flow diagram
Fig. 4 is the specific embodiment of the invention 3 process flow diagram
Embodiment
For clearly demonstrating technical scheme of the present invention, providing preferred embodiment below and being described with reference to the accompanying drawings.
The application scenarios of the preferred embodiments of the present invention 1,2,3 is the communication process between the inner arm processor of mobile communication terminal baseband chip and dsp processor, in each preferred embodiment, send intercommunication primitive for arm processor to dsp processor for ARM is provided with a sharing data area BUFFER_A2D comprising n DSB data store block in advance; Send intercommunication primitive for dsp processor to arm processor for DSP is provided with a sharing data area BUFFER_D2A comprising n DSB data store block, n be greater than 1 integer.
Specific embodiment 1
The present embodiment application scenarios is that in mobile communication terminal baseband chip, arm processor sends intercommunication primitive to dsp processor, idiographic flow as shown in Figure 2:
In the present embodiment, arm processor sends intercommunication primitive by BUFFER_A2D to dsp processor;
For BUFFER_A2D arranges a read pointer CPD_R, a write pointer CPA_W and interrupt resources MB_A2D;
In the present embodiment, read pointer and write pointer initial value all point to first DSB data store block, i.e. CPD_R=CPD_R=1 of sharing data area;
1, after data send and start, when arm processor sends intercommunication primitive at every turn, first detect sharing data area and whether also have idle data storage block;
Arm processor judges whether (CPA_W%n)+1 equals CPD_R, if perform step 6, otherwise performs step 4;
2, data are write idle data storage block according to the instruction of write pointer and revise write pointer by arm processor;
The DSB data store block of the intercommunication primitive write write pointers point that arm processor need send;
Amendment write pointer,
CPA_W＝(CPA_W％n)+1。
3, arm processor sends and interrupts MB_A2D to dsp processor;
4, arm processor judges whether that its intercommunication primitive needs to send in addition, returns step 3 in this way, otherwise performs step 5.
5, ARM terminates this data transmission procedure.
Specific embodiment 2
The present embodiment application scenarios is the intercommunication primitive that dsp processor in baseband chip of mobile terminal receives arm processor and sends, idiographic flow as shown in Figure 3:
In the present embodiment, dsp processor is from sharing data area BUFFER_A2D received communication primitive;
In advance for this sharing data area is provided with a read pointer CPD_R, a write pointer CPA_W and interrupt resources MB_A2D;
1, dsp processor response MB_A2D interrupts;
2, dsp processor judges MB_A2D interrupts whether there are untreated data in corresponding sharing data area;
Dsp processor compares CPD_R and CPA_W, if CPD_R is less than CPA_W, performs step 3, if CPD_R is greater than CPA_W, performs step 4, if CPD_R equals CPA_W, performs step 6;
3, to the data in the DSB data store block pointed by CPA_W-1 dsp processor reads the DSB data store block pointed to from CPD_R; Perform step 5;
4, dsp processor read from CPD_R point to DSB data store block to last DSB data store block of sharing data area and from the DSB data store block of first, sharing data area to the data in the DSB data store block pointed by CPA_W-1;
5, the DSB data store block number of this process of dsp processor amendment CPD_R, CPD_R=CPD_R+;
6, dsp processor terminates the process from arm processor received communication primitive.
Specific embodiment 3
The present embodiment application scenarios is the intercommunication primitive that arm processor in baseband chip of mobile terminal receives dsp processor and sends, idiographic flow as shown in Figure 4:
In the present embodiment, arm processor sends the sharing data area BUFFER_D2A received communication primitive of data from the dsp processor pre-set to arm processor;
In advance for this sharing data area is provided with a read pointer CPA_R, a write pointer CPD_W and interrupt resources MB_D2A;
1, arm processor response MB_D2A interrupts;
2, arm processor operating system scheduling needs the task of received communication primitive;
3, arm processor judges MB_D2A interrupts whether there are untreated data in corresponding sharing data area;
Arm processor compares CPA_R and CPD_W, if CPA_R=CPD_W, judges do not have untreated DSB data store block in sharing data area, performs step 6, otherwise performs step 4;
Data in each DSB data store block of 4, the corresponding sharing data area of arm processor process, amendment read pointer;
401, the data in arm processor process untreated DSB data store block;
402, arm processor judges whether CPA_R points to this DSB data store block, if so, performs step 403, otherwise performs step 406;
403, judge whether untreated DSB data store block in addition, perform step 404 if had, otherwise perform step 405;
In this step, judge that the foundation also having untreated DSB data store block is:
Also having unmarked except the DSB data store block of this process in determination range is processed DSB data store block.
404, revise CPA_R, make it point to next untreated DSB data store block, perform step 5;
405, revise CPA_R, make it point to DSB data store block pointed by CPD_W, perform step 6;
406, be processed by this data block identifier;
Wherein, whether in addition the determination range of described untreated DSB data store block is, if CPA_R is less than CPD_W, and a upper DSB data store block of determination range DSB data store block pointed by this DSB data store block to CPD_W; If CPA_R is greater than CPD_W, a upper DSB data store block of determination range DSB data store block pointed by this DSB data store block to last data block in territory, sharing data area and first data block to CPD_W in territory, sharing data area.
5, ARM judges whether running of task also needs to process data, if perform step 4, otherwise performs step 6;
6, ARM terminates this data handling procedure.
In the present embodiment, arm processor is as reception data processor, because ARM can operate external memory unit, therefore, carry out in processing procedure in ARM system to data, directly in sharing data area, data are processed and do not need primitive data to read in the ram space of himself and process again.Improve storage space utilization factor, reduce data-moving time and to bus holding time, simultaneously, due to the mode that ARM system is operating system scheduling task run, different primitive may have different priorities task to process, therefore might not process immediately after ARM receives data, but by task scheduling, just data be processed when inter-related task performs.Due to the task scheduling of ARM system and the impact of task priority, intercommunication primitive in different pieces of information storage block may be processed by the task of different priorities, this will produce the preceding DSB data store block in low priority task process position, and the situation of the posterior DSB data store block in high-priority task process position.High-priority task first can complete data processing, if directly amendment CPA_R can cause the discontinuous situation of idle data storage block after each task processes the DSB data store block of its correspondence, in the present embodiment step 3, ARM does not directly discharge this DSB data store block (amendment CPA_R) after processing a DSB data store block, but judge whether also had untreated DSB data store block before this DSB data store block, if also had, then do not revise CPA_R, only this DSB data store block is designated " processed ", wait follow-up work revises CPA_R after processing DSB data store block before it again, effectively avoid the discontinuous situation of idle data storage block.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (2)
1. inner processors of chip receives a method for data from other processors, it is characterized in that, comprising:
Receive data processor and read data from sending the sharing data area of data processor to its transmission data;
Steps A, the response of reception data processor send the interruption that data processor sends over;
Step B, reception data processor judge whether there are untreated data in this sharing data area according to the read pointer and write pointer that interrupt corresponding sharing data area;
Step C, the data received in data processor processes untreated DSB data store block; Judge whether read pointer points to this DSB data store block; If read pointer points to this DSB data store block, judge whether untreated DSB data store block in addition; If there is untreated DSB data store block, amendment read pointer, makes it point to next untreated DSB data store block; If do not have untreated DSB data store block, amendment read pointer, makes it point to DSB data store block pointed by write pointer; If read pointer does not point to this DSB data store block, this DSB data store block is designated processed;
If step D does not have untreated data, receive data processor and do not process.
2. a kind of inner processors of chip according to claim 1 receives the method for data from other processors, and it is characterized in that, described step B comprises:
Receive read pointer and write pointer that data processor compares this sharing data area;
If read pointer is less than write pointer, untreated DSB data store block comprises a upper DSB data store block of DSB data store block pointed by DSB data store block pointed by read pointer to write pointer; If read pointer is greater than write pointer, untreated DSB data store block comprises DSB data store block that read pointer the points to upper DSB data store block to DSB data store block pointed by last DSB data store block in territory, sharing data area and first DSB data store block to write pointer in territory, sharing data area; If read pointer equals write pointer, there is no untreated DSB data store block.
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| US9996145B2 (en) | 2013-11-18 | 2018-06-12 | Nxp B.V. | Shared interrupt multi-core architecture for low power applications |
| CN105264499B (en) * | 2013-12-20 | 2018-03-13 | 华为技术有限公司 | Message treatment method, device and reception core in a kind of shared queue |
| CN105550142A (en) * | 2015-12-07 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Data integrity processing method in high and low-speed conversion interface |
| CN111742306B (en) * | 2018-12-14 | 2024-10-18 | 华为技术有限公司 | Multiprocessor system and inter-processor communication method |
| CN114201270A (en) * | 2021-12-09 | 2022-03-18 | 海鹰企业集团有限责任公司 | A method of data integration and transmission based on general-purpose signal processor |
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| CN1472663A (en) * | 2002-07-30 | 2004-02-04 | 深圳市中兴通讯股份有限公司上海第二 | A method of data transfer in shared critical section |
| CN101105786A (en) * | 2006-07-14 | 2008-01-16 | 中兴通讯股份有限公司 | A Dual-CPU Communication Method Based on Shared Memory |
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| US7487271B2 (en) * | 2005-09-22 | 2009-02-03 | Motorola, Inc. | Method and apparatus using buffer pools and arrays of buffer pointers for sharing memory in a multiprocessor system |
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| CN1472663A (en) * | 2002-07-30 | 2004-02-04 | 深圳市中兴通讯股份有限公司上海第二 | A method of data transfer in shared critical section |
| CN101105786A (en) * | 2006-07-14 | 2008-01-16 | 中兴通讯股份有限公司 | A Dual-CPU Communication Method Based on Shared Memory |
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