CN102111161B - Method and device for acquiring encoder data - Google Patents

Abstract

A method and device for collecting encoder data, belonging to the technical field of industrial control, to solve the problem that in actual industrial applications, when it is necessary to collect the position value of any one of various encoders, it cannot be completed. The device of the present invention includes a data acquisition module and an encoder selection module, the data acquisition module is used to collect the position value of any encoder in the predetermined encoders, and outputs it; the encoder selection module is used to use the received position value The encoder corresponding to the value selects the encoder of the currently collected data. The present invention collects the position value of any encoder and selects the corresponding encoder as the encoder currently collecting data. When the actual industrial application requires, the acquisition of the position value of any encoder in various encoders is realized. .

Description

A method and device for collecting encoder data

technical field

The invention relates to an encoder data collection method and equipment, belonging to the technical field of industrial control.

Background technique

Encoder is a device that compiles and converts signals or data into signal forms that can be used for communication, transmission and storage. According to the working principle, the encoder can be divided into two types: incremental type and absolute type. The output data of the absolute type encoder reflects the absolute position of the measurement, which is a definite digital code. In the field of industrial control, the position data acquisition of absolute encoder is a relatively critical work. The major absolute encoder suppliers in the market all provide corresponding data acquisition chips, that is, decoding chips. It is relatively easy to obtain position data through decoding chips, but it consumes a lot of extra system cost and circuit board area. At the same time, there is also a lack of a configurable wide-applicability data acquisition module for encoders of various brands on the market

Since the position data output methods of each brand of encoder are different, in actual industrial applications, in many cases, it is necessary to use one of the various encoders under the same environmental conditions. When this situation occurs, it is impossible to collect the position value of any one of the various encoders in a general way under the prior art.

Contents of the invention

The invention provides an encoder data collection method and equipment to solve the problem that it cannot be collected when the position value of any one of various encoders needs to be collected in actual industrial applications.

A method for collecting encoder data, comprising:

Collect the position value of any one of the predetermined encoders and output it;

The encoder corresponding to the received position value is selected as the encoder of the currently collected data.

A device for collecting encoder data, comprising:

The data acquisition module is used to collect the position value of any encoder in the predetermined encoder and output it;

An encoder selection module, configured to select the encoder corresponding to the received position value as an encoder for currently collecting data.

The present invention collects the position value of any encoder and selects the corresponding encoder as the encoder currently collecting data. When the actual industrial application requires, the acquisition of the position value of any encoder in various encoders is realized. .

Description of drawings

Fig. 1 is a schematic flow chart of an encoder data collection method provided by a specific embodiment of the present invention;

Fig. 2 is the communication signal schematic diagram between the FPGA and Heinz music encoder that the specific embodiment of the present invention provides;

Fig. 3 is a schematic diagram of communication signals between the FPGA and the Heidenhain encoder provided by the specific embodiment of the present invention;

Fig. 4 is a schematic diagram of communication signals between the FPGA and the Tamagawa encoder provided by the specific embodiment of the present invention;

Fig. 5 is a schematic structural diagram of an encoder data collection device provided by a specific embodiment of the present invention.

Detailed ways

The specific embodiment of the present invention provides an encoder data acquisition method, which is mainly a configurable wide-applicability encoder data acquisition method realized by a field programmable gate array FPGA. In the encoder market, Hengstler (HENGSTLER), HEIDENHAIN (HEIDENHAIN) and Tamagawa (TAMAGAWA) are three commonly used encoders. The data acquisition protocol used by Hengstler is the BiSS protocol (bidirectional synchronous serial protocol), the data acquisition protocol used by Heidenhain is the EnDat protocol (Encoder Data protocol, a bidirectional serial interface defined by Heidenhain), and the data acquisition protocol of the Tamagawa encoder The protocol is the NRZ protocol. Therefore, this example proposes a soft-core module that can selectively collect the position value of any one of the three encoders of Heinzle, Heidenhain or Tamagawa through FPGA as an example. The encoder data The acquisition method is described in detail, and the technical solution provided by the present invention is by no means limited to the above three encoders, and all existing encoders can realize data acquisition through the method of the present invention.

In order to more clearly illustrate the encoder data acquisition method provided in this specific embodiment, the method is now described in detail in conjunction with the drawings of the description, as shown in Figure 1, the method may specifically include:

Step 11, collect the position value of any encoder from Heinzle, Heidenhain or Tamagawa, and output it.

Specifically, the Heinzle encoder data acquisition module, the Heidenhain encoder data acquisition module and the Tamagawa encoder data acquisition module are designed through programming in the FPGA. These three encoder data acquisition modules are all stored in the form of soft core modules. FPGA, and each module is connected with the corresponding encoder through data lines.

For the Heinzle encoder, the data acquisition protocol used is the BiSS protocol. Therefore, as shown in Figure 2, the Heinzle encoder data acquisition module can communicate with the encoder through the FPGA. The signals are Clock and Data. Clock is the clock signal sent by the FPGA to the encoder, and Data is the serial data signal returned by the encoder to the FPGA, including a maximum of 64-bit position data, 2-bit status data, 6-bit CRC check value, and 1-bit MCD value. The specific communication process is as follows: the Clock signal turns to a low level after a continuous high level, and continuously outputs a clock signal with a duty cycle of 50%, and the frequency is variable from 100Khz to 10Mhz; the first falling edge of the Clock is It is considered to be a request signal sent to the encoder. After the encoder receives the request signal, after a certain period of propagation delay and calculation delay, it returns a Start signal to the FPGA, followed by a series of data signals. After the FPGA synchronously collects the signals of the encoders, it outputs these signals to the encoder selection module.

For the HEIDENHAIN encoder, the data acquisition protocol used is the EnDat protocol, so as shown in Figure 3, the HEIDENHAIN encoder data acquisition module can communicate with the encoder through the FPGA. The signals are Clock and Data. Clock is the clock signal sent by the FPGA to the encoder, and Data is the serial data signal returned by the encoder to the FPGA, including a maximum of 64-bit position data, 2-bit status data, 6-bit CRC check value, and 1-bit MCD value. The data line in the Endat protocol is bidirectional. After two cycles of the first falling edge of the Clock, the FPGA sends serial 6-bit data 000111 to the encoder through the data line to request position data from the encoder. After a period of delay, the encoder returns the 1-bit start bit, followed by the position value with the lower bit first and the higher bit later, followed by the 5-bit CRC check bit. After the FPGA collects the signals of the HEIDENHAIN encoder synchronously, it outputs these signals to the encoder selection module.

For the Tamagawa encoder, the data acquisition protocol used is the NRZ protocol. Therefore, as shown in Figure 4, the Tamagawa encoder data acquisition module can communicate with the encoder through the FPGA. The signals are Clock and Data. Clock is the clock signal sent by the FPGA to the encoder, and Data is the serial data signal returned by the encoder to the FPGA, including a maximum of 64-bit position data, 2-bit status data, 6-bit CRC check value, and 1-bit MCD value. The FPGA requests the serial position value from the encoder by sending continuous 4-bit data 0000 to the Data terminal. After a period of delay, the encoder returns a 1-bit high level, which is the start bit, followed by 17-bit serial position data and 5-bit CRC check bit. FPGA synchronously collects these effective data values and stores them for use by subsequent circuits.

In step 22, the encoder corresponding to the received position value is selected as the encoder of the currently collected data.

The encoder selection module is also a soft-core module designed by programming in the FPGA, and is used to select the encoder corresponding to the received position value as the encoder for the current data collection. Specifically, the encoder selection module uses an internal or external selection signal to select the corresponding data acquisition module according to the use of the encoder in the system. When the selection signal is a binary number 00, 01 or 10, respectively select the use of Henry Schroth encoder, HEIDENHAIN encoder or Tamagawa encoder.

In this specific embodiment, when multiple encoders are selected and used, it is convenient to select one of the encoders through only one selection signal, so that each control board is no longer limited to a certain encoder, so that the system The versatility is greatly enhanced; since the current industrial design concept is that the system requires the circuit board area to be small enough, so directly using the FPGA to implement the data acquisition protocol to obtain data without using a decoding chip can significantly save the circuit board area.

The specific embodiment of the present invention also provides a kind of acquisition equipment of encoder data, as shown in Figure 5, each module in this equipment is the soft-core module that is set by programming in FPGA, specifically can comprise data acquisition module 51 and Encoder selection module 52, data collection module 51 is used for collecting the position value of any kind of encoder in predetermined encoder, and outputs; Encoder selection module 52 is used for the encoder selection corresponding to described position value that receives The encoder that is currently collecting data.

Further, the data acquisition module 51 may include a Heinz music encoder data acquisition module 511, a Heidenhain encoder data acquisition module 512 and a Tamagawa encoder data acquisition module 513, and the Heinz music encoder data acquisition module 511 is used for collecting Heinz music The position value of the encoder, and output; the HEIDENHAIN encoder data acquisition module 512 is used to collect the position value of the HEIDENHAIN encoder, and output; the Tamagawa encoder data acquisition module 513 is used to collect the position value of the Tamagawa encoder, and output .

In this specific embodiment, when multiple encoders are selected and used, it is convenient to select one of the encoders through only one selection signal, so that each control board is no longer limited to a certain encoder, so that the system The versatility is greatly enhanced; since the current industrial design concept is that the system requires the circuit board area to be small enough, so directly using the FPGA to implement the data acquisition protocol to obtain data without using a decoding chip can significantly save the circuit board area.

The specific implementation of the processing function of each module included in the above device has been described in the previous method implementation, and will not be repeated here.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (2)

1. the acquisition method of an encoder data is characterized in that, comprising:

Gather the positional value of any one encoder in the predetermined encoder, and output, described predetermined encoder is Heng Shile encoder, Heidenhain encoder or the river encoder that rubs more;

The described positional value corresponding codes device that receives is selected the encoder of current image data;

FPGA sends to after the clock signal of described predetermined encoder and serial data signal that described predetermined encoder returns to FPGA synchronously gather the signal of described predetermined encoder according to FPGA, the signal of gathering is exported to encoder select module.

2. the collecting device of an encoder data is characterized in that, comprising:

Data acquisition module is used for gathering the positional value of predetermined any one encoder of encoder, and exports, and described predetermined encoder is Heng Shile encoder, Heidenhain encoder or the river encoder that rubs more;

Encoder is selected module, and the described positional value corresponding codes device that is used for receiving is selected the encoder of current image data;

FPGA sends to after the clock signal of described predetermined encoder and serial data signal that described predetermined encoder returns to FPGA synchronously gather the signal of described predetermined encoder according to FPGA, the signal of gathering is exported to encoder select module.

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