CN102104557A

CN102104557A - Baseband circuit and application method thereof

Info

Publication number: CN102104557A
Application number: CN2009102004186A
Authority: CN
Inventors: 邹洁; 黄武; 缪春波; 商群峰
Original assignee: Alcatel Lucent Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 2009-12-18
Filing date: 2009-12-18
Publication date: 2011-06-22

Abstract

The invention discloses a baseband circuit and an application method thereof. The baseband circuit comprises a daughter board for processing a layer 1 of a baseband part, and a mother board which comprises a central processing unit (CPU) and is used for processing a layer 2 and a layer 3 of the baseband part, wherein the daughter board is connected to the mother board through a programmable communications interface equipment (PCI-E) interface. By the technical scheme, due to the adoption of the pluggable PCI-E, the baseband part of an evolved node B (eNodeB) can be changed by exchanging the daughter board, so the upgrading and the change of the eNodeB are very convenient and flexible.

Description

Baseband circuit and application process thereof

Technical field

Embodiments of the present invention are broadly directed to baseband circuit, more specifically, relate to baseband circuit and application process thereof.

Background technology

At present traditional enhanced base station (eNodeB) platform is all built by the printed circuit board (pcb) plate of custom-made, the last integrated equipment such as digital signal processor (DSP), field programmable gate array (FPGA), CPU, internal memory and hard disk of PCB.Its design, debugging and production all need the long cycle, and therefore cost is bigger.And the pcb board of this customization, each device all is fixed by welding on the plate, upgrading and change difficulty.

Summary of the invention

Embodiments of the present invention disclose a kind of baseband circuit and application process thereof, to address the above problem.

According to an aspect of the present invention, disclose a kind of baseband circuit, having comprised: layer 1 daughter board of handling that is used to carry out baseband portion; And the motherboard that comprises CPU, be used to carry out the layer 2 and layer 3 processing of baseband portion, wherein, described daughter board is connected to described motherboard by the PCI-E interface.

According to a further aspect in the invention, disclose a kind of baseband circuit startup method, be used to start above-mentioned baseband circuit, described method comprises: motherboard is powered on, and dispose PCI-E equipment on the described motherboard; And daughter board powered on, and dispose the PCI-E equipment of described daughter board.

In accordance with a further aspect of the present invention, disclose a kind of baseband circuit clock synchronizing method, be used for above-mentioned baseband circuit is carried out clock synchronization, described method comprises: daughter board obtains reference clock, and obtains multiple clock signal according to described reference clock; Daughter board carries out clock synchronization according to the multiple clock signal and the motherboard that obtain; Daughter board carries out clock synchronization according to the multiple clock signal that obtains to self equipment.

By above technical scheme,, make and to make the upgrading of eNodeB and change become very convenient and flexible by changing the baseband portion that daughter board changes eNodeB owing to adopted hot swappable PCI-E.

Description of drawings

In conjunction with the accompanying drawings embodiments of the present invention are described in detail, can understand the present invention better, wherein:

Fig. 1 shows the block diagram according to the baseband circuit of embodiment of the present invention;

Fig. 2 shows the flow chart according to the baseband circuit startup method of embodiment of the present invention;

Fig. 3 shows the flow chart according to the baseband circuit clock synchronizing method of embodiment of the present invention;

Fig. 4 shows according to embodiment of the present invention, the form schematic diagram of MSI capabilities register when address register is 64;

Fig. 5 shows according to embodiment of the present invention, the form schematic diagram of MSI capabilities register when address register is 32;

Fig. 6 shows according to embodiment of the present invention, the form schematic diagram of message control register among Fig. 4 and Fig. 5.

Embodiment

To a preferred embodiment of the present invention will be described in detail, having omitted in the description process is unnecessary details and function for the present invention with reference to the accompanying drawings, obscures to prevent that the understanding of the present invention from causing.

Embodiments of the present invention have proposed a kind of baseband circuit, comprise the daughter board 110 that layer 1 (L1) that be used to carry out baseband portion handles, and the motherboard 120 that comprises CPU 121, be used to carry out layer 2 (L2) and layer 3 (L3) processing of baseband portion, wherein, daughter board 110 is connected to motherboard 120 by the PCI-E interface.The CPU 121 here can be the CPU of Intel series, also can be the CPU of AMD series.The form that daughter board 110 can connect with light by optical fiber interface (as, by common public radio interface (CPRI)) communicate by letter with the radio circuit (not shown).

Wherein, daughter board 110 also comprises digital signal processor (DSP) 111 and FPGA 112, is used to carry out base band up-downgoing data processing.PCI-E switch 113 realization daughter boards 110 are communicated by letter with 120 of motherboards.

Motherboard 120 also comprises the chipset 124 that comprises south bridge 122 and north bridge 123, links to each other with CPU 121 by Front Side Bus (FSB), and represents the affairs of CPU 121 startup PCI-E, reference to storage (as, DDR 125, hard disc 126 etc.) etc.Motherboard can also comprise miscellaneous equipment 129 integrated on figure draw-in groove 127, internal clocking 128 and the motherboard 120.Especially, motherboard 120 is the computer mainboards of (as, personal computer (PC)).

FPGA 112 on the daughter board 110 obtains reference clock from outside global positioning system (GPS) (not shown), and obtain various clock signals by the phase-locked loop that self has, as, 10 milliseconds of clocks, 1 millisecond of clock, OFDM (OFDM) symbol clock, DSP work clock, SFN safeguard clock etc.

Daughter board 110 also comprises the memory of desired data when being used to preserve DSP 111 and FPGA 112 work, as double data rate memory (DDR) 114.

Can adopt the operating system of Linux as baseband circuit platform in the embodiment of the present invention.Linux2.6.9 and later release thereof have been supported the PCI-E hot plug.Certainly, also can use other to support the operating system of PCI-E hot plug

The function of L2 and L3 is positioned on the CPU 121 (in this example, being assumed to be Intel series CPU).Can realize their function by a plurality of Linux processes.Can adopt the Inter-Process Communication mode communication of Linux between L2 and the L3.

L2 and L3 order the L1 on next and the daughter board to carry out data transmission and reception by system call such as open, read, write and ioctl.

Because the Linux that has used general-purpose device and use to be convenient to programme and driven exploitation is as operating system, the base station equipment that comprises the baseband circuit that embodiment of the present invention proposes is convenient to build, exploitation, use, debugging, safeguard even upgrading, because employing all is the driving of plug-in device and module loading formula.Compare with traditional eNodeB platform, in the redundant plate and inter-board interface still less.

Though above with the formal description of the functional module of separating the baseband circuit of the embodiment of the invention, but each assembly shown in Fig. 1 can realize with a plurality of devices in actual applications, and a plurality of assemblies that illustrate also can be integrated in chip piece or the equipment in actual applications.This baseband circuit also can comprise any unit and the device that is used for other purpose.

The flow chart that refers now to Fig. 2 and Fig. 3 is described in detail annexation and the communication means between each assembly of the various functions of baseband circuit shown in Figure 1 and baseband circuit.

Fig. 2 shows the start-up course of baseband portion.

In step 210, at first motherboard 120 is powered on.

In framework shown in Figure 1, as PCI-E root complex, represent CPU 121 to start the PCI-E affairs, visit main storage etc. the north bridge on the motherboard 120 123.Provide centralized resource in the root complex: hot-swapping controller, power source management controller, interrupt control unit, error detection and report logic etc.DSP 111 on the PCI-E daughter board and FPGA 112 power by motherboard 120, and they just have power supply afterwards to have only motherboard 120 to power on.

BIOS among the CPU 121 begins the PCI-E configuration space of motherboard 120 is configured, and scans bus detection PCI-E end points again; As scan the address realm that end points reads appointment in the endpoint configurations space, address thus and PCI allocation-E switch and endpoint configurations space

In step 220, the FPGA 112 of daughter board 110 is powered on.

FPGA 112 can load and carry out initialization from the flash memory of outside.PCI-E configuration space to FPGA 112 in the preliminary examination process is provided with, and configures address realm, and waiting for CPU 121 is by the configuration of root complex.

In step 230, the DSP 111 of daughter board 110 is powered on.

Load (perhaps from CPU 121 by serial fast interface (sRIO) or Ethernet (Ethernet) load software) by JTAG (JTAG) interface, and carry out initialization.Similar with FPGA 112, in configuration space, configure the scope of PCI-E addressing, wait for the configuration of root complex.

Above step 220 and 230 also can be to carry out simultaneously, or at first carries out the operation of step 230.

Usually, FPGA 112 loadings and initialization speed ratio are very fast, can finish before BIOS scanning, and DSP 111 load and initialization speed is slow more than the speed of BIOS scanning PCI-E end points.In this case, the back that powers on is by BIOS, and the PCI-E of motherboard 120 can't find DSP111.Have two kinds of methods to address this problem: the first, after the DSP initialization finishes,, allow BIOS rescan and find and dispose all PCI-E equipment by power-off restarting motherboard 120 not; Second method is periodically to call kernel PCI-E scanning configuration feature in the given time by the application program on the motherboard 120, finds and dispose DSP 111.

In addition, PCI-E equipment is supported hot plug and plug and play.That is, the daughter board 110 of PCI-E type can insert the PCI-E slot again after motherboard 120 powers on.In this case, hot plug interrupt message will be delivered to the root complex, make software can detect the hot plug time.Thereafter start-up course is same as above.

Fig. 3 shows the method for synchronous of base band clock in the baseband circuit.

In the step 310, FPGA 112 from the outside (for example, by communicating by letter with external GPS) obtain reference clock, and obtain multiple clock signal by phase-locked loop frequency division or frequency multiplication, comprise that 10 milliseconds of clocks, 1 millisecond of clock, OFDM symbol clock, DSP work clock, single frequency network (SFN) safeguard clock.

In step 320, FPGA 112 carries out clock synchronization according to this multiple clock signal and DSP 111.

Between FPGA 112 and the DSP 111 the GPIO interface is arranged, multiple clock signal can be outputed to DSP 111 by general input and output (GPIO) interface.During the trailing edge of the GPIO module in the DSP 111 on detecting interface, will trigger an interrupt signal.Corresponding Interrupt Process function will trigger need be according to the affairs of this clock work.

In step 330, FPGA 112 carries out clock synchronization according to this multiple clock signal and CPU 121.

FPGA 112 passes through the PCI-E clock signal to CPU 121.

The PCI-E agreement provides the processing to multiple affairs, comprise read affairs, write affairs, locking memory transaction, non-forwarding affairs and message transaction.In the PCI-E system, endpoint device can submit to interrupt requests to give CPU 121 by approach in two kinds of bands.A kind of is to interrupt (MSI) by the message signale that memory write transaction is finished, and another kind is then submitted interrupt requests by message transaction to the root complex.A kind of message signale interrupted submitting to interruption before pure PCI-E equipment must use.Here FPGA 112 just will make in this way.

According to the PCI-E agreement: each PCI-E equipment is provided with a MSI capabilities register group in its configuration space.According to address register is 64 or 32, is divided into two kinds of forms of Fig. 4 and Fig. 5, wherein, and the form of MSI capabilities register when Fig. 4 shows 64 bit address registers, the form of MSI capabilities register when Fig. 5 shows 32 bit address registers.Wherein, ability ID is that 05h represents that this capabilities register is the MSI capabilities register.

Fig. 6 shows the form of message control register among Fig. 4 and Fig. 5, wherein

Many message capabilities: indication equipment wishes that CPU 121 distributes to its message bar number.It is n that FPGA112 is provided with many message capabilities, and the message bar number is 2 ⁿ, wherein 2 ⁿThe required clock interrupt signal quantity of＞=FPGA.

Many message-enabled: CPU 121 reads after above many message capabilities field, and actual allocated is given the message bar number of equipment.

Address register: CPU 121 is the target memory address of the MSI of devices allocation.The address be 64 still 32 depend on 64 bit address field in the control register.

Data register: after CPU 121 distributes to equipment message, will write one 16 value in this field.As MSI of device start, it will write one 32 bit data (high 16 is 0, and low 16 is the interior value of data register) to the message addresses register.If CPU 121 distributes to a plurality of message of equipment in many message-enabled field, then equipment will be revised the low level of data register to different message uses.

PCI-E provides the passage that transmits synchronizing signal.On this basis, source end FPGA 112 and receiving terminal CPU 121 also need synchronous protocol, make the PCI-E signal have the function of clock synchronization.

CPU 121 needs FPGA 112 that three kinds of clock sync signals are provided.Thereby FPGA 112 needs to provide to CPU 121 interruption of 10ms, 1ms and the synchronous 3 kinds of synchronizing signals of SFN altogether.Many message-enabled n is set to 2, because 2 ²=4＞3.Many message capabilities field is made as 010b.CPU 121 is made as the demand that 010b satisfies FPGA 112 equally with many message-enabled.

CPU 121 sets address register for FPGA 112, as 0x10000000h; The setting data register is as 0x00000100h.Because needing many message-enabled is 010b.When so CPU 121 is carried out write operation by FPGA 112 by writing affairs with FPGA 112 agreement destination register 0x10000000h, a generation among 4 MSI that express possibility.That interrupt signal need be arranged by the value of data register in the time of on earth.When triggering 3 kinds of different MS I, will insert 0x00000100h, 0x00000101h, 0x00000110h in CPU 121 register 0x10000000h as FPGA 112.As: 0x00000100 represents 10 milliseconds MSI; 0x00000101 represents 1 millisecond MSI; And 0x00000110 represents the MSI of SFN.When reading 0x00000100, represent to receive 10 milliseconds synchronizing signal at CPU 121 ends; 0x00000101 represents 1 millisecond synchronizing signal; And 0x00000110 represents the synchronizing signal of SFN.Arrive this, the function of CPU 121 ends is all finished in the PCI-E driver.

The source end FPGA 112 of synchronizing signal need detect the decline and the rising edge of clock sync signal in application layer, produces MSI message thus.

The receiving terminal CPU 121 of synchronizing signal need be after receiving and parse different synchronizing signals, and driver need produce an interruption to upper layer application by linux kernel.Upper layer application need define corresponding Interrupt Process function, is used for triggering the affairs that those wait for synchronizing signal.

In step 340, the single frequency network (SFN) of carrying out in the base band is synchronous

With respect to the clock synchronization of 10 milliseconds and 1 millisecond, SFN has a little difference synchronously.SFN is a System Frame Number.It increases progressively 1 every 10 milliseconds, and scope is from 0～4095.Exceed 4095 backs and return 0 repeatedly.Therefore, SFN also needs the value of synchronous SFN synchronously except 10 milliseconds on the synchronous stepping clock of needs.

The stepping clock synchronously as above, then the needing synchronously of value reads affairs by PCI-E and finishes.CPU 121 is in above-mentioned processing to MSI, when reading the data register value and being 0x00000110h, the PCI-E driver produces and interrupts, in the application layer Interrupt Process, to trigger the driver generation and read affairs, read the numerical value of SFN in FPGA 112 addresses of arranging in advance.

The synchronizing process of whole SFN: 1) the SFN initial value obtains by FPGA 112, its total alignment with aerial 10 milliseconds of frame periods and process GPS calibration.FPGA 112 gives CPU 121 with the SFN initialization, writes affairs by CPU 121 by PCI-E again and is transferred to other FPGA 112 and DSP 111.2) FPGA 112 will provide interruption to carry out the SFN maintenance to CPU 121, DSP111 and other FPGA 112 with fixed intervals 10ms, just add up.3) CPU 121 as 1 second, will carry out the verification of SFN through after the fixed intervals with other FPGA 112 and DSP 111.4) layer two among the CPU 121 and three SFN of layer become data interaction in the nuclear synchronously.

Those skilled in the art should be easy to recognize, can realize the different step of said method by programmed computer.At this, some execution modes comprise equally machine readable or computer-readable program storage device (as, digital data storage medium) and the coding machine can carry out or the executable program command of computer, wherein, some or all steps of said method are carried out in this instruction.For example, program storage device can be digital storage, magnetic storage medium (as Disk and tape), hardware or the readable digital data storage medium of light.Execution mode comprises the programmed computer of the described step of carrying out said method equally.

Description and accompanying drawing only illustrate principle of the present invention.Therefore should be appreciated that those skilled in the art can advise different structures,, embodied principle of the present invention and be included within its spirit and scope though these different structures are not clearly described herein or illustrated.In addition, all examples of herein mentioning mainly only are used for teaching purpose clearly helping the design of reader understanding's principle of the present invention and promotion this area that the inventor was contributed, and should be interpreted as not being the restriction to these specific examples of mentioning and condition.In addition, all statement and specific examples thereof of mentioning principle of the present invention, aspect and execution mode comprise its equivalent interior herein.

Top description only is used to realize embodiments of the present invention; it should be appreciated by those skilled in the art; the any modification or partial replacement that is not departing from the scope of the present invention; all should belong to claim of the present invention and come restricted portion; therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims

1. baseband circuit comprises:

Be used to carry out layer 1 daughter board of handling of baseband portion; And

The motherboard that comprises CPU is used to carry out the layer 2 and layer 3 processing of baseband portion,

Wherein, described daughter board is connected to described motherboard by the PCI-E interface.

2. baseband circuit according to claim 1, described daughter board comprises:

Be used to carry out base band up-downgoing data processing DSP and FPGA; And

Realize the PCI-E switch of communicating by letter between described daughter board and motherboard.

3. according to the described baseband circuit of claim 1, wherein, described FPGA comprises the phase-locked loop circuit part, is used for obtaining various clock signals according to the GPS in the external world.

4. baseband circuit according to claim 1, wherein, described motherboard is the mainboard of computer.

5. a baseband circuit startup method is used for starting according to each described baseband circuit of claim 1 to 4, and described method comprises:

Motherboard is powered on, and dispose PCI-E equipment on the described motherboard; And

Daughter board is powered on, and dispose the PCI-E equipment of described daughter board.

6. method according to claim 5 wherein, powers on to daughter board, and the PCI-E equipment that disposes described daughter board comprises:

From FPGA is powered on, and dispose the PCI-E configuration space of described FPGA; And

DSP is powered on, and dispose the PCI-E configuration space of described DSP.

7. powering method according to claim 6 comprises:

If the PCI-E of described motherboard does not find described DSP after powering on, the described motherboard of power-off restarting does not rescan and disposes all PCI-E equipment, up to finding described DSP.

8. powering method according to claim 6 comprises:

If the PCI-E of described motherboard does not find described DSP after powering on, periodically call kernel PCI-E scanning configuration feature in the given time by the application program on the described motherboard, find and dispose described DSP.

9. a baseband circuit clock synchronizing method is used for carrying out clock synchronization according to any described baseband circuit of claim 1 to 4, and described method comprises:

Daughter board obtains reference clock, and obtains multiple clock signal according to described reference clock;

Daughter board carries out clock synchronization according to the multiple clock signal and the motherboard that obtain;

Daughter board carries out clock synchronization according to the multiple clock signal that obtains to self equipment.

10. clock synchronizing method according to claim 9, described daughter board obtains reference clock, and obtains multiple clock signal according to described reference clock and comprise:

FPGA in the described daughter board obtains described reference clock from external GPS, and obtains described multiple clock signal by self phase-locked loop circuit.

11. clock synchronizing method according to claim 10, multiple clock signal that described daughter board basis obtains and motherboard carry out clock synchronization and comprise:

Described FPGA outputs to CPU in the described motherboard by PCI-E with in the described multiple clock signal some;

Described CPU receives and resolves some in the described multiple clock signal, and uses according to the clock signal that parses and trigger correspondent transaction.

12. clock synchronizing method according to claim 10, described daughter board carry out clock synchronization according to the multiple clock signal that obtains to self equipment and comprise:

Described FPGA sends to DSP in the described daughter board by the GPIO interface with described multiple clock signal;

A kind of corresponding affairs in described DSP triggering and the described multiple clock signal.

13. clock synchronizing method according to claim 10 also comprises:

Described FPGA obtains the SFN initial value, and sends it to the CPU in the described motherboard;

Described FPGA DSP and other FPGA in described CPU, described daughter board provide the interruption of 10ms at interval;

Through after the fixed intervals, the DSP in described CPU and the described daughter board and other FPGA carry out the verification of SFN; And

The SFN that described CPU middle level 2 and layer are 3 becomes data interaction in the nuclear synchronously.