CN102104368A

CN102104368A - Equalizer unit based on frequency compensation

Info

Publication number: CN102104368A
Application number: CN2009102427617A
Authority: CN
Inventors: 巨浩; 周玉梅; 蒋见花
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2009-12-16
Filing date: 2009-12-16
Publication date: 2011-06-22

Abstract

The invention discloses an equalizer unit based on frequency domain compensation, which comprises: the equalizing circuit is formed by sequentially connecting a first resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a third NMOS tube, a fourth NMOS tube, a second NMOS tube and a second resistor in series; the resistance adjusting circuit is composed of four branches connected in parallel, each branch is formed by connecting two adjusting switches and a resistor in series, and two ends of the circuit are respectively connected to a fifth endpoint and a sixth endpoint and used for adjusting the low-frequency gain of the equalizer circuit; and the capacitance adjusting circuit is composed of four branches connected in parallel, each branch is formed by connecting two adjusting switches and a capacitor in series, and two ends of the circuit are respectively connected to the fifth endpoint and the sixth endpoint and used for adjusting the zero-pole position of the frequency response of the equalizer circuit. By using the invention, the pole-zero distribution of the system can be dynamically adjusted through an external switch according to different channels, so that the high-frequency characteristic of the code element can be compensated.

Description

A kind of based on frequency compensated equalizer unit

Technical field

The present invention relates to HSSI High-Speed Serial Interface receiving terminal equalizer unit, relate in particular to a kind of based on frequency compensated equalizer unit.

Background technology

General Principle of Communication, the digital signal of transmitting terminal emission arrives receiving terminal through Channel Transmission.But actual channel is considered to a low pass channel, the high fdrequency component that its can filtered signal, in order to guarantee communication quality, must be before the receiving terminal processing signals compensate for channel to the influence of signal.Equalizer is exactly to be used for the high fdrequency component of compensating signal, under the prerequisite that guarantees communication quality, recovers original signal as far as possible and does not influence logic level.

Fig. 1 is traditional equalizer unit, and NMOS pipe (M1, M2) receives the differential signal through channel, and NMOS pipe (M3, M4) is as current offset; Resistance R and capacitor C are connected across between 5 and 6.This is a kind of compensation way of static state, and prerequisite is to have known the details of channel, compensates targetedly then.

The transfer function of whole system is as follows:

H (s) = \frac{- g_{m} R_{D} (1 + sRC)}{1 + \frac{1}{2} g_{m} R + sRC} - - - (1)

Wherein, R ₁=R ₂=R _D, g _mIt is the mutual conductance of NMOS pipe (M1, M2).From above-mentioned formula as can be seen, the zero point of system and limit are respectively:

f_{z} = \frac{1}{2 πRC} - - - (2)

f_{p} = (1 + \frac{1}{2} g_{m} R) \frac{1}{2 πRC} - - - (3)

The low-frequency gain of system is:

H (0) = \frac{g_{m} R_{D}}{1 + \frac{1}{2} g_{m} R} - - - (4)

By the design relevant parameters can compensating signal high fdrequency component, do not influence logic level to improve signal quality.But this mode is the compensation way of a static state, if the live signal that receives changes, this compensation might be undercompensation or overcompensation.

Summary of the invention

(1) technical problem that will solve

In order to overcome above-mentioned shortcoming, the invention provides a kind of based on frequency compensated equalizer unit, to realize compensation to the signal high fdrequency component.

(2) technical scheme

For achieving the above object, the invention provides a kind ofly based on frequency compensated equalizer unit, comprising:

Equalizing circuit, be connected together in series by first resistance R 1, a NMOS pipe M1, the 3rd NMOS pipe M3, the 4th NMOS pipe M4, the 2nd NMOS pipe M2 and second resistance R 2, wherein NMOS pipe M1 and the 2nd NMOS pipe M2 are as input port, the data that reception is come in from Channel Transmission, and connect power supply between first resistance R 1 and second resistance R 2, ground connection between the 3rd NMOS pipe M3 and the 4th NMOS pipe M4, have between the one NMOS pipe M1 and the 3rd NMOS pipe M3 between a five terminal point 5, the four NMOS pipe M4 and the 2nd NMOS pipe M2 and have one the 6th end points 6;

The resistance adjustment circuit is made of four tunnel branch roads that are connected in parallel, and every two by-pass cockes of route and a resistance are in series, and the two ends of this circuit are connected to five terminal point 5 and the 6th end points 6, the low-frequency gain that is used to regulate equalizer; And

The capacitance adjustment circuit, constitute by four tunnel branch roads that are connected in parallel, every two by-pass cockes of route and a capacitances in series form, and the two ends of this circuit are connected to five terminal point 5 and the 6th end points 6, are used to regulate the zero pole location of equalizer frequency response.

In the such scheme, described equalizing circuit comprises:

The one NMOS pipe M1 and the 2nd NMOS pipe M2, the grid 2 of the grid 1 of NMOS pipe M1 and the 2nd NMOS pipe M2 receives from the differential signal of channel input;

The 3rd NMOS pipe M3 and the 4th NMOS pipe M4, the grid 7 of the 3rd NMOS pipe M3 connects biasing circuit, as the direct current biasing of NMOS pipe M1 and the 2nd NMOS pipe M2;

First resistance R 1 connects the drain electrode of power supply and NMOS pipe M1; Second resistance R 2 connects the drain electrode of power supply and the 2nd NMOS pipe M2;

The equal ground connection of substrate of the one NMOS pipe M1, the 2nd NMOS pipe M2, the 3rd NMOS pipe M3 and the 4th NMOS pipe M4.

In the such scheme, described resistance adjustment circuit comprises:

The 6th end points 6, the three resistance R 3 that the drain electrode that the source electrode of the 5th NMOS pipe M5 meets five terminal point 5, the six NMOS pipe M6 of equalizing circuit connects equalizer connect the drain electrode of the 5th NMOS pipe M5 and the source electrode that the 6th NMOS manages M6 respectively; The grid of the 5th NMOS pipe M5 and the 6th NMOS pipe M6 connects the 9th control line 9;

The 6th end points 6, the four resistance R 4 that the drain electrode that the source electrode of the 7th NMOS pipe M7 meets five terminal point 5, the eight NMOS pipe M8 of equalizing circuit connects equalizer connect the drain electrode of the 7th NMOS pipe M7 and the source electrode that the 8th NMOS manages M8 respectively; The grid of the 7th NMOS pipe M7 and the 8th NMOS pipe M8 connects the tenth control line 10;

The 6th end points 6, the five resistance R 5 that the drain electrode that the source electrode of the 9th NMOS pipe M9 meets five terminal point 5, the ten NMOS pipe M10 of equalizing circuit connects equalizer connect the drain electrode of the 9th NMOS pipe M9 and the source electrode that the tenth NMOS manages M10 respectively; The grid of the 9th NMOS pipe M9 and the tenth NMOS pipe M10 connects the 11 control line 11;

The 6th end points 6, the six resistance R 6 that the drain electrode that the source electrode of the 11 NMOS pipe M11 meets five terminal point 5, the 12 NMOS pipe M12 of equalizing circuit connects equalizer connect the drain electrode of the 11 NMOS pipe M11 and the source electrode that the 12 NMOS manages M12 respectively; The grid of the 11 NMOS pipe M11 and the 12 NMOS pipe M12 connects the 12 control line 12.

The equal ground connection of substrate of the 5th NMOS pipe M5, the 6th NMOS pipe M6, the 7th NMOS pipe M7, the 8th NMOS pipe M8, the 9th NMOS pipe M9, the tenth NMOS pipe M10, the 11 NMOS pipe M11 and the 12 NMOS pipe M12.

In the such scheme, described capacitance adjustment circuit comprises:

The 6th end points 6, the first capacitor C 1 that the drain electrode that the source electrode of the 13 NMOS pipe M13 meets five terminal point 5, the 14 NMOS pipe M14 of equalizing circuit connects equalizer connect the drain electrode of the 13 NMOS pipe M13 and the source electrode that the 14 NMOS manages M14 respectively; The grid of the 13 NMOS pipe M13 and the 14 NMOS pipe M14 connects the 13 control line 13;

Drain electrode and the 16 NMOS that the 6th end points 6, the second capacitor C 2 that the drain electrode that the source electrode of the 15 NMOS pipe M15 meets five terminal point 5, the 16 NMOS pipe M16 of equalizing circuit connects equalizer connect the 15 NMOS pipe M15 respectively manage the M16 source electrode; The grid of the 15 NMOS pipe M15 and the 16 NMOS pipe M16 connects the 14 control line 14;

The 6th end points 6, the three capacitor C 3 that the drain electrode that the 17 NMOS pipe M17 source electrode meets five terminal point 5, the 18 NMOS pipe M18 of equalizing circuit connects equalizer connect the drain electrode of the 17 NMOS pipe M17 and the source electrode that the 18 NMOS manages M18 respectively; The grid of the 17 NMOS pipe M17 and the 18 NMOS pipe M18 connects the 15 control line 15;

The 6th end points 6, the four capacitor C 4 that the drain electrode that the source electrode of the 19 NMOS pipe M19 meets five terminal point 5, the 20 NMOS pipe M20 of equalizing circuit connects equalizer connect the drain electrode of the 19 NMOS pipe M19 and the source electrode that the 20 NMOS manages M20 respectively; The grid of the 19 NMOS pipe M19 and the 20 NMOS pipe M20 connects the 16 control line 16;

The equal ground connection of substrate of the 13 NMOS pipe M13, the 14 NMOS pipe M14, the 15 NMOS pipe M15, the 16 NMOS pipe M16, the 17 NMOS pipe M17, the 18 NMOS pipe M18, the 19 NMOS pipe M19 and the 20 NMOS pipe M20.

(3) beneficial effect

Utilize this equalizer unit provided by the invention based on frequency domain compensation, can be according to the difference of channel, the zero pole distribution of the dynamic regulating system of switch by the outside, thus can compensate the high frequency characteristics of code element.

Description of drawings

Fig. 1 is traditional equalizer unit circuit diagram;

Fig. 2 is provided by the invention based on frequency compensated equalizer unit circuit diagram;

Fig. 3 is the circuit diagram based on resistance adjustment circuit in the frequency compensated equalizer unit and capacitance adjustment circuit provided by the invention.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

As shown in Figure 2, equalizer unit provided by the invention and conventional equalizer unit are basic identical, and its difference only is between equalizer unit five terminal point 5 provided by the invention and the 6th end points 6 connection is as shown in Figure 3 one group of resistance and capacitor array.One group of resistance shown in Figure 3 and capacitor array are connected across between five terminal point 5 and the 6th end points 6, and the Kai Heguan of resistance is adjusted by NMOS pipe switch in both sides, thus the position of the low-frequency gain of Adjustment System and zero limit dynamically.

Referring again to Fig. 2, provided by the invention based on frequency compensated equalizer unit, comprise: equalizing circuit, by first resistance R 1, the one NMOS manages M1, the 3rd NMOS manages M3, the 4th NMOS manages M4, the 2nd NMOS pipe M2 and second resistance R 2 are connected together in series, wherein NMOS pipe M1 and the 2nd NMOS pipe M2 are as input port, the data that reception is come in from Channel Transmission, and connect power supply between first resistance R 1 and second resistance R 2, ground connection between the 3rd NMOS pipe M3 and the 4th NMOS pipe M4, have between the one NMOS pipe M1 and the 3rd NMOS pipe M3 between a five terminal point 5, the four NMOS pipe M4 and the 2nd NMOS pipe M2 and have one the 6th end points 6.The resistance adjustment circuit is made of four tunnel branch roads that are connected in parallel, and every two by-pass cockes of route and a resistance are in series, and the two ends of this circuit are connected to five terminal point 5 and the 6th end points 6, the low-frequency gain that is used to regulate equalizer.The capacitance adjustment circuit, constitute by four tunnel branch roads that are connected in parallel, every two by-pass cockes of route and a capacitances in series form, and the two ends of this circuit are connected to five terminal point 5 and the 6th end points 6, are used to regulate the zero pole location of equalizer frequency response.

Wherein, described equalizing circuit comprises: NMOS pipe M1 and the 2nd NMOS pipe M2, the grid 2 of the grid 1 of NMOS pipe M1 and the 2nd NMOS pipe M2 receives from the differential signal of channel input.The 3rd NMOS pipe M3 and the 4th NMOS pipe M4, the grid 7 of the 3rd NMOS pipe M3 connects biasing circuit, as the direct current biasing of NMOS pipe M1 and the 2nd NMOS pipe M2.First resistance R 1 connects the drain electrode of power supply and NMOS pipe M1; Second resistance R 2 connects the drain electrode of power supply and the 2nd NMOS pipe M2.The equal ground connection of substrate of the one NMOS pipe M1, the 2nd NMOS pipe M2, the 3rd NMOS pipe M3 and the 4th NMOS pipe M4.

Described resistance adjustment circuit comprises: the source electrode of the 5th NMOS pipe M5 connects the five terminal point 5 of equalizing circuit, the 6th end points 6, the three resistance R 3 that the drain electrode of the 6th NMOS pipe M6 connects equalizer connect the drain electrode of the 5th NMOS pipe M5 and the source electrode of the 6th NMOS pipe M6 respectively; The grid of the 5th NMOS pipe M5 and the 6th NMOS pipe M6 connects the 9th control line 9.The 6th end points 6, the four resistance R 4 that the drain electrode that the source electrode of the 7th NMOS pipe M7 meets five terminal point 5, the eight NMOS pipe M8 of equalizing circuit connects equalizer connect the drain electrode of the 7th NMOS pipe M7 and the source electrode that the 8th NMOS manages M8 respectively; The grid of the 7th NMOS pipe M7 and the 8th NMOS pipe M8 connects the tenth control line 10.The 6th end points 6, the five resistance R 5 that the drain electrode that the source electrode of the 9th NMOS pipe M9 meets five terminal point 5, the ten NMOS pipe M10 of equalizing circuit connects equalizer connect the drain electrode of the 9th NMOS pipe M9 and the source electrode that the tenth NMOS manages M10 respectively; The grid of the 9th NMOS pipe M9 and the tenth NMOS pipe M10 connects the 11 control line 11.The 6th end points 6, the six resistance R 6 that the drain electrode that the source electrode of the 11 NMOS pipe M11 meets five terminal point 5, the 12 NMOS pipe M12 of equalizing circuit connects equalizer connect the drain electrode of the 11 NMOS pipe M11 and the source electrode that the 12 NMOS manages M12 respectively; The grid of the 11 NMOS pipe M11 and the 12 NMOS pipe M12 connects the 12 control line 12.The equal ground connection of substrate of the 5th NMOS pipe M5, the 6th NMOS pipe M6, the 7th NMOS pipe M7, the 8th NMOS pipe M8, the 9th NMOS pipe M9, the tenth NMOS pipe M10, the 11 NMOS pipe M11 and the 12 NMOS pipe M12.

Described capacitance adjustment circuit comprises: the source electrode of the 13 NMOS pipe M13 connects the five terminal point 5 of equalizing circuit, the 6th end points 6, the first capacitor C 1 that the drain electrode of the 14 NMOS pipe M14 connects equalizer connect the drain electrode of the 13 NMOS pipe M13 and the source electrode of the 14 NMOS pipe M14 respectively; The grid of the 13 NMOS pipe M13 and the 14 NMOS pipe M14 connects the 13 control line 13.Drain electrode and the 16 NMOS that the 6th end points 6, the second capacitor C 2 that the drain electrode that the source electrode of the 15 NMOS pipe M15 meets five terminal point 5, the 16 NMOS pipe M16 of equalizing circuit connects equalizer connect the 15 NMOS pipe M15 respectively manage the M16 source electrode; The grid of the 15 NMOS pipe M15 and the 16 NMOS pipe M16 connects the 14 control line 14.The 6th end points 6, the three capacitor C 3 that the drain electrode that the 17 NMOS pipe M17 source electrode meets five terminal point 5, the 18 NMOS pipe M18 of equalizing circuit connects equalizer connect the drain electrode of the 17 NMOS pipe M17 and the source electrode that the 18 NMOS manages M18 respectively; The grid of the 17 NMOS pipe M17 and the 18 NMOS pipe M18 connects the 15 control line 15.The 6th end points 6, the four capacitor C 4 that the drain electrode that the source electrode of the 19 NMOS pipe M19 meets five terminal point 5, the 20 NMOS pipe M20 of equalizing circuit connects equalizer connect the drain electrode of the 19 NMOS pipe M19 and the source electrode that the 20 NMOS manages M20 respectively; The grid of the 19 NMOS pipe M19 and the 20 NMOS pipe M20 connects the 16 control line 16.The equal ground connection of substrate of the 13 NMOS pipe M13, the 14 NMOS pipe M14, the 15 NMOS pipe M15, the 16 NMOS pipe M16, the 17 NMOS pipe M17, the 18 NMOS pipe M18, the 19 NMOS pipe M19 and the 20 NMOS pipe M20.

Below in conjunction with carrying out gain-adjusted and zero limit based on frequency compensated equalizer unit and regulate and be elaborated respectively to provided by the invention.

One, gain-adjusted:

As shown in Figure 3, for the branch road of forming by the 5th NMOS pipe M5, the 6th NMOS pipe M6 and resistance R 3, if on the 9th end points 9, add a high level, so corresponding the 5th NMOS pipe M5 and the 6th NMOS pipe M6 switch will be opened, thereby the 3rd resistance R 3 has been connected between five terminal point 5 and the 6th end points 6; Otherwise, on the 9th end points 9, adding a low level, so corresponding the 5th NMOS pipe M5 and the 6th NMOS pipe M6 switch will be closed, thereby with resistance R 3 and five

terminal point

5 and 6 disconnections of the 6th end points.

Three tunnel resistance branch of back, the i.e. branch road of being made up of the 7th NMOS pipe M7, the 8th NMOS pipe M8 and resistance R 4, the branch road of being made up of the 9th NMOS pipe M9, the tenth NMOS pipe M10 and resistance R 5 and manage M11, the 12 NMOS by the 11 NMOS and manage the branch road that M12 and resistance R 6 are formed, its operation principle is identical with said process.If all resistance switchs are all opened, the resistance that is connected in parallel on so between five terminal point 5 and the 6th end points 6 is minimum, and according to formula (4) as can be known, the low-frequency gain of this moment is maximum.If close one of them or two switches, the resistance that is connected in parallel between five terminal point 5 and the 6th end points 6 will increase, and low-frequency gain will descend so.

So from this process, significantly can see Gain Adjustable joint, thus can compensate for channel for the decay of signal amplitude.

Two, zero limit is regulated:

As shown in Figure 3, for the circuit of forming by the 13 NMOS pipe M13, the 14 NMOS pipe M14 and first capacitor C 1, if on the 13 end points 13, add high level, so corresponding the 13 NMOS pipe M13 and the 14 NMOS pipe M14 switch will be opened, thereby first capacitor C 1 has been connected between five terminal point 5 and the 6th end points 6; Otherwise, on the 13 end points 13, adding a low level, so corresponding the 13 NMOS pipe M13 and the 14 NMOS pipe M14 switch will be closed, thereby with first capacitor C 1 and five

terminal point

5 and 6 disconnections of the 6th end points.

Three road capacitive branch of back, promptly the branch road of forming by the 15 NMOS pipe M15, the 16 NMOS pipe M16 and second capacitor C 2, by the branch road of forming by the 17 NMOS pipe M17, the 18 NMOS pipe M18 and the 3rd capacitor C 3 with by manage the branch road that M20 and the 4th capacitor C 4 are formed by the 19 NMOS pipe M19, the 20 NMOS, its operation principle is similar with this process.If all capacitance switchs are all opened, be connected in parallel on five terminal point 5 so and the electric capacity above the 6th end points 6 are maximum, according to formula (2,3) as can be known, the zero pole frequency of this moment is minimum.If close one of them or two switches, be connected in parallel on electric capacity on five terminal point 5 and the 6th end points 6 and will increase for a short time, zero pole frequency will raise so.So from this process, significantly can see zero pole frequency scalable, thus can compensate for channel for the decay of high fdrequency component.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. An equalizer unit based on frequency compensation, characterized in that, comprising:

The equalization circuit consists of the first resistor (R1), the first NMOS transistor (M1), the third NMOS transistor (M3), the fourth NMOS transistor (M4), the second NMOS transistor (M2) and the second resistor (R2) in sequence It is connected in series, where the first NMOS transistor (M1) and the second NMOS transistor (M2) are used as input ports to receive the data transmitted from the channel, and the first resistor (R1) and the second resistor (R2) are connected to the power supply , the ground between the third NMOS transistor (M3) and the fourth NMOS transistor (M4), a fifth terminal (5) between the first NMOS transistor (M1) and the third NMOS transistor (M3), the fourth NMOS transistor There is a sixth terminal (6) between (M4) and the second NMOS transistor (M2);

The resistance adjustment circuit is composed of four branches connected in parallel, each branch is formed by two adjustment switches and a resistor in series, and the two ends of the circuit are respectively connected to the fifth terminal (5) and the sixth terminal (6) , for adjusting the low-frequency gain of the equalizer circuit; and

Capacitance adjustment circuit is composed of four branches connected in parallel, each branch is formed by two adjustment switches and a capacitor in series, and the two ends of the circuit are respectively connected to the fifth terminal (5) and the sixth terminal (6) , used to adjust the zero-pole position of the frequency response of the equalizer circuit.

2. The equalizer unit based on frequency compensation according to claim 1, wherein the equalization circuit comprises:

The first NMOS transistor (M1) and the second NMOS transistor (M2), the gate (1) of the first NMOS transistor (M1) and the gate (2) of the second NMOS transistor (M2) receive the differential signal input from the channel ;

The third NMOS transistor (M3) and the fourth NMOS transistor (M4), the gate (7) of the third NMOS transistor (M3) is connected to the bias circuit, as the first NMOS transistor (M1) and the second NMOS transistor (M2) DC bias;

The first resistor (R1) is connected to the power supply and the drain of the first NMOS transistor (M1); the second resistor (R2) is connected to the power supply and the drain of the second NMOS transistor (M2);

The substrates of the first NMOS transistor (M1), the second NMOS transistor (M2), the third NMOS transistor (M3) and the fourth NMOS transistor (M4) are all grounded.

3. The equalizer unit based on frequency compensation according to claim 1, wherein the resistance adjustment circuit comprises:

The source of the fifth NMOS transistor (M5) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the sixth NMOS transistor (M6) is connected to the sixth terminal (6) of the equalizer circuit, and the third resistor (R3) is respectively Connect the drain of the fifth NMOS transistor (M5) and the source of the sixth NMOS transistor (M6); the gates of the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6) are connected to the ninth control line (9);

The source of the seventh NMOS transistor (M7) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the eighth NMOS transistor (M8) is connected to the sixth terminal (6) of the equalizer circuit, and the fourth resistor (R4) is respectively Connect the drain of the seventh NMOS transistor (M7) and the source of the eighth NMOS transistor (M8); the gates of the seventh NMOS transistor (M7) and the eighth NMOS transistor (M8) are connected to the tenth control line (10);

The source of the ninth NMOS transistor (M9) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the tenth NMOS transistor (M10) is connected to the sixth terminal (6) of the equalizer circuit, and the fifth resistor (R5) is respectively Connect the drain of the ninth NMOS transistor (M9) and the source of the tenth NMOS transistor (M10); the gates of the ninth NMOS transistor (M9) and the tenth NMOS transistor (M10) are connected to the eleventh control line (11) ;

The source of the eleventh NMOS transistor (M11) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the twelfth NMOS transistor (M12) is connected to the sixth terminal (6) of the equalizer circuit, and the sixth resistor (R6 ) are respectively connected to the drain of the eleventh NMOS transistor (M11) and the source of the twelfth NMOS transistor (M12); the gates of the eleventh NMOS transistor (M11) and the twelfth NMOS transistor (M12) are connected to the tenth Two control lines (12).

The fifth NMOS transistor (M5), the sixth NMOS transistor (M6), the seventh NMOS transistor (M7), the eighth NMOS transistor (M8), the ninth NMOS transistor (M9), the tenth NMOS transistor (M10), the tenth Both the substrates of the first NMOS transistor (M11) and the twelfth NMOS transistor (M12) are grounded.

4. The equalizer unit based on frequency compensation according to claim 1, wherein the capacitance adjustment circuit comprises:

The source of the thirteenth NMOS transistor (M13) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the fourteenth NMOS transistor (M14) is connected to the sixth terminal (6) of the equalizer circuit, and the first capacitor (C1 ) are respectively connected to the drain of the thirteenth NMOS transistor (M13) and the source of the fourteenth NMOS transistor (M14); the gates of the thirteenth NMOS transistor (M13) and the fourteenth NMOS transistor (M14) are connected to the tenth Three control lines (13);

The source of the fifteenth NMOS transistor (M15) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the sixteenth NMOS transistor (M16) is connected to the sixth terminal (6) of the equalizer circuit, and the second capacitor (C2 ) are respectively connected to the drain of the fifteenth NMOS transistor (M15) and the source of the sixteenth NMOS transistor (M16); the gates of the fifteenth NMOS transistor (M15) and the sixteenth NMOS transistor (M16) are connected to the fourteenth control line (14);

The source of the seventeenth NMOS transistor (M17) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the eighteenth NMOS transistor (M18) is connected to the sixth terminal (6) of the equalizer circuit, and the third capacitor (C3) respectively connect the drain of the seventeenth NMOS transistor (M17) and the source of the eighteenth NMOS transistor (M18); the gates of the seventeenth NMOS transistor (M17) and the eighteenth NMOS transistor (M18) are connected to the fifteenth control line (15);

The source of the nineteenth and fourth NMOS transistors (M19) is connected to the fifth terminal (5) of the equalizer circuit, the drain of the twentieth NMOS transistor (M20) is connected to the sixth terminal (6) of the equalizer circuit, and the fourth capacitor ( C4) respectively connect the drain of the nineteenth NMOS transistor (M19) and the source of the twentieth NMOS transistor (M20); the gates of the nineteenth NMOS transistor (M19) and the twentieth NMOS transistor (M20) are connected to the first Sixteen control lines (16);

Thirteenth NMOS tube (M13), fourteenth NMOS tube (M14), fifteenth NMOS tube (M15), sixteenth NMOS tube (M16), seventeenth NMOS tube (M17), eighteenth NMOS tube (M18), the substrates of the nineteenth NMOS transistor (M19) and the twentieth NMOS transistor (M20) are all grounded.