CN102104090B - Crystal-bonding method for light-emitting diode chip, crystal-bonded light-emitting diode and chip structure - Google Patents

Abstract

A die bonding method for a light emitting diode chip, a die bonded light emitting diode and a chip structure are provided, which are suitable for die bonding the light emitting diode chip on a substrate. The light emitting diode chip has a first metal thin film layer. The chip structure comprises a chip and a die bonding material layer, wherein the die bonding material layer is arranged on one side surface of the chip. The die bonding method comprises forming a second metal film layer on the surface of the substrate; forming a die bonding material layer on the second metal film layer; placing the light emitting diode chip on the die bonding material layer and making the first metal thin film layer contact with the die bonding material layer; heating the die bonding material layer at a liquid-solid reaction temperature for a pre-bonding time to form a first inter-metal layer and a second inter-metal layer; and heating the die bonding material layer at a die bonding temperature for a curing time to perform a die bonding reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110 ℃, and the melting points of the first and second medium metal layers after the solid-solid reaction are higher than 200 ℃.

Description

Crystal-bonding method for light-emitting diode chip, crystal-bonded light-emitting diode and chip structure

technical field

The present invention relates to a bonding method (bonding method) of a light-emitting diode chip (chip), a light-emitting diode and a chip structure, in particular to a bonding method capable of low-temperature bonding and obtaining a high-temperature intermetallic layer, and a bonding method with the bonding method. structure of light-emitting diodes and chip structures.

Background technique

The technology of attaching light emitting diode (LED, Light Emitting Diode) chips to the lead frame has been developed for many years, and it can be roughly divided into two types according to the different die bonding materials. The first type is polymer conductive adhesive material, and the second type is metal welding material.

The aforementioned first category can be found in Taiwan Patent No. 463394 "Chip-Type Light-Emitting Diode and Its Manufacturing Method". It is mainly to plate silver on the surface of a metal substrate, and form a plurality of wire frames after etching. The wire frames are bonded to one end and connected to the opposite end by wire bonding. After sealing and cutting, a chip is formed. Type light-emitting diode, the wire frame exposed at the bottom constitutes the electrical contact. In this way, if the glue is not uniformly applied during the bonding process, the crystal grains cannot be fixed at a predetermined position, thereby affecting the luminous efficiency. Secondly, due to the extremely poor heat resistance of this type of crystal bonding method, the silver adhesive bonding layer will be easily deteriorated when operating in a high temperature environment. Furthermore, the polymer material has poor thermal conductivity, and the LED grains will not be able to obtain a good heat dissipation effect because of the difficulty in thermal conductivity (the thermal conductivity of silver glue is only 1W/M-K). The lifespan and photoelectric conversion efficiency of LED grains also decrease accordingly.

The aforementioned second category can be found in Taiwan Patent Application Publication No. 200840079 "Die Bonding Material and Method for Light Emitting Diode Packaging". The die-bonding method adopted in this patent application mainly utilizes the metal material of the substrate to adopt eutectic bonding. A layer of eutectic bonding material in an appropriate range is first coated on the upper surface of the metal base of the packaging structure. Next, disposing the LED die on the eutectic bonding material of the base. The finished product is then passed through a hot plate, oven or tunnel furnace to provide an appropriate temperature to complete the eutectic bonding. This technology uses eutectic bonding material, and the bonding layer formed by it is a metal material, so it is better than silver glue in terms of heat dissipation and heat resistance. Part of the eutectic bonding material used in this patented technology has a high melting point, which makes it easy to leave thermal stress on the LED die during bonding and damage the die. Although the other part of the eutectic bonding material is a low-melting point alloy, after the bonding of this type of bonding material is completed, if the LED is used in an environment of 70-80 degrees, the bonding layer will soften, and the reliability of the contact will be greatly reduced.

In addition to the above-mentioned technologies, US Patent Application Publication No. 2007/0141749 proposes introducing ultrasonic waves into the die bonding process to ionize the joint surface with ultrasonic waves, thereby reducing heating temperature and reducing thermal stress. In this method, ultrasonic equipment needs to be added, and the manufacturing cost is increased. At the same time, if the ultrasonic wave is not properly operated, it may directly vibrate the LED die, causing the die to split.

The existing die-bonding technology that combines the chip structure with substrates such as lead frames or printed circuit boards has been developed for many years. Currently, the commonly used die-bonding methods are roughly divided into two categories, one of which is polymer conductive adhesive (such as silver glue) ) stick the chip structure on the substrate, and then put it into the air furnace for thermal curing and baking, so that the polymer conductive adhesive material is cured, and then the chip structure is fixed on the substrate. However, in this method of die bonding with polymer conductive adhesive, if the adhesive is not uniformly applied during the bonding process, the chip structure cannot be fixed at the predetermined position, thereby affecting the yield rate of the finished product after die bonding. In addition, due to the poor heat resistance of the polymer conductive adhesive, when the chip structure is operated in a high temperature environment, the polymer conductive adhesive is prone to deterioration, making the chip structure unsuitable for use in a high temperature environment. Furthermore, due to the poor thermal conductivity of the polymer conductive adhesive material, the chip structure cannot obtain a good heat dissipation effect, which further reduces the efficiency of the chip structure and greatly shortens the service life of the chip structure.

Another type of die-bonding method is to replace the use of polymer conductive adhesives with metal soldering materials. The crystal bonding method using metal soldering materials is to pre-set metal soldering materials such as tin (Sn), gold tin (AuSn), tin-lead (SnPb) on the surface of the substrate or chip structure, and provide appropriate flux (flux). Next, the chip structure is placed on the substrate, and then a baking temperature (about 300 degrees Celsius (°C) high temperature) is provided through a hot plate, an oven or a tunnel, so that the chip structure is eutectically bonded to the substrate by the metal solder material. Because this technology uses metal materials as the bonding medium between the chip structure and the substrate, it is better than molecular conductive adhesives in terms of heat dissipation and heat resistance. However, due to the high melting point of the metal soldering material, it is easy to leave thermal stress on the chip structure during the eutectic bonding process and damage the chip structure.

In order to solve the problem of residual thermal stress, some manufacturers have introduced ultrasonic equipment into the die-bonding process to ionize the joint surface between the chip structure and the substrate by ultrasonic waves, thereby reducing the heating temperature and thermal stress. However, this method needs to increase ultrasonic equipment, resulting in increased manufacturing costs. At the same time, if the operation is not done properly during the eutectic bonding process, the ultrasonic wave will directly vibrate the chip structure, causing the chip structure to break. Although another process can use metal soldering materials with low melting point characteristics to overcome the above-mentioned problem of residual thermal stress. However, when the chip structure is operated in an environment of 70-80° C., the low-melting-point metal solder material is prone to softening, which further reduces the reliability of the joint between the chip structure and the substrate.

Contents of the invention

Based on the above problems, the technical problem to be solved by the present invention is to propose a method for bonding light-emitting diode chips and a light-emitting diode using the method. The bonding alloy completed with crystal bonding has a melting point higher than 200 degrees, so the shortcomings and problems of the above-mentioned various methods can be solved.

In view of the above problems, the technical problem to be solved by the present invention is to provide a chip structure, so as to improve the existing chip structure. The problem of reduced performance and shortened service life; and the use of metal soldering materials, resulting in the residual thermal stress of the chip structure during the die bonding process and the problem of reduced reliability of the contact between the chip structure and the substrate after the die bonded.

To achieve the above object, the present invention provides a method for bonding LED chips. According to an embodiment of the method for bonding LED chips, the method for bonding LED chips is suitable for bonding LED chips and substrates. The LED chip has a first metal thin film layer, and the crystal bonding method includes: forming a second metal thin film layer on the surface of the substrate; forming a solid crystal material layer on the second metal thin film layer, and the melting point of the solid crystal material is lower than 110 degrees Celsius; The LED chip is placed on the crystal-bonding material layer, so that the first metal thin film layer contacts the crystal-bonding material; the crystal-bonding material layer is heated at a liquid-solid reaction temperature for a pre-curing time, so that the first metal film layer and the crystal-bonding material layer Forming a first intermetallic layer therebetween, and forming a second intermetallic layer between the crystal-bonding material layer and the second gold film layer; and heating the crystal-bonding material layer with a solid-solid reaction temperature for a solidification time, A solid-solid reaction is performed, and the melting points of the first intermetallic layer and the second intermetallic layer after the solid-solid reaction are higher than 200°C.

According to an embodiment, the aforementioned liquid-solid reaction temperature is equal to or higher than the melting point of the crystal-bonding material. The solid-solid reaction temperature is lower than the melting point of the crystal-bonding material. The material of the first metal thin film layer and the second metal thin film layer can be gold (Au), silver (Ag), copper (Cu) or nickel (Ni). The material of the die-bonding material layer can be bismuth indium, bismuth indium zinc, bismuth indium tin and bismuth indium tin zinc. The material of the first intermetallic layer and the second intermetallic layer can be selected from copper indium zinc (Cu-In-Sn) intermetallic, nickel indium zinc (Ni-In-Sn) intermetallic, nickel bismuth (Ni-Bi ) intermetal, gold-indium (Au-In) intermetal, silver-indium (Ag-In) intermetal, silver-zinc (Ag-Sn) intermetal and gold-bismuth (Au-Bi) intermetal.

Wherein, the step of heating the crystal-bonding material layer at the solid-solid reaction temperature to perform the solid-solid reaction is: heating the crystal-bonding material layer at the solid-solid reaction temperature to perform the solid-solid reaction until the crystal-bonding material The solid reaction with the first metal thin film layer and the second gold thin film layer is completed.

Wherein, the liquid-solid reaction temperature is 85 degrees centigrade, and the pre-solidification time is 0.1 second to 1 second.

Wherein, the curing reaction temperature is 40°C to 80°C, and the curing time is 30 minutes to 3 hours.

In order to achieve the above object, the present invention also provides a light-emitting diode. According to an embodiment of the light-emitting diode, the light-emitting diode includes a substrate, a second metal thin film layer, a second intermetallic layer, a first intermetallic layer, The first metal thin film layer and the LED chip. The material of the first metal thin film layer and the second metal thin film layer can be gold (Au), silver (Ag), copper (Cu) or nickel (Ni). The material of the interlayer metal layer can be copper indium zinc (Cu-In-Sn), nickel indium zinc (Ni-In-Sn), nickel bismuth (Ni-Bi), gold indium (Au-In), silver indium (Ag-In ), silver-zinc (Ag-Sn) or gold-bismuth (Au-Bi) intermetallics.

Wherein, the above-mentioned light-emitting diode also includes an intermediary layer sandwiched between the first intermetallic layer and the second intermetallic layer, and the material of the intermediary layer is selected from tin, bismuth, indium and zinc. group.

According to the embodiment of the above crystal bonding method, the LED chip can be pre-cured (liquid-solid reaction) at a temperature lower than 110 degrees for about 0.1 to 1 second. Thereafter, a solidification reaction is performed at a temperature lower than 80 degrees for about 30 minutes to 3 hours to complete the process of solidifying the LED chip and the substrate. Since all die-bonding procedures are performed at low temperature, no thermal stress occurs in the LED chip. Secondly, in the light-emitting diode completed by this die-bonding method, the bonding material between the LED chip and the substrate is made of metal, which has good heat conduction and heat dissipation effects. Furthermore, since the generated intermetallic compound has a melting point higher than 200°C, even if the light-emitting diode operates in an environment of 70 to 80°C, it will not have the problem of joint alloy softening.

In order to achieve the above object, the present invention also provides a chip structure, which includes a chip and a crystal-bonding material layer, the crystal-bonding material layer is arranged on a surface of the chip, and the composition material of the crystal-bonding material layer is selected from bismuth At least one of the group consisting of indium (Bi-In), bismuth indium zinc (Bi-In-Zn), bismuth indium tin (Bi-In-Sn) and bismuth indium zinc tin (Bi-In-Zn-Sn) one.

The efficacy of the present invention lies in that, according to the embodiment of the above-mentioned die-bonding method and the LED structure after die-bonding, it can be seen that during the die-bonding process, the LED chip can be pre-solidified on the substrate at a low temperature and in a short time without misalignment. shifting problem. Thereafter, the solid-solid reaction was carried out at a lower temperature. The reacted first intermetallic layer and the second intermetallic layer have high melting points (greater than 200 degrees). Therefore, even if the LED after die bonding is operated at a temperature above 80 degrees for a long time, the first intermetallic layer and the second intermetallic layer will not be softened, thereby affecting the alignment accuracy. Furthermore, since the temperature used in the process is lower than 100 degrees, there will be no thermal stress residue or concentration problem in the LED chip and other components (such as substrate, plastic reflective cup, etc.) during the die bonding process. LEDs with good reliability are obtained. Finally, since the pre-curing process can be carried out by means of laser heating, the pre-curing time is considerably shortened. Coupled with the solid time, batch operations can be adopted. This enables the crystal bonding method to have a much higher throughput than the prior art.

According to the above-mentioned embodiment of the chip structure, during the process of bonding the chip structure to a substrate such as a lead frame or a printed circuit board, the chip structure can be bonded to the substrate in a low-temperature environment by virtue of the low melting point characteristic of the die-bonding material layer. , can avoid the thermal stress concentration of the chip structure during the die-bonding process or the residual thermal stress after the die-bonding is completed, resulting in cracking and damage to the chip structure. Moreover, after the die-bonding process is completed, the high-melting-point interlayer metal layer produced by the die-bonding material layer between the chip structure and the substrate makes the connection between the chip structure and the substrate have good reliability, and it can be used in a high-temperature environment. Under long-term use, it can still maintain good operating performance.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Fig. 1 is the schematic flow sheet of one embodiment of the solid crystal method of light-emitting diode (LED) chip of the present invention;

FIG. 2A is a schematic structural diagram of an LED chip in an embodiment of the crystal bonding method of the present invention;

2B is a schematic structural view of a substrate of an embodiment of the crystal bonding method of the present invention;

FIG. 2C is a schematic structural view of the substrate performing step S52 in an embodiment of the crystal bonding method of the present invention;

2D is a schematic structural diagram of step S54 of an embodiment of the crystal bonding method of the present invention;

2E is a schematic diagram of the LED structure in step S56 of an embodiment of the crystal bonding method of the present invention;

2F is a schematic diagram of the LED structure in step S58 of an embodiment of the crystal bonding method of the present invention;

2G is a schematic diagram of another LED structure in step S58 of an embodiment of the crystal bonding method of the present invention;

3 is an alloy analysis diagram of the bonding of the crystal-bonding material layer and the first metal thin film layer in an embodiment of the crystal-bonding method according to the present invention;

4 is a schematic cross-sectional view of the first embodiment of the chip structure of the present invention;

5 is a schematic cross-sectional view of the first embodiment of the chip structure of the present invention disposed on the substrate;

6 is a schematic cross-sectional view of eutectic bonding to a substrate of the first embodiment of the chip structure of the present invention;

7 is a schematic cross-sectional view of a second embodiment of the chip structure of the present invention;

8 is a schematic cross-sectional view of a third embodiment of the chip structure of the present invention; and

FIG. 9 is a schematic cross-sectional view of a fourth embodiment of the chip structure of the present invention.

Among them, reference signs:

10 LED chips

12 The first metal film layer

20 matrix

22 Second metal film layer

30 layers of die-bonding material

32, 32' first interlayer metal layer

34, 34' second intermetallic layer

36 Interposer

100 chips

110 Substrate

120 metal layers

130 semiconductor structure

131 N-type semiconductor layer

132 luminescent material layer

133 P-type semiconductor layer

140 metal bumps

200 layers of die-bonding material

300 Substrate

310 metal layer

400 first intermetallic layer

500 Second intermetallic layer

Detailed ways

Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

First, please refer to FIG. 1 , FIG. 2A and FIG. 2B . FIG. 1 is a schematic flowchart of an embodiment of a method for bonding a light-emitting diode (LED) chip according to the present invention. FIG. 2A is a schematic structural diagram of an LED chip according to an embodiment of the die bonding method of the present invention. FIG. 2B is a schematic structural diagram of a substrate according to an embodiment of the crystal bonding method of the present invention.

This LED chip bonding method is suitable for combining the LED chip 10 and the substrate 20 . The LED chip 10 can be an LED with a p-i-n structure, such as but not limited to gallium nitride (GaN), gallium indium nitride (GaInN), aluminum indium gallium phosphide (AlInGaP) and aluminum indium gallium nitride (AlInGaN), nitride Aluminum (AlN), Indium Nitride (InN), Gallium Indium Arsenide (GaInAsN), Gallium Indium Phosphorus Nitride (GaInPN), or any combination thereof.

The spectrum of the light emitted by the LED chip 10 can be any visible light spectrum (380nm (nanometer) to 760nm), or other spectrums. The type of the LED chip 10 can be a horizontal structure (Saphhire base), a vertical structure (Thin-GaN LED) and a flip-chip (Flip-Chip) type.

The LED chip 10 has a first metal thin film layer 12 . The material of the first metal thin film layer 12 can be gold, silver, copper and nickel. The first metal thin film layer 12 can be plated on the surface of the LED chip 10 by means of electroplating, sputtering or evaporation. The thickness of the first metal thin film layer 12 may be, but not limited to, 0.2um (micrometer) to 2.0um. For example, the thickness is 0.5um (micrometer) to 1.0um.

The aforementioned LED chip 10 with the first metal thin film layer 12 is usually not directly coated with the first metal thin film layer 12 on the cut chip, but firstly coated with the first metal thin film layer on the back of the LED chip by means of the above-mentioned electroplating or the like. After 12, the chip is then completed by cutting, spectroscopic and other steps.

The aforementioned substrate 20 may be a lead frame, a printed circuit board, a substrate with a plastic reflective cup, or a ceramic substrate. The material of the base 20 can be pure elements of copper (Cu), aluminum (Al), iron (Fe), nickel (Ni) or alloys with a small amount of other elements added. The material of the substrate 20 can also be silicon (Si), aluminum nitride (AlN) or low-temperature co-fired multilayer ceramics (LTCC, Low-Temperature Cofired Ceramics).

Regarding the die-bonding method of the LED chip 10 , please refer to FIG. 1 together with FIG. 2B , FIG. 2C , FIG. 2D , FIG. 2E , and FIG. 2F . It can be seen from the figure that the LED chip 10 die-bonding method includes:

Step S50: forming a second metal thin film layer 22 on the surface of the substrate 20; (see FIG. 2B)

Step S52: forming a crystal-bonding material layer 30 on the second metal thin film layer 22, the melting point of the crystal-bonding material layer 30 being lower than 100 degrees Celsius; (see FIG. 2C )

Step S54: placing the LED chip 10 on the die-bonding material layer 30 so that the first metal thin film layer 12 contacts the die-bonding material layer 30; (see FIG. 2D )

Step S56: heating the crystal-bonding material layer 30 at a liquid-solid reaction temperature for a pre-curing time to form a first intermetallic layer 32 between the first metal thin film layer 12 and the crystal-bonding material layer 30, and to form a first interlayer metal layer 32 on the crystal-bonding material layer 30 A second intermetallic layer 34 is formed between the material layer 30 and the second gold film layer 22; and (see FIG. 2E)

Step S58: heating the crystal-bonding material layer 30 at a solid-solid reaction temperature for a solid-solid reaction to carry out a solid-solid reaction, and the melting points of the first intermetallic layer 32' and the second intermetallic layer 34' after the solid-solid reaction are higher than 200 degrees (see Figure 2F).

Regarding step S50, please refer to FIG. 2B. Wherein, the second metal thin film layer 22 can be formed on the substrate 20 by electroplating, sputtering or vapor deposition and other processes. The material of the second metal thin film layer 22 may be gold (Au), silver (Ag), copper (Cu) or nickel (Ni). The thickness of the second metal thin film layer 22 may be, but not limited to, 0.2um (micrometer) to 2.0um. For example, the thickness is 0.5um to 1.0um.

After step S50 , please refer to FIG. 2C , step S52 may form a die-bonding material layer 30 on the second metal thin film layer 22 by means of electroplating, evaporation or sputtering. The material of this solid crystal material layer 30 can be bismuth indium (Bi-In), bismuth indium tin (Bi-In-Sn), bismuth indium tin zinc (Bi-In-Sn-Zn) and bismuth indium zinc (Bi-In -Zn). Among them, the melting point of Bi-In (bismuth indium) is about 110 degrees, the melting point of Bi-25In-18Sn (bismuth indium tin) is about 82 degrees, and the melting point of Bi-20In-30Sn-3Zn (bismuth indium tin zinc) is about 90 degrees, the melting point of Bi-33In-0.5Zn (bismuth indium zinc) is about 110 degrees. The thickness of the die-bonding material layer 30 may be, but not limited to, 0.2um (micrometer) to 2.0um. For example, the thickness is 0.5um to 1.0um. Wherein, it should be noted that: Bi-25In-18Sn represents the ratio of atomic number, that is, the ratio of Bi-In-Sn atomic number is 1:25:18, and similar expression methods of other alloys in this application represent the same meaning.

Second, please refer to Figure 2D. Step S54 is to place the LED chip 10 on the die-bonding material layer 30 , and make the first metal thin film layer 12 contact the die-bonding material layer 30 . That is, as shown in Fig. 2D.

Then, proceed to step S56 of heating the crystal-bonding material layer 30 at a liquid-solid reaction temperature for a pre-curing time, so as to form the first metal film layer 12, the crystal-bonding material layer 30 and the second gold film layer 22 respectively. An intermetallic layer 32 and a second intermetallic layer 34 (see FIG. 2E ). Wherein, the liquid-solid reaction temperature may be equal to or higher than the melting temperature of the crystal-bonding material layer 30 . If the material of the die-bonding material layer 30 is bismuth indium tin, the liquid-solid reaction temperature may be 82 degrees or above. The heating method can be laser heating, hot air heating, infrared heating, thermocompression bonding, or ultrasonic-assisted thermocompression bonding.

The heating position can be directly raising the ambient temperature to the liquid-solid reaction temperature, or directly heating the crystal-bonding material layer 30 or directly heating the substrate 20 and then conducting heat to the crystal-bonding material layer 30 . For example, but not limited to, the laser is used to directly heat the bottom of the substrate 20 (ie the heating is under the substrate 20 shown in FIG. 2E ).

The heating time (pre-curing time) may be but not limited to 0.1 second to 2 seconds, for example, 0.2 second to 1 second. The heating time can be appropriately adjusted depending on the liquid-solid reaction situation. The heating time may be the time spent when the first intermetallic layer 32 and the second intermetallic layer 34 are respectively formed among the first metal thin film layer 12 , the crystal-bonding material layer 30 and the second gold thin film layer 22 . The thickness of the formed first intermetallic layer 32 and the second intermetallic layer 34 may be very thin, which means that the operation of step S56 is completed. That is, as long as the first intermetallic layer 32 and the second intermetallic layer 34 are formed between the first metal thin film layer 12, the crystal-bonding material layer 30, and the second gold thin film layer 22, that is, there is an effect of joining. Stop step S56 and proceed to the next step (S58). Of course, if the pre-curing time is increased during the process, so that more first intermetallic layers 32 and second intermetallic layers 34 are formed, it is also possible to implement.

The heating action in step S56 can also be referred to as a pre-fixing procedure. The purpose is to pre-fix the LED chip 10 and the substrate 20 according to the current alignment relationship (Alignment), so as to facilitate the subsequent process. Because the temperature of this pre-solidification process can be equal to or slightly higher than the melting point of the die-bonding material layer 30, and the pre-solidification time can be quite short, so the aforementioned alignment relationship will be effectively maintained, and will not cause damage to the LED chip 10. have any effects like thermal stress.

The materials of the first intermetallic layer 32 and the second intermetallic layer 34 are related to the first metal thin film layer 12 and the second gold thin film layer 22 , which will be described in detail later.

Finally, proceed to step S58 of heating the solidification material layer 30 at a solidification reaction temperature for a solidification time, so as to perform a solidification reaction. The solidification reaction temperature may be lower than the melting point of the crystal-bonding material layer 30 , and may be but not limited to 40°C to 80°C. The aforementioned curing time can be adjusted according to the curing reaction temperature. For example, when the solidification reaction temperature is higher, the curing time can be shorter. When the solidification reaction temperature is lower, the curing time can be longer. The curing time can be from 30 minutes to 3 hours.

The purpose of the solidification reaction is to allow the alloy elements of the die-bonding material layer 30 to diffuse with the elements of the first metal thin film layer 12 and the second metal thin film layer 22 . The solidification reaction time may be determined by the time required for most of the alloy elements in the solidification material layer 30 to complete the diffusion.

The execution of step S58 can be carried out in the form of batch operation in the actual application stage. That is, a plurality of semi-finished products that have completed step S56 are assembled, and step S58 is performed uniformly by means of hot air, oven, infrared heating or hot plate heating.

Since the solidification reaction temperature in step S58 is lower than the melting point of the die-bonding material layer 30 , it will not affect the alignment relationship completed in step S56 .

There are several possibilities for the structure of the light emitting diode formed after step S58. The structure of the first light-emitting diode is shown in FIG. 2F. It can be seen from the figure that the light-emitting diode includes a substrate 20, a second metal thin film layer 22, a second intermetallic layer 34', a first intermetallic layer 32', a first metal thin film layer 12 and an LED chip stacked in sequence. 10. The materials of the first metal thin film layer 12 and the second metal thin film layer 22 are selected from the group consisting of gold (Au), silver (Ag), copper (Cu) and nickel (Ni). The aforementioned two intermetallic layers 32', 34' are made of Cu-In-Sn (copper indium zinc) intermetallic (melting point at least 400° C.), Ni-In-Sn (nickel indium zinc) intermetallic (melting point about 700° C. °C or higher), Ni-Bi (nickel bismuth) intermetallic (melting point at least 400 °C or higher), Au-In (gold indium) intermetallic (melting point at least 400 °C or higher), Ag-In (silver indium) intermetallic (melting point at least 250°C or higher), Ag-Sn (silver-zinc) intermetallic (melting point at least 450°C or higher) and Au-Bi (gold bismuth) intermetallic (melting point at least 350°C or higher).

Secondly, it must be explained that the first intermetallic layer 32 and the second intermetallic layer 34 formed in the pre-solidification process (as shown in FIG. The material of the metal layer 34' may be different. During the pre-solidification process, although the liquid-solid reaction temperature has reached the melting point of the solidification material layer 30, the execution time of step S56 only needs to be stopped after the first intermetallic layer 32 and the second intermetallic layer 34 are formed. Therefore, part of the alloy elements in the crystal-bonding material layer 30 did not diffuse. For example, if the crystal-bonding material layer 30 generally contains indium, it is easier for the indium to diffuse first during the liquid-solid reaction to form the intermetallic layer.

Listed below are three examples showing the second metal thin film layer 22, the second intermetallic layer 34', the first intermetallic layer 32', and The material of the first metal thin film layer 12 .

[Figure 2ELED structure embodiment one]

[Figure 2ELED structure embodiment two]

[Figure 2ELED structure embodiment three]

layer Step S54 Step S56 Step S58 The first metal thin film layer Cu Cu Cu The first intermetallic layer none Cu-In-Sn intermetallic. Cu-In-Sn intermetallic. Die-bonding material layer Bi-In-Sn Bi-In-Sn none Second intermetallic layer none Cu-In-Sn intermetallic. Cu-In-Sn intermetallic. Second metal film layer Cu Cu Cu

The melting points of the first intermetallic layer 32' and the second intermetallic layer 34' in the first embodiment of the ELED structure in FIG. 2 are both higher than 200 degrees. Even if the LED is operated at a temperature above 80 degrees for a long time in the future, there will be no problem of softening of the bonding medium, and the alignment relationship in the process can be continuously maintained to obtain good light extraction efficiency.

Another structure of the LED formed after step S58 is shown in FIG. 2G . It can be seen from the figure that the light-emitting diode includes a substrate 20, a second metal thin film layer 22, a second intermetallic layer 34', an intermediate layer 36, a first intermetallic layer 32', and a first metal thin film layer stacked in sequence. 12 and LED chip 10. The material of the interposer 36 is selected from the group consisting of tin, bismuth, indium and zinc. Moreover, the material of the interposer layer 36 is related to the materials of the die-bonding material layer 30, the second intervening metal layer 34', and the first intervening metal layer 32'. If the material of the die-bonding material layer 30 is bismuth indium tin, the material of the interposer layer 36 may be tin (Sn). That is, after the solidification reaction, only tin (Sn) remains in the solidification material layer 30 .

Since the melting point of tin (Sn) is about 230°C, which is also higher than 200°C, the above purpose of not softening during the use of the LED can be achieved. That is to say, after the solidification reaction, the crystal-bonding material layer 30 may be reacted and disappear, or may remain to form the interposer layer 36 . Please refer to Figure 3 for the combined state of BIS and Ag. FIG. 3 is an alloy analysis diagram of the bonding between the crystal-bonding material layer 30 and the first metal thin film layer 12 in an embodiment of the crystal-bonding method according to the present invention. In this experiment, the Bi-25In-18Sn bismuth-indium-tin alloy is placed on a silver plate, and the temperature of 85 degrees is applied for a period of time, and then the alloy analysis diagram is obtained. It can be seen from the figure that a bonding layer of Ag2In is formed between the bismuth indium tin and the silver plate. From this, it can be known that the crystal-bonding material layer 30 used in the present invention can form a bonding layer with silver at low temperature.

According to the embodiment of the above-mentioned die-bonding method and the LED structure after die-bonding, it can be seen that during the die-bonding process, the LED chip 10 can be pre-bonded on the substrate 20 at low temperature and in a short time without the problem of misalignment. Thereafter, the solid-solid reaction was carried out at a lower temperature. The reacted first intermetallic layer 32' and the second intermetallic layer 34' have high melting points (greater than 200°C). Therefore, even if the LED after die bonding is operated at a temperature above 80 degrees for a long time, the first intermetallic layer 32' and the second intermetallic layer 34' will not be softened, thereby affecting the alignment accuracy. Furthermore, since the temperature used in the process is lower than 100 degrees, the LED chip 10 and other components (such as the base 20 , plastic reflective cup, etc.) will not have thermal stress residue or concentration during the die bonding process. LEDs with good reliability are obtained. Finally, since the pre-curing process can be carried out by means of laser heating, the pre-curing time is considerably shortened. Coupled with the solid time, batch operations can be adopted. This enables the crystal bonding method to have a much higher throughput than the prior art.

Please refer to FIG. 4 , which is a schematic cross-sectional view of the first embodiment of the chip structure provided by the present invention, which includes a chip 100 and a die-bonding material layer 200 . The chip 100 has a substrate 110 , a metal layer 120 and a semiconductor structure 130 . The composition material of the substrate 110 may be, but not limited to, sapphire (sapphire), gold (Au), silver (Ag), molybdenum (Mo), nickel (Ni), silicon (Si), silicon carbide (SiC), copper (Cu ), aluminum nitride (AlN), gallium arsenide (GaAs) or gallium nitride (GaN), etc. In this embodiment, a sapphire substrate is used as an example for illustration, but it is not limited thereto. The metal layer 120 and the semiconductor structure 130 are respectively disposed on two opposite sides of the substrate 110. The material of the metal layer 120 may be, but not limited to, metal materials such as gold, silver, copper, nickel, and alloys of the above metals. The semiconductor structure 130 has a N-type semiconductor layer 131, a luminescent material layer 132 and a P-type semiconductor layer 133, the luminescent material layer 132 is interposed between the N-type semiconductor layer 131 and the P-type semiconductor layer 133, and constitutes a semiconductor structure 130 in the form of P-I-N, and the semiconductor The structure 130 contacts the substrate 110 with the N-type semiconductor layer 131 , so that the chip 100 constitutes a light emitting diode (LED, light emitting diode) chip with a sapphire substrate.

Wherein, the N-type semiconductor layer 131 and the P-type semiconductor layer 133 can be but not limited to N-type and P-type gallium nitride (GaN), gallium indium nitride (GaInN), aluminum indium gallium phosphide (AlInGaP) and nitrogen Aluminum Indium Gallium Nitride (AlInGaN), Aluminum Nitride (AlN), Indium Nitride (InN), Gallium Indium Arsenide Nitride (GaInAsN), Gallium Indium Phosphorus Nitride (GaInPN), or combinations thereof.

The crystal-bonding material layer 200 is arranged on the other side surface of the metal layer 120 opposite to the substrate 110, and the composition material of the crystal-bonding material layer 200 is selected from bismuth indium (Bi-In), bismuth indium zinc (Bi-In-Zn) , bismuth indium tin (Bi-In-Sn) and bismuth indium zinc tin (Bi-In-Zn-Sn) and other metal materials with low melting point characteristics and at least one of the group. For example, the melting point of bismuth indium and bismuth-33indium-0.5zinc (Bi-33In-0.5Zn) is about 110°C, the melting point of bismuth-25indium-18tin (Bi-25In-18Sn) is about 82°C, and bismuth-20 Indium-30zinc-3tin (Bi-20In-30Zn-3Sn) has a melting point of about 90°C. The crystal-bonding material layer 200 can be plated on the surface of the metal layer 120 by means of electroplating, sputtering or vapor deposition to form a crystal-bonding material layer 200 with a thickness of 0.2-5.0 microns (μm) on the surface of the metal layer 120 . In another embodiment, the thickness of the die-bonding material layer 200 is between 2.0-3.5 microns (μm).

Therefore, during the operation process of die-bonding the chip structure on a substrate such as a lead frame or a printed circuit board, the die-bonding material layer 200 can be bonded to the substrate at an environment lower than 120° C. without leaving any residue in the chip structure. Thermal stress, and can prevent the chip structure from being destroyed due to structural disintegration.

Please refer to FIG. 5 , in the die-bonding process, the chip structure is contacted with the die-bonding material layer 200 on the substrate 300 , the substrate 300 can be a lead frame, a printed circuit board, a base with a plastic reflective cup, and the like. The material of the base 300 can be copper, aluminum, iron (Fe), nickel (Ni) pure elements or alloys with a small amount of other elements added. In addition, the material of the substrate 300 may also be silicon, aluminum nitride, or low-temperature co-fired multilayer ceramics (LTCC, Low-Temperature Cofired Ceramics) and the like. Moreover, there is another metal layer 310 on the surface of the base body 300, and the composition material of the metal layer 310 can be, but not limited to, metals such as gold, silver, copper and nickel that are easy to form high melting point intermetallic compounds with elements such as bismuth, indium and tin. . Therefore, when the substrate 300 is composed of gold, silver, copper or nickel, the disposition of the metal layer 310 can be omitted.

Please refer to FIG. 5 and FIG. 6 at the same time. After the chip structure contacts the metal layer 310 of the substrate 300 with the die-bonding material layer 200 , an appropriate liquid-solid reaction temperature is provided within a predetermined time. The liquid-solid reaction temperature may be equal to or higher than the melting temperature of the die-bonding material layer 200, for example, 82° C. or above, so that an intermediary is generated between the die-bonding material layer 200 and the metal layer 120 of the chip 100 and the metal layer 310 of the substrate 300. The metal compound is pre-solidified on the substrate 300 to avoid the problem of alignment shift of the chip structure on the substrate 300 . Afterwards, a solidification reaction temperature is provided within a solidification time. The solidification reaction temperature can be lower than the melting temperature of the crystal-bonding material layer 200, for example, between 40-80° C., so that the crystal-bonding material layer 200 and the crystal-bonding material layer 200 respectively A first intermetallic layer 400 and a second intermetallic layer 500 are formed between the two metal layers 120 and 310 .

For example, when the constituent materials of the two metal layers 120 and 310 are silver and gold respectively, between the crystal-bonding material layer 200 and the metal layer 120, silver-indium (Ag-In) and silver-tin ( Ag-Sn) and other high-melting-point intermetallic compounds form the first intermetallic layer 400; - the second intermetallic layer 500 composed of a high melting point intermetallic compound such as Sn). Among them, the melting point of the silver-indium intermetallic compound is at least about 250°C or higher, the melting point of the silver-tin intermetallic compound is at least about 450°C or higher, the melting point of the gold-bismuth intermetallic compound is at least about 350°C or higher, and the gold-tin intermetallic compound The compound has a melting point of at least about 250°C or higher.

Moreover, after the die-bonding process is completed, the die-bonding material layer 200 may partially remain between the first intermetallic layer 400 and the second intermetallic layer 500, or be completely reacted and disappear, so that the chip structure is The metal layer 400 and the second intermetallic layer 500 are firmly combined on the substrate 300 . At the same time, since the first intermetallic layer 400 and the second intermetallic layer 500 have a high melting point (at least greater than 200°C), the chip structure can be used in a high temperature environment, for example, the chip structure is kept at 80°C for a long time. Operating under the operating temperature, the first intermetallic layer 400 and the second intermetallic layer 500 will not soften, which can ensure a stable alignment relationship and contact reliability between the chip structure and the substrate 300, and obtain good results. of operational effectiveness.

If the chip structure disclosed in the present invention is further compared with the existing chip structure using polymer conductive adhesive material and metal welding material for die-bonding process, as shown in Table 4 and Table 5 below, Table 4 is at a current of 700 mA (mA) and power 2.5 watts (W) to test the service life of the chip structure; Table 5 compares the die-bonding temperature, die-bonding strength, heat-resistant temperature and service life of different chip structures.

Table four

Table five

From the results presented in Table 4 and Table 5 above, it can be found that compared with the existing chip structure, the chip structure disclosed in the present invention has the characteristics of low die-bonding temperature, high die-bonding strength, high heat resistance and long service life. , so that the chip structure disclosed in the present invention can be bonded to the substrate in a low-temperature environment to avoid damage to the chip structure due to the problem of residual thermal stress. It can also maintain good reliability and service life when used under high conditions.

In addition, in the chip structure disclosed in the present invention, the crystal-bonding material layer is not only disposed on the light-emitting diode chip with the sapphire substrate as in the first embodiment, but also can be applied to different types of chips in other examples of the present invention. . For example, as shown in FIG. 7, in the chip structure disclosed in the second embodiment of the present invention, the chip 100 used is an integrated circuit (IC, integrated circuit) chip, and there is a layer of contacting die-bonding material in the chip 100. 200 metal layer 120; or as shown in FIG. 8, which is the chip structure disclosed in the third embodiment of the present invention, the substrate 110 of the chip 100 is made of materials such as silicon, silicon carbide or copper, and the semiconductor structure 130 is The P-type semiconductor layer 133 is in contact with the substrate 110 to form a vertical light emitting diode chip (Vertical LED). Meanwhile, when the substrate 110 of the chip 100 is a copper substrate, the die-bonding material layer 200 can be directly disposed on the surface of the substrate 110 by means of electroplating, sputtering or vapor deposition, and the provision of the metal layer 120 is omitted.

For example, as shown in FIG. 9 , it is the chip structure disclosed in the fourth embodiment of the present invention. In the chip 100, two metal bumps (bump) 140 are arranged on the metal substrate 110, so that the semiconductor structure 130 is suspended on the substrate 110. Above, forming a flip-chip light-emitting diode (Flip-Chip LED). And because the substrate 110 is composed of metal materials, the metal layer 120 can be selectively disposed on the substrate 110, or the metal layer 120 can be omitted, so that the die-bonding material layer 200 can be directly disposed on the substrate 110 relative to the semiconductor structure 130. on the other side. This is only a difference in the arrangement among the substrate 110 , the metal layer 120 and the die-bonding material layer 200 , but it is not intended to limit the present invention.

The effect of the chip structure of the present invention is that the chip structure is provided with a crystal-bonding material layer composed of materials such as bismuth-indium, bismuth-indium-tin, bismuth-indium-zinc or bismuth-indium-tin-zinc, so that the chip structure can Bonding the chip to a substrate such as a lead frame or a printed circuit board in a low-temperature environment can prevent the chip structure from remaining thermal stress after the die-bonding is completed, resulting in cracking and damage to the chip structure. At the same time, after the die-bonding is completed, the high-melting-point metal layer formed between the die-bonding material layer and the substrate allows the chip structure to operate in a high-temperature environment for a long time and maintain good contact reliability. and operational efficiency.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (16)

1. a die-bonding method for light-emitting diode chip for backlight unit, is suitable in conjunction with a light-emitting diode chip for backlight unit and a matrix, and this light-emitting diode chip for backlight unit has one first metal film layer, and this die-bonding method comprises:

Form one second metal film layer in a surface of this matrix;

Form a die bond material layer in this second metal film layer, a fusing point of this die bond material layer is lower than 110 degree Celsius;

Put this light-emitting diode chip for backlight unit on this die bond material layer, make this first metal film layer contact this die bond material layer;

With a liquid-solid reaction temperature, heat the pre-time admittedly of this die bond material layer one, to form one first Jie's metal level between this first metal film layer and this die bond material layer, and form one second Jie's metal level between this die bond material layer and this second gold thin film layer, wherein this liquid-solid reaction temperature is equal to or higher than this fusing point of this die bond material layer; And

With a solid-solid reaction temperature, heat one curing time of this die bond material layer, to carry out a solid-solid reaction, wherein this solid-solid reaction temperature is lower than this fusing point of this die bond material layer, and this first Jie metal level after this solid-solid reaction and a fusing point of this second Jie metal level are higher than 200 degree;

Wherein, the material of this first metal film layer is selected from the group being comprised of gold, silver, copper and nickel, and the material of this second metal film layer is selected from the group being comprised of gold, silver, copper and nickel; The material of this die bond material layer is selected from the group being comprised of bismuth indium, bismuth indium zinc, bismuth indium tin and bismuth indium tin zinc.

2. die-bonding method according to claim 1, it is characterized in that, with this solid-solid reaction temperature, heat this die bond material layer, take the step of carrying out this solid-solid reaction as: with this solid-solid reaction temperature, heat this die bond material layer, to carry out this solid-solid reaction, until this solid-solid reaction of this die bond material and this first metal film layer and this second gold thin film layer is complete, to allow the element phase counterdiffusion of alloying element with this first metal film layer and this second metal film layer of this die bond material layer.

3. die-bonding method according to claim 1, is characterized in that, this liquid-solid reaction temperature is 85 degree Celsius, and time is 0.1 second to 1 second admittedly in advance for this.

4. die-bonding method according to claim 1, is characterized in that, this solid-solid reaction temperature be Celsius 40 degree to 80 degree, be 30 minutes to 3 hours this curing time.

5. die-bonding method according to claim 1, it is characterized in that, the material of this first Jie metal level and this second Jie metal level is selected from the group being comprised of copper indium zinc Jie metal, nickel indium zinc Jie metal, nickel bismuth Jie metal, golden indium Jie metal, silver-colored indium Jie metal, silver-colored zinc Jie metal and golden bismuth Jie metal.

6. a light-emitting diode, is characterized in that, comprises:

One matrix;

One second metal film layer, is positioned on this matrix, and the material of this second metal film layer is selected from gold, silver, copper and group that nickel forms;

One second Jie's metal level, is positioned on this second metal film layer;

One first Jie's metal level, is positioned on this second Jie metal level;

One first metal film layer, be positioned on this first Jie metal level, the material of this first metal film layer is selected from gold, silver, copper and group that nickel forms, and the material of this first Jie metal level and this second Jie metal level is selected from the group consisting of copper indium zinc Jie metal, nickel indium zinc Jie metal, nickel bismuth Jie metal, golden indium Jie metal, silver-colored indium Jie metal, silver-colored zinc Jie metal and golden bismuth Jie metal; And

One light-emitting diode chip for backlight unit, is positioned on this first metal film layer.

7. light-emitting diode according to claim 6, is characterized in that, separately comprises: an intermediary layer, be folded between this first Jie metal level and this second Jie metal level, and the material of this intermediary layer is selected from the group being comprised of tin, bismuth, indium and zinc.

8. a chip structure, is arranged on a matrix, it is characterized in that, includes:

One chip; And

One die bond material layer, is arranged at a surface of this chip, and the composition material of this die bond material layer is selected from the group being comprised of bismuth indium, bismuth indium zinc, bismuth indium tin and bismuth indium tin zinc at least one of them;

This chip has a metal level, and this die bond material layer is arranged on this metal level, in the die bond program engaging, between this die bond material layer and this metal level, can form Jie's metal level at this chip structure with this matrix.

9. chip structure according to claim 8, is characterized in that, the composition material of this metal level is selected from the group being comprised of gold, silver, copper, nickel and alloy thereof at least one of them.

10. chip structure according to claim 8, is characterized in that, this chip has a substrate and semiconductor structure, and this semiconductor structure and this die bond material layer are arranged at respectively the two side faces that this substrate is relative.

11. chip structures according to claim 10, is characterized in that, the composition material of this substrate is selected from one of them of the group that is comprised of sapphire, gold, silver, molybdenum, nickel, copper, silicon, carborundum, aluminium nitride, GaAs and gallium nitride.

12. chip structures according to claim 10, is characterized in that, this semiconductor structure has a n type semiconductor layer, a luminous material layer and a p type semiconductor layer, and this luminous material layer is between this n type semiconductor layer and this p type semiconductor layer.

13. chip structures according to claim 10, is characterized in that, this chip also has at least one metal coupling, and this metal coupling is arranged between this substrate and this semiconductor structure, make this semiconductor structure be suspended in this substrate top.

14. chip structures according to claim 10, is characterized in that, this metal level is between this substrate and this die bond material layer.

15. chip structures according to claim 10, is characterized in that, the thickness of this die bond material layer is 0.2～5.0 micron.

16. chip structures according to claim 15, is characterized in that, the thickness of this die bond material layer is 2.0～3.5 microns.

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