CN102104060B - Semiconductor structure and forming method thereof - Google Patents

Abstract

The present invention proposes a semiconductor structure, comprising: a first semiconductor material substrate; a first porous structure layer formed on the top layer of the first semiconductor material substrate; formed on the first porous structure layer The second porous structure layer, wherein, the porosity and pore size in the second porous structure layer are smaller than the porosity and pore size in the first porous structure layer; formed in the second porous structure layer of second semiconductor material above the layer. The invention can release the thermal mismatch stress between the Si material and the epitaxial material through the porous structure layer, prevent the occurrence of problems such as cracking of the epitaxial film at a relatively large thickness, and improve the crystal quality of the epitaxial film. Therefore, the epitaxial material layer (such as GaN, etc.) that has a large thermal mismatch stress with the Si material can be epitaxed on the Si substrate by the present invention, and the porous Si material can be removed in the subsequent process, so there is no It will affect the subsequent device process.

Description

A kind of semiconductor structure and its forming method

technical field

The invention relates to the technical field of semiconductor manufacturing and design, in particular to a semiconductor structure and a forming method thereof.

Background technique

In recent years, light emitting diodes (light emitting diodes, LEDs) have been widely used in display screens, backlight sources, special lighting, and other fields due to their long life, high luminous efficiency, small size, durability, and rich colors. The core of the LED is the LED epitaxial wafer, and its main structure includes: a substrate, a buffer layer, an N-type semiconductor layer, an active region light-emitting layer, an electron blocking layer, and a P-type semiconductor layer. As the core of the LED epitaxial wafer, the light-emitting layer in the active area is between the N-type semiconductor layer and the P-type semiconductor layer, so that the interface between the P-type semiconductor layer and the N-type semiconductor layer forms a PN junction. Due to the different thermal expansion coefficients of the substrate and the film layer, as well as the constraints of the deposition method, after the film layer grows, internal stress will be generated in the film layer due to thermal mismatch, such as Al ₂ O in the LED field ₃ (sapphire) substrates, GaN epitaxial wafers grown on Al ₂ O ₃ substrates will generate tensile stress, and for example, GaN epitaxial wafers grown on SiC substrates will generate compressive stress. However, the sapphire substrate is very expensive, and the wafer is not easy to make large, so the current LED is very expensive. Because Si material is cheap, the process is mature, and there are large-diameter wafers, there are currently many applications based on Si materials, such as optoelectronics and microwave applications, which require different materials, such as GaN.

However, there is a large thermal stress mismatch between Si and these III-V compound semiconductor materials. The thermal stress mismatch will cause cracks in the film when the epitaxial thickness is large, and the quality of the epitaxial film is not good. The thickness of the film is thus limited.

Contents of the invention

The purpose of the present invention is to at least solve one of the above-mentioned technical defects, in particular, to propose a semiconductor structure and a method for forming the same.

To achieve the above object, the present invention proposes a semiconductor structure on the one hand, comprising: a first semiconductor material substrate; a first porous structure layer formed on the top layer of the first semiconductor material substrate; a first porous structure layer formed on the first semiconductor material substrate; a second porous structure layer on top of a porous structure layer, wherein both the porosity and pore size in the second porous structure layer are smaller than the porosity and pore size in the first porous structure layer; and forming A second semiconductor material layer on the second porous structure layer.

In one embodiment of the present invention, the first semiconductor material substrate comprises Si, low Ge composition SiGe or a combination thereof.

In one embodiment of the present invention, the first porous structure layer and the second porous structure layer are porous silicon structure layers or porous germanium silicon structure layers.

In one embodiment of the present invention, it further includes: a third porous structure layer formed between the first porous structure layer and the first semiconductor material substrate, wherein the third porous structure The layer is a porous silicon structure layer or a porous silicon germanium structure layer, and the porosity and pore diameter of the third porous structure layer are smaller than those of the first porous structure layer.

In one embodiment of the present invention, cutting and peeling is performed between the third porous structure layer and the first porous structure layer.

In one embodiment of the present invention, the first porous structure layer includes a plurality of first regions and a second region spaced between the two first regions, wherein the pores of the first regions Both the porosity and the pore diameter are larger than the porosity and the pore diameter of the second region.

In one embodiment of the present invention, the porosity in the first porous structure layer is graded, and the porosity is from the interface between the first porous structure layer and the first semiconductor material substrate to the The interface between the first porous structure layer and the second porous structure layer gradually increases.

In one embodiment of the present invention, the second semiconductor material layer includes III-V compound semiconductor materials.

Another aspect of the present invention also provides a method for forming a semiconductor structure, including the following steps: providing a first semiconductor material substrate; forming a first porous structure layer and a second porous structure layer on the top layer of the first semiconductor material substrate a porous structure layer, wherein both the porosity and pore size in the second porous structure layer are smaller than the porosity and pore size in the first porous structure layer; and on the second porous structure layer A second semiconductor material layer is formed.

In one embodiment of the invention, the substrate comprises Si, low Ge composition SiGe, or a combination thereof.

In one embodiment of the present invention, the forming the first porous structure layer and the second porous structure layer on the top layer of the first semiconductor material substrate further comprises: performing anodic oxidation on the first semiconductor material substrate , while applying a pulsed anode current to the first semiconductor material substrate to form a first porous structure layer and a second porous structure layer on the top of the first semiconductor material substrate, wherein the first The porous structure layer and the second porous structure layer are porous silicon structure layers or porous germanium silicon structure layers.

In one embodiment of the present invention, before performing anodization, it also includes: implanting the first semiconductor material substrate to form an injection layer, and the injection layer forms the first porous structure layer after anodization .

In one embodiment of the present invention, the forming the first porous structure layer and the second porous structure layer on the top layer of the first semiconductor material substrate further comprises: performing anodic oxidation on the first semiconductor material substrate to form a first porous structure layer; annealing the first porous structure layer to form a second porous structure layer on top of the first porous structure layer.

In one embodiment of the present invention, it further includes: forming a third porous structure layer between the top layer of the first semiconductor material substrate and the first porous structure layer by anodic oxidation, wherein the third The porous structure layer is a porous silicon structure layer or a porous silicon germanium structure layer, and the porosity and pore diameter of the third porous structure layer are smaller than those of the first porous structure layer.

In one embodiment of the present invention, cutting and peeling is performed between the third porous structure layer and the first porous structure layer.

In one embodiment of the present invention, the forming the third porous structure layer, the first porous structure layer and the second porous structure layer further includes: anode-forming the first semiconductor material substrate oxidation, while applying a multi-level pulsed anode current to the first semiconductor material substrate to form the third porous structure layer, the first porous structure layer on the top of the first semiconductor material substrate and the second porous structure layer.

In one embodiment of the present invention, the first porous structure layer includes a plurality of first regions and a second region spaced between the two first regions, wherein the pores of the first regions Both the porosity and the pore diameter are larger than the porosity and the pore diameter of the second region. The first porous structure layer is formed through the following steps: forming a mask layer on the first semiconductor material substrate; etching the mask layer to form a plurality of openings; The semiconductor material substrate is implanted to form a first implanted region at the opening, and the first implanted region forms the first region after being anodized.

In one embodiment of the present invention, the porosity in the first porous structure layer is graded, and the porosity is from the interface between the first porous structure layer and the first semiconductor material substrate to the The interface between the first porous structure layer and the second porous structure layer gradually increases. The specific forming method is: implanting the first semiconductor material substrate, performing anodic oxidation on the first semiconductor material substrate, and simultaneously applying an anode current to the first semiconductor material substrate, and the anode current has A rapidly increasing rising edge and a gradually decreasing falling edge.

In one embodiment of the present invention, the second semiconductor material layer includes III-V compound semiconductor materials.

In the present invention, after the cooling of the subsequent epitaxial process, the thermal mismatch stress can be released through the mechanical deformation or fracture of the porous structure layer, so that the produced III-V thin film can avoid the Crack phenomenon, so it can be grown by the present invention Thicker III-V materials. In addition, in the present invention, a porous structure layer with lower porosity and pore size can be formed on the porous structure layer, so that the dislocation between the first semiconductor material and the second semiconductor material can be eliminated. More preferably, another layer of porous structure layer with lower porosity and pore diameter can be formed between the first semiconductor material substrate and the above-mentioned porous structure layer, so as to facilitate the removal of the porous structure layer. The invention can release the thermal mismatch stress between the Si material and the epitaxial material through the porous structure layer, prevent the occurrence of problems such as cracking of the epitaxial film at a relatively large thickness, and improve the crystal quality of the epitaxial film. Therefore, the epitaxial material layer (such as GaN, etc.) that has a large thermal mismatch stress with the Si material can be epitaxed on the Si substrate by the present invention, and the porous Si material can be removed in the subsequent process, so there is no It will affect the subsequent device process.

The present invention adopts epitaxy on the porous silicon with large porosity and a large thermal mismatch semiconductor material layer with the Si material, which can release the thermal mismatch stress through the partial deformation of the fragile porous silicon layer during the cooling process, so as to ensure the epitaxial thin film material layer Intact, can epitaxial thicker epitaxial material layer. Secondly, the release of thermal mismatch stress can be controlled through the patterned porous silicon (that is, the porous silicon structure of multiple first regions and second regions), providing good mechanical support and further improving the quality of the epitaxial film.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a semiconductor structure according to Embodiment 1 of the present invention;

2 is a flowchart of a method for forming a semiconductor structure according to Embodiment 1 of the present invention;

3 is a schematic diagram of a semiconductor structure of Embodiment 2 of the present invention;

4 is a flowchart of a method for forming a semiconductor structure according to Embodiment 2 of the present invention;

FIG. 5 is a semiconductor structure diagram of Embodiment 3 of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

The present invention mainly releases the thermal mismatch stress introduced by the subsequent process through the porous structure layer with large porosity and pore diameter, and removes the porous structure layer when forming the subsequent device, thereby avoiding the thermal mismatch of different semiconductor materials. impact on the device.

As shown in FIG. 1 , it is a schematic diagram of a semiconductor structure according to Embodiment 1 of the present invention. The semiconductor structure includes a first semiconductor material substrate 1100, a first porous structure layer 1200 and a second porous structure layer 1300 formed on the first semiconductor material substrate 1100, and a first porous structure layer 1300 formed on the second porous structure layer 1300. The second semiconductor material layer 1400 above. In an embodiment of the present invention, the porosity and pore diameter of the second porous structure layer 1300 are smaller than those of the first porous structure layer 1200, and the porosity of the first porous structure layer 1200 is greater than 30%. . Wherein, the materials of the first semiconductor material substrate 1100 and the second semiconductor material layer 1400 are different, for example, the first semiconductor material substrate 1100 may include Si, low Ge composition SiGe or a combination thereof, and the second semiconductor material layer 1400 Group III-V compound semiconductor materials and the like may be included. In this way, in the embodiment of the present invention, since the porosity and pore size of the first porous structure layer 1200 are relatively large, the subsequent thermal mismatch stress can be released through the above-mentioned first porous structure layer 1200 . In addition, in the embodiment of the present invention, the second porous structure layer 1300 having smaller porosity and pore diameter can help to improve the quality of the second semiconductor material layer 1400 grown thereon. Wherein, in one embodiment of the present invention, the first porous structure layer 1200 is a porous silicon germanium structure layer, and the Ge composition in the first porous structure layer 1200 is graded. The thickness of the second porous structure layer 1300 is relatively thin, so that the stress of the upper second semiconductor material layer 1400 can be transmitted to the first porous structure layer 1200 . In one embodiment of the present invention, the porosity in the first porous structure layer 1200 is greater than 20%. In one embodiment of the present invention, the porosity in the first porous structure layer 1200 is greater than 20%. Wherein, in one embodiment of the present invention, the porosity and pore size of the second porous structure layer 1300 can be very small, and the porosity and pore size of the second porous structure layer 1300 can be changed to zero after annealing, that is, become is a non-porous structure.

In one embodiment of the present invention, the first semiconductor material substrate 1100 is a silicon substrate or a silicon germanium substrate with a low germanium composition, and both the first porous structure layer 1200 and the second porous structure layer 1300 are porous silicon The structural layer or the porous germanium silicon structural layer is preferably a porous silicon structural layer in the present invention. Wherein, the thickness of the first porous structure layer 1200 is greater than the thickness of the second porous structure layer 1300, for example, the thickness of the first porous structure layer 1200 is about tens of nm to tens of μm, while the thickness of the second porous structure layer The thickness of the layer 1300 is about several nanometers to tens of nanometers, so as to facilitate the removal of the first porous structure layer 1200 that releases thermal mismatch stress in subsequent processes.

As shown in FIG. 2, it is a flowchart of a method for forming a semiconductor structure according to Embodiment 1 of the present invention, including the following steps:

In step S201 , a first semiconductor material substrate 1100 is provided. The first semiconductor material substrate 1100 may include Si, SiGe with a low Ge composition, or a combination thereof.

Step S202 , forming a first porous structure layer 1200 and a second porous structure layer 1300 on the first semiconductor material substrate 1100 . In the embodiment of the present invention, the first porous structure layer 1200 and the second porous structure layer 1300 can be formed on the first semiconductor material substrate 1100 in various ways, for example:

method one,

Carry out anodic oxidation to the first semiconductor material substrate 1100, apply the anode current of pulse form to the first semiconductor material substrate 1100 at the same time to form the first porous structure layer 1200 and the second porous structure layer 1200 on the top of the first semiconductor material substrate 1100 Pore structure layer 1300 .

way two,

Before performing anodic oxidation, the first semiconductor material substrate 1100 is implanted to form an implanted layer, wherein, in the embodiment of the present invention, various doping impurities, such as P, B, etc., can be used. Next, the first injection layer and the second injection layer are anodized so that the injection layers form the first porous structure layer 1200 , and the second porous structure layer 1300 is formed on the first porous structure layer 1200 . Among them, this method needs to be combined with method one.

way three,

Anodizing the first semiconductor material substrate 1100 to form a first porous structure layer 1200, annealing the first porous structure layer 1200 to form a second porous structure layer 1300 on top of the first porous structure layer 1200 .

way four,

In one embodiment of the present invention, the porosity in the first porous structure layer 1200 is graded, and from the interface between the first porous structure layer 1200 and the first semiconductor material substrate 1100 to the first porous The interface between the structural layer 1200 and the second porous structural layer 1300 is gradually raised, so that not only the thermal mismatch stress can be released, but also the cutting and peeling layer can be used. The first porous structure layer 1200 is formed by the following steps: implanting the first semiconductor material substrate 1100, anodizing the first semiconductor material substrate 1100, and applying anodic current to the first semiconductor material substrate 1100, wherein , the anode current has a rapidly increasing rising edge and a gradually decreasing falling edge, that is, the anode current decreases slowly and gradually after a sudden increase for a certain period of time.

Step S203 , forming a second semiconductor material layer 1400 on the second porous structure layer 1300 . Wherein, the second semiconductor material layer 1400 may include III-V compound semiconductor materials and the like.

As shown in FIG. 3 , it is a schematic diagram of a semiconductor structure of Embodiment 2 of the present invention. The semiconductor structure 3000 includes a first semiconductor material substrate 3100, a third porous structure layer 3200 formed on the first semiconductor material substrate 3100, and a first porous structure formed on the third porous structure layer 3200. layer 3300 and the second porous structure layer 3400 , and a second semiconductor material layer 3500 formed on the second porous structure layer 3400 .

In an embodiment of the present invention, the porosity and pore size of the second porous structure layer 3400 and the third porous structure layer 3200 are smaller than those of the first porous structure layer 3300 . Wherein, the materials of the first semiconductor material substrate 3100 and the second semiconductor material layer 3500 are different, for example, the first semiconductor material substrate 3100 may include Si, low Ge composition SiGe or a combination thereof, while the second semiconductor material layer 3500 Group III-V compound semiconductor materials may be included. In this way, in the embodiment of the present invention, since the porosity and pore size of the first porous structure layer 3300 are relatively large, the subsequent thermal mismatch stress can be released through the above-mentioned first porous structure layer 3300 . In addition, in the embodiment of the present invention, dislocation between the first semiconductor material substrate 3100 and the second semiconductor material layer 3500 can be improved by the second porous structure layer 3400 having a smaller porosity and pore size. Secondly, in the embodiment of the present invention, the thickness of the third porous structure layer 3200 is greater than the thickness of the first porous structure layer 3300, for example, the thickness of the first porous structure layer 3300 is about tens to hundreds of nm. , while the thickness of the second porous structure layer 3400 is about several nm to tens of nm, and the thickness of the third porous structure layer 3200 is about tens nm to tens of μm. Due to the difference in porosity, such Cutting and peeling can be easily performed between the third porous structure layer 3200 and the first porous structure layer 3300, thereby facilitating removal of the porous structure layer in subsequent processes.

In one embodiment of the present invention, the first semiconductor material substrate 3100 is a silicon substrate or a silicon germanium layer with a low germanium composition, the third porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer The structural layers 3400 are all porous silicon structural layers or porous germanium silicon structural layers.

As shown in FIG. 4, it is a flowchart of a method for forming a semiconductor structure according to Embodiment 2 of the present invention, including the following steps:

In step S401, a first semiconductor material substrate 3100 is provided, and the first semiconductor material substrate 3100 may include Si, SiGe with a low Ge composition, or a combination thereof.

Step S402 , forming a third porous structure layer 3200 , a first porous structure layer 3300 and a second porous structure layer 3400 on the first semiconductor material substrate 3100 . Wherein, the porosity and pore diameter of the third porous structure layer 3200 and the second porous structure layer 3400 are smaller than those of the first porous structure layer 3300 . The thickness of the third porous structure layer 3200 is greater than the thickness of the first porous structure layer 3300, for example, the thickness of the first porous structure layer 3300 is about tens to hundreds of nm, while the second porous structure layer 3400 The thickness of the third porous structure layer 3200 is between several tens of nm and several tens of nm. In the embodiment of the present invention, the third porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer 3400 can be formed on the first semiconductor material substrate 3100 in various ways, for example:

method one,

Anodize the first semiconductor material substrate 3100, and at the same time apply anodic current in the form of multilevel pulses to the first semiconductor material substrate 3100 to form a third porous structure layer 3200, a second porous structure layer 3200 on the top of the first semiconductor material substrate 3100 A porous structure layer 3300 and a second porous structure layer 3400 . Wherein, in this embodiment, the anode current in the form of multi-level pulse means that the magnitude of the current is gradually increased in two or more levels, so that the porosity and pore diameter of the first porous structure layer 3300 are larger than those of the third porous structure layer. 3200 and the purpose of the porosity and pore size of the second porous structure layer 3400.

way two,

In order to facilitate the formation of the first porous structure layer 3300, the first semiconductor material substrate 3100 needs to be implanted before anodic oxidation, and the thickness of the implanted layer at the implantation depth can be controlled to be the thickness of the first porous structure layer 3300 . In this way, the injection layer can be etched into the first porous structure layer 3300 after anodization.

Step S403 , forming a second semiconductor material layer 3500 on the second porous structure layer 3400 . Wherein, the second semiconductor material layer 3500 may include III-V compound semiconductor materials and the like.

As shown in FIG. 5 , it is a semiconductor structure diagram of Embodiment 3 of the present invention. The semiconductor structure includes a first semiconductor material substrate 1100, a first porous structure layer 5200 and a second porous structure layer 5300 formed on the first semiconductor material substrate 5100, and a first porous structure layer 5300 formed on the second porous structure layer 5300. The second semiconductor material layer 5400 above. In this embodiment, the first porous structure layer includes a plurality of first regions 6100 and second regions 6200 spaced between the two first regions 6100, wherein the porosity and pore diameter of the first regions 6100 are larger than The porosity and pore size of the second region 6200. Such a first porous structure layer can be formed by the following method. For example, a mask layer is first formed on the first semiconductor material substrate, and then the mask layer is etched to form a plurality of openings, and the first semiconductor material substrate is implanted through these openings to form a first implantation region at the openings , followed by anodic oxidation, because of the damage caused by the implantation, the first implanted region can form the first region after anodic oxidation. In this way, the porosity and pore diameter in the first region can be made larger, which is more conducive to stress release. At the same time, because the second region with smaller porosity and pore diameter is provided as a support between the first regions, it will not Collapse due to stress release.

In the present invention, after the subsequent epitaxial process is cooled, the thermal mismatch stress can be released through the mechanical deformation of the porous structure layer, so that the produced III-V thin film can avoid the Crack phenomenon, so it can grow thicker by the present invention. of III-V materials. In addition, in the present invention, a porous structure layer with lower porosity and pore size can be formed on the porous structure layer, so that the dislocation between the first semiconductor material and the second semiconductor material can be eliminated. More preferably, another layer of porous structure layer with lower porosity and pore diameter can be formed between the first semiconductor material substrate and the above-mentioned porous structure layer, so as to facilitate the removal of the porous structure layer. The invention can release the thermal mismatch stress between the Si material and the epitaxial material through the porous structure layer, prevent the occurrence of problems such as cracking of the epitaxial film at a relatively large thickness, and improve the crystal quality of the epitaxial film. Therefore, the epitaxial material layer (such as GaN, etc.) that has a large thermal mismatch stress with the Si material can be epitaxed on the Si substrate by the present invention, and the porous Si material can be removed in the subsequent process, so there is no It will affect the subsequent device process.

The present invention adopts epitaxy on the porous silicon with large porosity and a large thermal mismatch semiconductor material layer with the Si material, which can release the thermal mismatch stress through the partial deformation of the fragile porous silicon layer during the cooling process, so as to ensure the epitaxial thin film material layer Intact, can epitaxial thicker epitaxial material layer. Secondly, the release of thermal mismatch stress can be controlled through the patterned porous silicon (that is, the porous silicon structure of multiple first regions and second regions), providing good mechanical support and further improving the quality of the epitaxial film.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims (21)

1. a semiconductor structure is characterized in that, comprising:

The first semiconductive material substrate;

Be formed on the first porous structure layer on described the first semiconductive material substrate top layer;

Be formed on the second porous structure layer on described the first porous structure layer; With

Be formed on the second semiconductor material layer on described the second porous structure layer, wherein, porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer, discharging the thermal mismatch stress between described the first semiconductive material substrate and described the second semiconductor material layer, and improve the dislocation between described the first semiconductive material substrate and described the second semiconductor material layer.

2. semiconductor structure as claimed in claim 1 is characterized in that, described the first semiconductive material substrate comprises Si, low Ge component S iGe or its combination.

3. semiconductor structure as claimed in claim 2 is characterized in that, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.

4. semiconductor structure as claimed in claim 3 is characterized in that, also comprises:

Be formed on the 3rd porous structure layer between described the first porous structure layer and described the first semiconductive material substrate, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.

5. semiconductor structure as claimed in claim 4 is characterized in that, cuts between described the 3rd porous structure layer and described the first porous structure layer and peels off.

6. semiconductor structure as claimed in claim 1, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.

7. semiconductor structure as claimed in claim 1, it is characterized in that, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.

8. semiconductor structure as claimed in claim 1 is characterized in that, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.

9. the formation method of a semiconductor structure is characterized in that, may further comprise the steps:

The first semiconductive material substrate is provided;

On described the first semiconductive material substrate top layer, form the first porous structure layer and the second porous structure layer; With

On described the second porous structure layer, form the second semiconductor material layer, wherein, porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer, discharging the thermal mismatch stress between described the first semiconductive material substrate and described the second semiconductor material layer, and improve the dislocation between described the first semiconductive material substrate and described the second semiconductor material layer.

10. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described substrate comprises Si, low Ge component S iGe or its combination.

11. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms the first porous structure layer and the second porous structure layer further comprises on the first semiconductive material substrate top layer:

Described the first semiconductive material substrate is carried out anodic oxidation, while forms the first porous structure layer and the second porous structure layer to the anode current that described the first semiconductive material substrate applies impulse form with the top in described the first semiconductive material substrate, wherein, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.

12. the formation method of semiconductor structure as claimed in claim 11 is characterized in that, also comprises before the anodic oxidation carrying out:

Described the first semiconductive material substrate is injected to form implanted layer, and described implanted layer forms described the first porous structure layer after anodic oxidation.

13. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms the first porous structure layer and the second porous structure layer further comprises on the first semiconductive material substrate top layer:

Described the first semiconductive material substrate is carried out anodic oxidation to form the first porous structure layer;

Described the first porous structure layer annealed form the second porous structure layer with the top at described the first porous structure layer.

14. the formation method of semiconductor structure as claimed in claim 13 is characterized in that, also comprises:

Between described the first semiconductive material substrate top layer and described the first porous structure layer, form the 3rd porous structure layer by anodic oxidation, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.

15. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, cuts between described the 3rd porous structure layer and described the first porous structure layer and peels off.

16. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, described formation the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer further comprise:

Described the first semiconductive material substrate is carried out anodic oxidation, and the while forms described the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer to the anode current that described the first semiconductive material substrate applies the multistage pulses form with the top in described the first semiconductive material substrate.

17. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.

18. the formation method of semiconductor structure as claimed in claim 17 is characterized in that, described the first porous structure layer forms by following steps:

On described the first semiconductive material substrate, form mask layer;

The described mask layer of etching is to form a plurality of openings;

By described opening described the first semiconductive material substrate is injected to form the first injection zone at described opening part, described the first injection zone is forming described first area through after the anodic oxidation.

19. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.

20. the formation method of semiconductor structure as claimed in claim 19, it is characterized in that, described the first porous structure layer forms by following steps: described the first semiconductive material substrate is injected, and described the first semiconductive material substrate carried out anodic oxidation, simultaneously apply anode current to described the first semiconductive material substrate, the trailing edge that described anode current has the rising edge of fast lifting and progressively reduces.

21. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.

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