CN102097348B - Measure electrical testing structure and the method thereof of epitaxial patterns side-play amount - Google Patents
Measure electrical testing structure and the method thereof of epitaxial patterns side-play amount Download PDFInfo
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- CN102097348B CN102097348B CN201010575796.5A CN201010575796A CN102097348B CN 102097348 B CN102097348 B CN 102097348B CN 201010575796 A CN201010575796 A CN 201010575796A CN 102097348 B CN102097348 B CN 102097348B
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- 238000012360 testing method Methods 0.000 title claims abstract description 142
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005259 measurement Methods 0.000 claims abstract description 6
- 230000005611 electricity Effects 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 6
- 230000005012 migration Effects 0.000 claims description 4
- 238000013508 migration Methods 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 description 6
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- 230000003111 delayed effect Effects 0.000 description 4
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Abstract
A kind of electrical testing structure measuring epitaxial patterns side-play amount, including: buried regions, it is formed at semiconductor substrate surface；Epitaxial layer, is formed at semiconductor substrate surface；Plug district, is equidistantly formed in the epitaxial layer on described buried regions surface, and has different default bias amounts in same direction from described buried regions；Contact hole, is formed at surface, described plug district；And sequentially form at the contact hole in described adjacent plug district the first conductive connecting line, the second conductive connecting line, and the 3rd conductive connecting line.The method of described measurement epitaxial patterns side-play amount includes: the electrical testing structure with different default bias amount is carried out electrical testing respectively.The present invention, by utilizing electrical testing structure to measure epitaxial patterns side-play amount, not only makes measuring accuracy higher, and delays figure to the registration error of figure before extension outside can effectively reducing.
Description
Technical field
The present invention relates to the epitaxy technique in IC manufacturing, particularly relate to a kind of epitaxial patterns of measuring and offset
The electrical testing structure of amount and method thereof.
Background technology
In bipolar semiconductor manufacturing process, in the side of surface of silicon one layer of single-crystal semiconductor thin film of growth
Method, referred to as extension.Initial wafer carries out epitaxial growth and has many benefits.One, epitaxial layer is not
Need, with lower floor's wafer, there is identical doping type.Such as in bipolar process, N-type epitaxy layer can grow
In P type substrate.Secondly, unlike CZ silicon, epitaxial silicon will not be stain by oxygen or carbon.
Meanwhile, allow also in the epitaxial layer form buried regions.N+ buried regions becomes the key step in most bipolar process
Suddenly, because it makes the vertical NPN transistor of the low collector resistance of making be possibly realized.Arsenic and antimony are to form N-type
The first-selected impurity of buried regions, because the low diffusion rate of described arsenic and antimony makes buried regions in high-temperature process subsequently
Horizontal proliferation minimum.Antimony is more more generally used than arsenic because it outside time-delay table reveal and less laterally automatically mix
Miscellaneous.
The N+ buried regions formed in described epitaxial layer needs annealed to eliminate implant damage, in annealing process
In thermal oxide can occur, oxidation can cause occurring that slight silicon face is discontinuous in oxidation layer window edge surrounding.
Epitaxial layer is by discontinuous at silicon face described in the final surface-rendering of wafer faithfully.Examining under a microscope can
To find, the surface of epitaxial layer defines a profile faintly, referred to as n type buried layer shade.At light subsequently
Carving in step, the etching in such as deep N+ district, described deep N+ district will aligned in position discontinuous with described silicon face.
This front layer figure displacement produced after extension is referred to as domain displacement, and i.e. figure is after epitaxial growth
There occurs certain drift.
When lithography alignment before the photoetching needs delayed outward and extension, it is necessary to inclined to this exposure when
Shifting amount compensates.The value compensated typically is multiplied by a penalty coefficient by epitaxial thickness and obtains.But,
Described penalty coefficient is an empirical value, it is impossible to complies fully with real offset, and makes compensation inaccuracy,
Figure is delayed to the registration error of figure before extension outside can not efficiently controlling.
The problem that prior art exists, this case designer, by being engaged in the industry experience for many years, actively studies
Improvement, has then had the present invention to utilize the method that electrical parameter measures extent pattern drifting quantity.
Summary of the invention
The present invention be directed in prior art, the compensation inaccuracy to extension map migration amount, it is impossible to effectively
Figure is delayed to defects such as the registration error of figure before extension, it is provided that a kind of epitaxial patterns of measuring offsets outside controlling
The electrical testing structure of amount.
A further object of the present invention is in prior art, the compensation inaccuracy to extension map migration amount,
Figure is delayed to defects such as the registration error of figure before extension, it is provided that one utilizes institute outside can not efficiently controlling
State the method that electrical testing structure measures epitaxial patterns side-play amount.
In order to solve the problems referred to above, the present invention provides a kind of electrical testing structure measuring epitaxial patterns side-play amount,
The electrical testing structure of described measurement epitaxial patterns side-play amount includes: buried regions, is formed at semiconductor substrate surface；
Epitaxial layer, is formed at the semiconductor substrate surface with described buried regions；Plug district, be equidistantly formed at described in bury
In the epitaxial layer on layer surface, and there is from described buried regions different default bias amounts in same direction；Contact hole,
It is formed at surface, described plug district；And first sequentially formed at the contact hole in described adjacent plug district
Conductive connecting line, the second conductive connecting line, and the 3rd conductive connecting line.Plug district offsets in same direction, and has
Each electrical testing structure of different default bias amounts forms an electrical testing structure group.
Wherein, the size of described default bias amount is any value between 0 to 1 times of epitaxy layer thickness.
The step-length in described plug district determines according to the thickness of epitaxial layer and the precision of compensation dosage.
Described step-length is between 0.01 micron to 1 micron.
Optionally, when described epitaxy layer thickness is 1 micron, step-length is 0.1 micron.
Optionally, described electrical testing structure group is included in equidirectional skew, and default bias amount is respectively 0
Micron, 0.1 micron, 0.2 micron, 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron,
0.8 micron, 0.9 micron, the electrical testing structure of 1 micron.
Optionally, described electrical testing structure has 3 adjacent plug districts.
The direction of electrical testing structure is along X positive direction, X negative direction, Y positive direction relative to buried regions, with
And Y negative direction.
For realizing a further object of the present invention, outside the present invention provides one to utilize described electrical testing structure to measure
The method prolonging map migration amount, the method for testing of described epitaxial patterns side-play amount includes:
The electrical testing structure with different default bias amount in electrical testing structure group is carried out electricity respectively
Test, the first resistance between the first conductive connecting line and second conductive connecting line of test electrical testing structure, with
And the second resistance that second between conductive connecting line and the 3rd conductive connecting line,
If described first resistance is equal with described second resistance, then presetting corresponding to this electrical testing structure
Side-play amount is just real offset；
If described first resistance is the most unequal with described second resistance, then with described electrical testing structure group
Electrical testing structure in the electrical testing structure group that offset direction, plug district is contrary carries out described electricity survey respectively
Examination, if described first resistance is equal with described second resistance, then presetting corresponding to this electrical testing structure
Side-play amount is just real offset；
If described first resistance is the most unequal with described second resistance, then described electrical testing structure group with
And the electrical testing structure group contrary with offset direction, described electrical testing structure group plug district is chosen the first electricity
The default bias amount corresponding to electrical testing structure of resistance and the second resistance difference minimum is as real offset.
In sum, the present invention, by utilizing electrical testing structure to measure epitaxial patterns side-play amount, not only makes
Measuring accuracy is higher, and delays figure to the registration error of figure before extension outside can effectively reducing.
Accompanying drawing explanation
Fig. 1 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have first along X positive direction pre-
If the structural representation of side-play amount；
Fig. 2 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have second along X positive direction pre-
If the structural representation of side-play amount；
Fig. 3 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 3rd along X positive direction pre-
If the structural representation of side-play amount；
Fig. 4 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 4th along X negative direction pre-
If the structural representation of side-play amount；
Fig. 5 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 5th along X negative direction pre-
If the structural representation of side-play amount；
Fig. 6 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 6th along Y positive direction pre-
If the structural representation of side-play amount；
Fig. 7 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 7th along Y positive direction pre-
If the structural representation of side-play amount；
Fig. 8 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 8th along Y positive direction pre-
If the structural representation of side-play amount；
Fig. 9 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the 9th along Y negative direction pre-
If the structural representation of side-play amount；
Figure 10 is that the present invention measures the electrical testing structure of epitaxial patterns side-play amount to have the tenth along Y negative direction pre-
If the structural representation of side-play amount.
Detailed description of the invention
By describing the technology contents of the invention, structural feature in detail, being reached purpose and effect, below
To in conjunction with the embodiments and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1～Figure 10, Fig. 1～Figure 10 and show the electrical testing knot measuring epitaxial patterns side-play amount
The schematic diagram of structure 1.Described electrical testing structure 1 is included in the Semiconductor substrate with the first conduction type ion
(not shown) surface carries out the second conduction type ion diffusion, is positioned at described semiconductor substrate surface to be formed
There is the buried regions 10 of the second conduction type ion.It is epitaxially formed at the semiconductor substrate surface with described buried regions 10
There is the epitaxial layer 11 of the second conduction type ion.Described buried regions 10 be positioned at Semiconductor substrate and epitaxial layer 11 it
Between.
It is being positioned at described epitaxial layer 11, and is being positioned at buried regions 10 surface and etches along same offset direction and adulterate
Form some plug districts 12.Described plug district 12 is that the second conduction type ion heavy doping is formed.Described plug district
12 equidistantly and relative to described buried regions 10 along X positive direction, X negative direction, Y positive direction, and Y losing side
To having different default bias amounts.
Wherein, described default bias amount is any value between 0 to 1 times of epitaxial layer 11 thickness.Described slotting
The step-length in bolt district 12 is determined by the precision of the thickness of epitaxial layer 11 and compensation side-play amount.Described step-length is 0.01
Between micron to 1 micron.Such as one epitaxial layer 11 thickness is the technique of 1 micron, and step-length is set to 0.1
Micron, then the mechanism for testing 1 in the positive direction of X includes: 0 micron, 0.1 micron, 0.2 micron, and 0.3 is micro-
Rice, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron, 0.8 micron, 0.9 micron, 1 micron.At X
Negative direction, the rest may be inferred for the positive direction of Y and the mechanism for testing 1 of negative direction.
In the present embodiment, it is listed below different default bias and measures value, but not as limitation of the present invention.
Specifically, i.e. Fig. 1～Fig. 3 show and is respectively provided with first along X positive direction relative to buried regions 10 and presets partially
The structure of the electrical testing structure 1 of shifting amount the 121, second default bias amount the 122, the 3rd default bias amount 123
Schematic diagram.Fig. 4～Fig. 5 show along X negative direction relative to buried regions 10 have the 4th default bias amount 124,
The structural representation of the electrical testing structure 1 of the 5th default bias amount 125.Fig. 6～Fig. 8 show along Y
Positive direction relative to buried regions 10 be respectively provided with the 6th default bias amount 126, the 7th default bias amount 127,
The structural representation of the electrical testing structure 1 of eight default bias amounts 128.Fig. 9～Figure 10 show and bears along Y
Direction has the electrical testing of the 9th default bias amount the 129, the tenth default bias amount 120 relative to buried regions 10
The structural representation of structure 1.
Contact hole 13 is correspondingly formed on surface, described plug district 12.Described contact hole 13 is by being sequentially located at
Conductive connecting line in described plug district 12 electrically connects with outer test circuit.
In the present invention, it is preferred to, described electrical testing structure 1 comprises 3 adjacent plug districts 12, and
First conductive connecting line the 141, second conductive connecting line is sequentially formed at the contact hole 13 in described adjacent plug district 12
142, and the 3rd conductive connecting line 143.
Plug district 12 offsets in same direction, and has each electrical testing structure 1 shape of different default bias amount
Become an electrical testing structure group.Specifically, i.e. in X positive direction, described electrical testing structure 1 relative to
When the default bias of described buried regions 10 measures different value, described each electrical testing structure 1 just constitutes an electricity and surveys
Examination structure group.Similarly, in X negative direction, Y positive direction, and Y negative direction the rest may be inferred corresponding landform
Become different electrical testing structure groups.
Utilize the method that described electrical testing structure 1 measures epitaxial patterns side-play amount, including: to electrical testing
The electrical testing structure 1 with different default bias amount in structure group carries out electrical testing, test electricity respectively
Learn the first resistance between the first conductive connecting line 141 and second conductive connecting line 142 of test structure 1, and
The second resistance between second conductive connecting line 142 and the 3rd conductive connecting line 143,
If described first resistance is equal with described second resistance, then pre-corresponding to this electrical testing structure 1
If side-play amount is just real offset；
If described first resistance is the most unequal with described second resistance, then with described electrical testing structure group
Electrical testing structure 1 in the electrical testing structure group that offset direction, plug district 12 is contrary carries out described electricity respectively
Learn test, if described first resistance is equal with described second resistance, then corresponding to this electrical testing structure 1
Default bias amount be just real offset；
If described first resistance is the most unequal with described second resistance, then described electrical testing structure group with
And the electrical testing structure group contrary with offset direction, described electrical testing structure group plug district 12 chooses first
The default bias amount corresponding to electrical testing structure 1 of resistance and the second resistance difference minimum is as actual shifts
Amount.
Specifically, the square and measurement of X negative direction real offset if carried out X, then in X positive direction
Optional one in the electrical testing structure with different default bias amount of the electrical testing structure group of upper formation,
And this electrical testing structure 1 is carried out electrical testing.That is, choose electrical testing structure 1 and be sequentially located at described
First conductive connecting line the 141, second conductive connecting line 142 at contact hole 13 in adjacent plug district 12, and
3rd conductive connecting line 143 carries out resistance test.Now, tired definition the first conductive connecting line 141 is not led with second
Resistance between the electrical testing structure 1 that electrical wiring 142 is constituted is the first resistance, the second conductive connecting line 142
The resistance of the electrical testing structure 1 constituted with the 3rd conductive connecting line 143 is the second resistance.
If described first resistance is equal with described second resistance, then pre-corresponding to this electrical testing structure 1
If side-play amount is just the real offset of X positive direction.If described first resistance and described second resistance,
Then at the electrical testing structure with different default bias amount of the electrical testing structure group offset along X negative direction
Optional one in 1, and test the first conductive connecting line 141 and the second conductive connecting line of described electrical testing structure 1
The second electricity between the first resistance between 142, and the second conductive connecting line 142 and the 3rd conductive connecting line 143
Resistance, if described first resistance is equal with described second resistance, then inclined corresponding to this electrical testing structure 1
Moving just is real offset；If described first resistance is the most unequal with described second resistance, then described along X
The electrical testing structure group of positive direction skew and choose the along the electrical testing structure group of X negative direction skew
The side-play amount corresponding to electrical testing structure 1 of one resistance and the second resistance difference minimum is real offset.
Similarly, the square and measurement of Y negative direction real offset if carried out Y, then in Y positive direction
Optional one in the electrical testing structure with different default bias amount of the electrical testing structure group formed, and
This electrical testing structure 1 is carried out electrical testing.That is, choose electrical testing structure 1 and be sequentially located at described phase
First conductive connecting line the 141, second conductive connecting line 142, Yi Ji at contact hole 13 in adjacent plug district 12
Three conductive connecting lines 143 carry out series resistance test.Now, definition the first conductive connecting line 141 and second it is not tired of
Resistance between the electrical testing structure 1 that conductive connecting line 142 is constituted is the first resistance, the second conductive connecting line
142 and the 3rd the resistance of electrical testing structure 1 that constituted of conductive connecting line 143 be the second resistance.
If described first resistance is equal with described second resistance, then pre-corresponding to this electrical testing structure 1
If side-play amount is just the real offset of Y positive direction.If described first resistance and described second resistance,
Then at the electrical testing structure with different default bias amount of the electrical testing structure group offset along Y negative direction
Optional one in 1, and test the first conductive connecting line 141 and the second conductive connecting line of described electrical testing structure 1
The second electricity between the first resistance between 142, and the second conductive connecting line 142 and the 3rd conductive connecting line 143
Resistance, if described first resistance is equal with described second resistance, then inclined corresponding to this electrical testing structure 1
Moving just is real offset；If described first resistance is the most unequal with described second resistance, then described along Y
The electrical testing structure group of positive direction skew and choose the along the electrical testing structure group of Y negative direction skew
The side-play amount corresponding to electrical testing structure 1 of one resistance and the second resistance difference minimum is real offset.
By utilizing described electrical testing structure 1 to epitaxial patterns in X positive direction, X negative direction, Y pros
To, and the real offset of Y negative direction measures, and just obtains the real offset of epitaxial patterns.
In sum, the present invention, by utilizing electrical testing structure to measure epitaxial patterns side-play amount, not only makes
Measuring accuracy is higher, and delays figure to the registration error of figure before extension outside can effectively reducing.
Those skilled in the art are it will be appreciated that without departing from the spirit or scope of the present invention, the most permissible
The present invention is carried out various modifications and variations.Thus, if any amendment or modification fall into claims
Time in the protection domain of book and equivalent, it is believed that the present invention contains these amendment and modification.
Claims (9)
1. the electrical testing structure measuring epitaxial patterns side-play amount, it is characterised in that outside described measurement
The electrical testing structure prolonging map migration amount includes:
Buried regions, is formed at semiconductor substrate surface；
Epitaxial layer, is formed at the semiconductor substrate surface with described buried regions；
Plug district, is equidistantly formed in the epitaxial layer on described buried regions surface, and buries with described in same direction
Layer has different default bias amounts；
Contact hole, is formed at surface, described plug district；
And, the first conductive connecting line of sequentially forming at the contact hole in adjacent described plug district,
Two conductive connecting lines, and the 3rd conductive connecting line；
Plug district offsets in same direction, and each electrical testing structure with different default bias amount is formed
One electrical testing structure group.
2. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 1, its feature exists
In, the size of described default bias amount is any value between 0 to 1 times of epitaxy layer thickness.
3. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 1, its feature exists
In, the step-length in described plug district determines according to the thickness of epitaxial layer and the precision of compensation dosage.
4. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 3, its feature exists
In, described step-length is between 0.01 micron to 1 micron.
5. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 3, its feature exists
In, when described epitaxy layer thickness is 1 micron, step-length is 0.1 micron.
6. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 5, its feature exists
In, described electrical testing structure group is included in equidirectional skew, and default bias amount is respectively 0 micron,
0.1 micron, 0.2 micron, 0.3 micron, 0.4 micron, 0.5 micron, 0.6 micron, 0.7 micron, 0.8
Micron, 0.9 micron, the electrical testing structure of 1 micron.
7. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 1, its feature exists
In, the direction of electrical testing structure is along X positive direction, X negative direction, Y positive direction relative to buried regions,
And Y negative direction.
8. the electrical testing structure measuring epitaxial patterns side-play amount as claimed in claim 1, its feature exists
In, described electrical testing structure has 3 adjacent plug districts.
9. one kind utilizes the side that electrical testing structure as claimed in claim 1 measures epitaxial patterns side-play amount
Method, it is characterised in that the method for described measurement epitaxial patterns side-play amount includes:
The electrical testing structure with different default bias amount in electrical testing structure group is carried out electricity respectively
Learn test, test the first resistance between the first conductive connecting line and second conductive connecting line of electrical testing structure,
And the second resistance that second between conductive connecting line and the 3rd conductive connecting line,
If the first resistance and the second resistance are equal, then the default bias amount corresponding to this electrical testing structure
Just it is real offset；
If the first resistance and the second resistance are unequal, then to inclined with described electrical testing structure group plug district
Move the electrical testing structure in electrical testing structure group in opposite direction and carry out described electrical testing respectively, as
Really the first resistance and the second resistance are equal, then the default bias amount corresponding to this electrical testing structure is just real
Border side-play amount；
If the first resistance and the second resistance are unequal, then in described electrical testing structure group and with described
The electrical testing structure group that offset direction, electrical testing structure group plug district is contrary is chosen the first resistance and
The default bias amount corresponding to electrical testing structure of two resistance difference minimums is as real offset.
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| US11854915B2 (en) | 2021-07-09 | 2023-12-26 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
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| CN103137603B (en) * | 2011-11-23 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | Under monitoring polysilicon side wall, light dope injects test structure and the method for stability |
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| JPS57159014A (en) * | 1981-03-25 | 1982-10-01 | Nec Home Electronics Ltd | Measuring method for characteristics of epitaxial semiconductor wafer |
| JPH08330375A (en) * | 1995-05-31 | 1996-12-13 | Oki Electric Ind Co Ltd | Pattern and method for measuring effective gate length of schottky gate field effect transistor |
| JPH10303104A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Method and pattern structure for measuring mask alignment accuracy |
| KR100902080B1 (en) * | 2008-07-11 | 2009-06-15 | 주식회사 엠아이티 | Single plate non-conductor energizing plate, manufacturing method thereof |
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| US6771077B2 (en) * | 2002-04-19 | 2004-08-03 | Hitachi, Ltd. | Method of testing electronic devices indicating short-circuit |
| TW574744B (en) * | 2002-12-27 | 2004-02-01 | Nanya Technology Corp | Misalignment test structure and method thereof |
| TWI401780B (en) * | 2010-07-20 | 2013-07-11 | Ind Tech Res Inst | Structure and method for testing through-silicon via (tsv) |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57159014A (en) * | 1981-03-25 | 1982-10-01 | Nec Home Electronics Ltd | Measuring method for characteristics of epitaxial semiconductor wafer |
| JPH08330375A (en) * | 1995-05-31 | 1996-12-13 | Oki Electric Ind Co Ltd | Pattern and method for measuring effective gate length of schottky gate field effect transistor |
| JPH10303104A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Method and pattern structure for measuring mask alignment accuracy |
| KR100902080B1 (en) * | 2008-07-11 | 2009-06-15 | 주식회사 엠아이티 | Single plate non-conductor energizing plate, manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11854915B2 (en) | 2021-07-09 | 2023-12-26 | Changxin Memory Technologies, Inc. | Electrical test structure, semiconductor structure and electrical test method |
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