CN102082085A - Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor - Google Patents

Abstract

A method for forming an ultra-shallow junction, comprising: providing a semiconductor substrate; performing a first ion implantation in the semiconductor substrate to form a first implantation region; performing a second ion implantation on the first implantation region, and performing a second ion implantation on the first implantation region. Amorphization is performed on the first implanted region; third ion implantation is performed on the amorphized first implanted region, so far, an ultra-shallow junction structure is formed. Wherein, the first ion is boronous fluoride ion, the second ion is tetravalent ion, and the third ion is boron ion. The invention also provides a method for forming the PMOS transistor.

Description

Formation method of ultra-shallow junction structure and PMOS transistor formation method

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming an ultra-shallow junction structure and a method for forming a PMOS transistor. the

Background technique

Ion implantation technology is an impurity doping technology widely used in the formation of various semiconductor devices and integrated circuits. By controlling the current and voltage of the implanted ion beam, the content and distribution of impurities in the semiconductor substrate can be precisely adjusted. the

As we all know, the feature size of semiconductor devices is getting smaller and smaller with the innovation of process technology. According to the requirement of proportional reduction, while the lateral dimension of the device (ie, the line width represented by the feature size) is continuously reduced, the vertical dimension of the device (ie, the depth of the device) is also required to be proportionally reduced. Therefore, an important development direction of ion implantation technology is how to form shallow junctions and ultra-shallow junctions, such as forming lightly doped source regions and lightly doped drain regions of metal oxide semiconductor MOS transistors. the

Threshold voltage is one of the important performance parameters of MOS transistors, which can be improved by increasing the substrate bias effect. the

The substrate bias effect, also known as the body effect, is defined as follows: For a PMOS transistor, when the substrate and the source are in reverse bias (the P substrate is connected to a negative voltage), the depletion region in the substrate becomes thicker, making the depletion layer in the depletion layer The number of fixed charges increases. Due to the balance of charge on both sides of the gate capacitance, the increase in the depletion layer charge will inevitably lead to a decrease in the mobile charge in the channel when the charge on the gate does not change, resulting in a decrease in the conductivity level. To maintain the original conductivity level, the gate voltage must be increased, that is, the number of charges on the gate must be increased. For the device, the existence of the substrate bias voltage will increase the value of the threshold voltage of the PMOS transistor. the

If the body effect is measured by the body effect value γ, the higher the body effect value is, the more obvious the body effect is, and the higher the value of the threshold voltage is. Among them, the expression formula of the body effect value γ is as follows:

$\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; a</span>}}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; Cox</span>}$

In the above formula, ε ₀ is the vacuum dielectric coefficient, q is the amount of elementary charge, _Na is the ion doping concentration in the channel region, and Cox represents the capacitance per unit area of the gate dielectric layer.

Combining the above formulas, it can be seen that if the body effect value γ needs to be increased, it can be achieved by increasing the ion doping concentration _Na in the channel region.

In the prior art, N _a is often increased by increasing the distance between the source terminal and the drain terminal. The specific principle is: when the distance between the source end and the drain end increases, the diffusion of implanted impurities at the source end and the drain end is well controlled, so that the charge from the drain end in the depletion layer is reduced, thereby increasing _Na and improving the volume. effect.

The prior art also discloses a method of increasing the body effect by increasing the thickness of the sidewall, but this will reduce the saturation current of the drain terminal and affect other electrical parameters of the MOS device. the

The Chinese patent application with application number 200710094406.0 provides a method for forming an ultra-shallow junction PMOS transistor, including: providing a semiconductor substrate with a gate structure; amorphizing the substrate; using the gate structure as Mask, perform the first ion implantation into the semiconductor substrate; use the gate structure as a mask, perform the second ion implantation into the semiconductor substrate to form an ultra-shallow junction structure, the atomic number of the first ion implantation is higher than that of the first ion implantation The atomic number of the second ion implantation is large; the ion implantation is performed to form the source electrode and the drain electrode; and the semiconductor substrate is annealed. the

In the above solution, the first ion with a larger atomic number blocks the diffusion of the second ion and improves the bulk effect. the

However, the above process still needs to be further optimized to further increase the threshold voltage of the transistor. the

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming an ultra-shallow junction structure and a method for forming a PMOS transistor, so as to further increase the threshold voltage of the PMOS transistor. the

In order to solve the above problems, the present invention provides a method for forming an ultra-shallow junction, including:

Provide semiconductor substrates;

Performing a first ion implantation in the semiconductor substrate to form a first implantation region;

performing a second ion implantation on the first implantation region, and performing amorphization on the first implantation region;

A third ion implantation is performed on the amorphized first implantation region to form an ultra-shallow junction structure. the

Optionally, the first ion is boronous fluoride ion. the

Optionally, the implantation energy of the first ions ranges from 10 to 30 KeV, and the dose ranges from 1E15 to 3E15/cm ² .

Optionally, the second ion is a tetravalent ion. the

Optionally, the implantation energy range of the second ions is 30-60Kev, and the dose range is 1E15-9E15/cm ² .

Optionally, the third ion is boron ion. the

Optionally, the implantation energy of the third ions ranges from 0.5 to 12Kev, and the dose ranges from 1E13 to 1E14/cm ² .

The invention provides a method for forming a PMOS transistor, comprising:

Provide semiconductor substrates;

forming a gate structure on the semiconductor substrate, wherein the substrates on both sides of the gate structure are source regions and drain regions;

Using the gate structure as a mask, performing first ion implantation on the source region and the drain region to form a first implantation region;

Using the gate structure as a mask, performing a second ion implantation on the first implantation region, and performing amorphization on the first implantation region;

Using the gate structure as a mask, a third ion implantation is performed on the amorphized first implantation region to form an ultra-shallow junction structure. the

Optionally, the first ion is boronous fluoride ion. the

Optionally, the implantation energy of the first ions ranges from 10 to 30 KeV, and the dose ranges from 1E15 to 3E15/cm ² .

Optionally, the second ion is a tetravalent ion. the

Optionally, the implantation energy range of the second ions is 30-60Kev, and the dose range is 1E15-9E15/cm ² .

Optionally, the third ion is boron ion. the

Optionally, the implantation energy of the third ions ranges from 0.5 to 12Kev, and the dose ranges from 1E13 to 1E14/cm ² .

Based on the above research, the method of the present invention raises the implantation of boronous fluoride ions to before the amorphization of the substrate, and utilizes the characteristics that fluorine ions are easier to diffuse in the state of crystalline silicon, so that fluorine ions in crystalline silicon can more easily make the substrate The silicon-oxygen bond in the gate dielectric layer on the bottom surface is broken, and these oxygen ions detached from the silicon-oxygen bond will oxidize the substrate silicon near the gate dielectric layer, which leads to the increase of the gate dielectric layer and reduces the unit of the gate dielectric layer. Area capacitance, thereby increasing the body effect value and increasing the threshold voltage;

At the same time, boronous fluoride ions are slightly heavier than boron ions, which can block the subsequent diffusion of boron ions, thereby controlling the lateral diffusion of boron, which is further conducive to improving the body effect and increasing the threshold voltage of the device. the

Description of drawings

FIG. 1 is a schematic flowchart of a method for forming an ultra-shallow junction structure according to an embodiment of the present invention. the

2 to 6 are schematic cross-sectional structure diagrams of a method for forming an ultra-shallow junction structure according to an embodiment of the present invention. the

FIG. 7 is a schematic flowchart of a method for forming a PMOS transistor according to an embodiment of the method of the present invention. the

8 to 9 are schematic cross-sectional structure diagrams of a method for forming a PMOS transistor according to an embodiment of the present invention. the

Detailed ways

In the method of the present invention, the implantation of boronous fluoride ions is carried out before the amorphization of the substrate, and the feature that the fluorine ions are easier to diffuse in the state of crystalline silicon is utilized, so that the fluorine ions in the crystalline silicon can more easily make the grid on the surface of the substrate The silicon-oxygen bond in the polar dielectric layer is broken, and the oxygen ions detached from the silicon-oxygen bond will oxidize the substrate silicon near the gate dielectric layer, which leads to the increase of the gate dielectric layer. Among them, the formula combined with the above body effect value is as follows:

$\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; a</span>}}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; Cox</span>}$

The increase of the gate dielectric layer will directly lead to Cox in the formula, that is, the reduction of the capacitance per unit area of the gate dielectric layer, thereby increasing the body effect value γ, thereby increasing the threshold voltage;

At the same time, boronous fluoride ions are slightly heavier than boron ions, which can block the diffusion of subsequent boron ions, thereby controlling the lateral diffusion of boron, improving the body effect, and increasing the threshold voltage of the device. the

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. the

In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the invention is not limited to the specific implementations disclosed below. the

Fig. 1 is a schematic flow chart of a method for forming an ultra-shallow junction structure according to an embodiment of the present invention, including:

Execute step S101 to provide a semiconductor substrate;

Executing step S102, performing a first ion implantation in the semiconductor substrate to form a first implantation region;

Executing step S103, performing a second ion implantation on the first implantation region, and performing amorphization on the first implantation region;

Step S104 is executed to perform a third ion implantation on the amorphized first implantation region to form an ultra-shallow junction structure. the

2 to 6 are schematic cross-sectional structure diagrams of an ultra-shallow junction structure forming method according to an embodiment of the present invention. In this embodiment, an ultra-shallow junction structure formed by forming a shallowly doped implanted region (LDD) of a PMOS transistor is used as an example for illustration. . the

A semiconductor substrate is provided. As shown in FIG. 2 , the semiconductor substrate 101 may be single crystal silicon or silicon germanium, or silicon-on-insulator (SOI). Or other materials may also be included, such as III-V compound semiconductors such as gallium arsenide. the

Wherein, an N-type well and a channel region (not shown in the figure) are formed in the semiconductor substrate 101 . An isolation structure is also formed in the substrate 101 , such as a field oxide region or a shallow trench isolation structure (not shown in the figure) formed by a local oxidation method. the

As shown in FIG. 3 , a gate dielectric layer 102 is formed on the surface of the semiconductor substrate 101 . The gate dielectric layer 102 is silicon oxide, silicon nitride or high-K dielectric. As a preferred example, silicon oxide is used in this embodiment. The thickness of the gate dielectric layer 102 is tens to hundreds of angstroms, and its deposition method can be conventional vacuum coating technology, such as furnace tube thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma Volume-enhanced chemical vapor deposition (PECVD) process, this embodiment adopts furnace tube thermal oxidation process. the

Continuing to refer to FIG. 3, a gate electrode layer 103 is formed on the gate dielectric layer 102. The gate electrode layer 103 may be polysilicon, and the thickness of the gate electrode layer 103 is between hundreds to several thousand angstroms. Chemical vapor deposition (LPCVD). the

Next, the gate dielectric layer 102 and the gate electrode layer 103 are patterned by using a resist mask to form a gate structure. The gate structure includes a gate dielectric layer 102 and a gate electrode layer 103 . So far, the structure of the formed PMOS device is shown in FIG. 3 . the

After the gate structure is formed, the semiconductor substrate 101 located on both sides of the gate structure is a source region and a drain region respectively. the

As shown in FIG. 4 , using the gate structure as a mask, the source region and the drain region are implanted with first ions at an acceleration energy of 10-30Kev and a dose of about 1E15-3E15/cm ² , A first implantation region 104 is formed. The first ion is boronous fluoride ion.

Next, as shown in FIG. 5 , using the gate electrode 103 as a mask, the second ion implantation is performed in the first implantation region 104 at an acceleration energy of 30-60Kev and a dose of about 1E15-9E15/cm ² , performing amorphization on the first implanted region 104 . The second ion is a tetravalent ion, and the tetravalent ion may be silicon or germanium.

The purpose of amorphization is to make the crystal lattice of the first implanted region in a disordered state, making it more difficult for subsequent implanted ions to diffuse. the

As an example, silicon ions are used for amorphization, the silicon ion implantation energy is 40Kev, and the implantation concentration is 4E15/cm ² .

Next, as shown in FIG. 6 , using the gate electrode 103 as a mask, under the acceleration energy of 5-12Kev and the dose of about 1E13-1E14/cm ² , in the first implanted region 104 after the amorphization Implanting third ions, the third ions are boron ions. So far, the ultra shallow junction structure 105 is formed.

As an example, the boron ion implantation energy is 10Kev, and the implantation concentration is 5.0E13/cm ² .

The invention also provides a method for forming the PMOS transistor. As shown in Figure 7, including:

Execute step S201 to provide a semiconductor substrate;

Execute step S202, forming a gate structure on the semiconductor substrate, wherein the substrates located on both sides of the gate structure are source regions and drain regions;

Executing step S203, using the gate structure as a mask, performing first ion implantation on the source region and the drain region to form a first implantation region;

Executing step S204, using the gate structure as a mask, performing a second ion implantation on the first implantation region, and performing amorphization on the first implantation region;

Executing step S205, using the gate structure as a mask, performing a third ion implantation on the amorphized first implantation region to form an ultra-shallow junction structure;

Execute step S206, forming sidewalls on both sides of the gate structure;

Executing step S207, performing deep doping on the source region and the drain region to form the source electrode and the drain electrode;

Step S208 is executed, performing a heat treatment process on the semiconductor substrate to form a PMOS transistor. the

Regarding the specific implementation process of the ultra-shallow junction structure in the PMOS transistor, reference may be made to the above-mentioned embodiment of the formation process of the ultra-shallow junction structure, which will not be described in detail here. Please refer to FIG. 6 on the basis of the foregoing, in the structure having the ultra-shallow junction structure 105 , subsequent PMOS transistors are fabricated. the

As shown in FIG. 8 , sidewalls are formed on both sides of the gate electrode 103 . Including: forming a dielectric layer (not shown) on the semiconductor substrate 101, the formation method may be low pressure chemical vapor deposition (LPCVD), the thickness is higher than the height of the gate electrode 103; then, the dielectric layer An etch back process is performed to form sidewalls 106 on both sides of the gate structure. The function of the spacer is to protect the gate electrode 103 . the

Wherein, the dielectric layer may be a silicon oxide material, or may be an oxide layer-silicon nitride-oxide layer (ONO) structure. In this embodiment, silicon oxide is selected as the material of the dielectric layer. the

As shown in FIG. 9 , on the surface of the semiconductor substrate 101 , using the gate structure as a mask, ion implantation is performed on the source region and the drain region to form the source electrode 111 and the drain electrode 112 . In this embodiment, the implanted ion type is P-type, such as boron or arsenic. The dose of ions implanted into the source and the drain is on the order of 10 ¹⁴ -10 ¹⁵ /cm ² , and the energy of implanted ions is 10 to 100 keV.

Finally, a heat treatment process is performed on the semiconductor substrate to form a PMOS transistor. the

The heat treatment is to perform a spike annealing treatment on the semiconductor substrate structure, activate doping ions and recover the crystal lattice damage of the semiconductor substrate caused by ion implantation. The main process of the spike annealing includes: first heating the semiconductor substrate to a certain temperature, and then rapidly raising the temperature after the temperature is stable for a period of time, and cooling down immediately after reaching the peak temperature. The key parameters of the peak annealing process are the peak temperature of the temperature curve, the dwell time of the peak temperature and the temperature divergence (ie, the time for the annealing temperature to remain in the region near the peak temperature). In a specific embodiment, the peak temperature of the spike annealing treatment is 1000 to 1100 degrees Celsius. the

The actual process proves that, through the method of the invention, the body effect value of the PMOS transistor can be doubled, and then the threshold voltage of the PMOS transistor can be doubled. the

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range. the

Claims (14)

1. the formation method of a super shallow junction comprises:

Semiconductor substrate is provided;

In described Semiconductor substrate, carry out first ion and inject, form first injection region;

Second ion is carried out in described first injection region inject, carry out decrystallized described first injection region;

The 3rd ion is carried out in first injection region after decrystallized inject, form super shallow junction structures.

2. the formation method of super shallow junction as claimed in claim 1 is characterized in that, described first ion is for fluoridizing inferior boron ion.

3. the formation method of super shallow junction as claimed in claim 2 is characterized in that, the injection energy range of described first ion is 10～30Kev, and dosage range is 1E15～3E15/cm ²

4. the formation method of super shallow junction as claimed in claim 1 is characterized in that, described second ion is a quadrivalent ion.

5. the formation method of super shallow junction as claimed in claim 4 is characterized in that, the injection energy range of described second ion is 30～60Kev, and dosage range is 1E15～9E15/cm ²

6. the formation method of super shallow junction as claimed in claim 1 is characterized in that, described the 3rd ion is the boron ion.

7. the formation method of super shallow junction as claimed in claim 6 is characterized in that, the injection energy of described boron ion is 0.5～12Kev for injecting energy range, and dosage range is 1E13～1E14/cm ²

8. transistorized formation method of PMOS comprises:

Semiconductor substrate is provided;

Form grid structure on described Semiconductor substrate, wherein, the substrate that is positioned at the both sides of described grid structure is source region and drain region;

With described grid structure is mask, and the injection of first ion is carried out in described source region and drain region, forms first injection region;

With described grid structure is mask, second ion is carried out in described first injection region inject, and carries out decrystallized to described first injection region;

With described grid structure is mask, the 3rd ion is carried out in first injection region after decrystallized inject, and forms super shallow junction structures.

9. the transistorized formation method of PMOS as claimed in claim 8 is characterized in that, described first ion is for fluoridizing inferior boron ion.

10. the transistorized formation method of PMOS as claimed in claim 9 is characterized in that the injection energy range of described first ion is 10～30Kev, and dosage range is 1E15～3E15/cm ²

11. the transistorized formation method of PMOS as claimed in claim 8 is characterized in that described second ion is a quadrivalent ion.

12. the transistorized formation method of PMOS as claimed in claim 11 is characterized in that the injection energy range of described second ion is 30～60Kev, dosage range is 1E15～9E15/cm ²

13. the transistorized formation method of PMOS as claimed in claim 8 is characterized in that described the 3rd ion is the boron ion.

14. the transistorized formation method of PMOS as claimed in claim 13 is characterized in that the injection energy of described the 3rd ion is 0.5～12Kev, dosage range is 1E13～1E14/cm ²

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