CN102074582B - Integrated circuit structure and method of forming the same - Google Patents

Abstract

The invention provides an integrated circuit structure and a forming method thereof. The first semiconductor fin is on the semiconductor substrate and has a first fin height. The second semiconductor fin is on the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height. The invention has a positive impact on reducing current crowding of the source and drain regions. The increased volume of the stressed source and drain regions also increases the tensile and compressive stress on the channel region of the finfet.

Description

Integrated circuit structure and method of forming the same

technical field

The present invention relates to integrated circuits, and in particular to a semiconductor fin plate, a fin field-effect transistor (Fin field-effect transistor; FinFet) and a forming method thereof.

Background technique

With the continuous down-scaling of integrated circuits and the increase of high-speed requirements for integrated circuits, transistors must have higher driving currents while the size is continuously reduced. In order to meet the above requirements, FinFETs have been developed. Since the channel of the FinFET has an extra sidewall portion besides the top surface of the fin plate, the channel width increases. Since the driving current of the transistor is proportional to the channel width, the driving current of the FinFET is larger than that of the planar transistor.

Contents of the invention

In order to overcome the above disadvantages of the prior art, according to an embodiment of the present invention, the integrated circuit structure includes a semiconductor substrate including a first portion of the semiconductor substrate in the first element region, and a second portion in the second element region. The first semiconductor fin is on the semiconductor substrate and has a first fin height. The second semiconductor fin is on the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

According to an embodiment of the present invention, a method for forming an integrated circuit structure includes: providing a semiconductor substrate, including a first part in a first element region and a second part in a second element region; A first semiconductor fin plate is formed on the semiconductor substrate and has a first fin plate height; and a second semiconductor fin plate is formed on the semiconductor substrate and has a second fin plate height, wherein the first fin plate height is greater than the Second fin height.

The invention also includes other embodiments.

The invention has a positive effect on reducing current crowding in the source and drain regions. Due to the increased volume of the stressed source and drain regions, the tensile and compressive stresses on the channel region of the FinFET are also increased. In addition, the current crowding effect of the silicide region is also reduced.

In order to make the above-mentioned and other objects, features, and advantages of the present invention more clearly understood, the preferred embodiments are specifically listed below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

1-10 are cross-sectional views of intermediate stages in the fabrication of semiconductor fins with different fin heights, according to one embodiment.

11A, 11B, 12, 13, 14A, 14B, 15A-15C, 16A, and 16B are cross-sectional views and perspectives of intermediate stages of manufacturing fin field effect transistors according to another embodiment picture.

Fig. 17 shows a device area in a semiconductor wafer.

FIG. 18 shows a SRAM comprising two FinFETs with fins having different fin heights.

Wherein, the reference signs are explained as follows:

20～substrate

100, 200～component area

22～cushion

24. 317～mask layer

30, 30_1, 30_2～shallow trench isolation area

134, 234～photoresist

136, 236 ~ depression

138, 238, 310～fins

H _fin1 , H _fin2 , H _fin '～fin height

160, 260～fin field effect transistor

150, 250, 314 ~ gate dielectric

152, 252, 316 ~ grid electrode

318～fine interstitial objects

320～Gate spacers

324～Epitaxial semiconductor layer

T～Thickness

328～dotted line

Line 327, 329~

330, 332～silicide area

Detailed ways

Several different embodiments are provided due to different features of the invention. The specific elements and arrangements in the present invention are for simplicity, but the present invention is not limited to these embodiments. For example, a description of forming a first element on a second element may include embodiments in which the first element is in direct contact with the second element, as well as embodiments having additional elements formed between the first element and the second element such that the second element An embodiment in which one element is not in direct contact with a second element.

The present invention provides a novel method to form semiconductor fins and FinFETs with different fin heights. This disclosure illustrates intermediate steps in the manufacture of embodiments and discusses various embodiments. In the illustrations and descriptions of the respective embodiments, similar elements are denoted by similar reference numerals.

Referring to FIG. 1 , a semiconductor substrate 20 is provided. In one embodiment, the semiconductor substrate 20 includes silicon. Other commonly used materials such as carbon, germanium, gallium, arsenic, indium, and/or phosphorus may also be included in the semiconductor substrate.

The semiconductor substrate 20 includes a part in the device region 100 and a part in the device region 200 . In one embodiment, the device areas 100 and 200 are different areas, including a logic core (logic core) area, a storage area (such as an embedded static random access memory area), an analog (analog) area, an input/output (IO, It is also called a peripheral (peripheral) area, a dummy area (to form a dummy pattern), and the like. The above-mentioned reference device area is shown in FIG. 17 . In one embodiment, the device area 100 is a logic core area, and the device area 200 is an input/output area. In another embodiment, the device region 100 is a p-type FinFET region, and the device region 200 is an n-type FinFET region.

A pad layer 22 and a mask layer 24 may be formed on the semiconductor substrate 20 . The pad layer 22 may be a thin film including, for example, silicon oxide formed by a thermal oxidation process. The pad layer 22 can serve as an adhesive layer between the semiconductor substrate 20 and the mask layer 24 . Pad layer 22 may also serve as an etch stop layer for etch mask layer 24 . In one embodiment, masking layer 24 is formed of silicon nitride, such as by low pressure chemical vapor deposition (LPCVD). In another embodiment, the mask layer 24 is formed by thermal nitridation of silicon or plasma anodic nitridation. The mask layer 24 serves as a hard mask in the subsequent photolithography process.

STI regions 30 (indicated as 30_1 and 30_2 ) are formed in the substrate 20 . The depth of STI region 30 may be between about 100 nm and about 250 nm, but other depths may also be used. However, it should be understood that the dimensions described herein are for example only, and may vary depending on the formation techniques used. The shallow trench isolation region 30 can be formed by a known method, so its process details will not be detailed here.

Referring to FIG. 2 , the device region 100 is exposed using the photoresist 134 as a mask to expose the device region 200 . Then, the exposed STI region 30_2 is recessed in the etching step to obtain the recess 236 in the substrate 20 . The resulting structure is shown in Figure 3. The portion of the semiconductor substrate 20 between the recesses 236 thus forms a fin 238 whose fin height is denoted as H _fin2 . In one embodiment, the fin height H _fin2 is between 15 nm and about 30 nm, but it can be larger or smaller. The photoresist 134 is then removed.

Referring to FIG. 4 , the device region 200 is exposed using the photoresist 234 as a mask to expose the device region 100 . The exposed STI region 30_1 is recessed in the etching step to obtain a recess 136 , as shown in FIG. 5 . The portion of the semiconductor substrate 20 between the recesses 136 thus forms a fin 138 whose fin height is denoted as H _fin1 . In one embodiment, the fin height H _fin1 is between 25 nm and about 40 nm, but it can be larger or smaller. The fin heights H _fin1 and H _fin2 are different from each other. The absolute value of the difference in fin height (H _fin1 -H _fin2 ) may be greater than about 5 nm, more or greater than about 10 nm. Also, the ratio of H _fin1 /H _fin2 may be greater than about 1.25, more or greater than about 1.33.

Then, as shown in FIG. 6 , the mask layer 24 and pad layer 22 are removed. If the mask layer 24 is formed of silicon nitride, it can be removed by hot phosphoric acid wet etching, and if the pad layer 22 is formed of silicon oxide, it can be removed by dilute hydrofluoric acid. It should be noted that as shown in FIG. 6 , the portion of the substrate 20 below the bottom of the STI region 30 can be regarded as a semiconductor substrate, and the fins 138 and 238 can be regarded as being on the semiconductor substrate.

FIG. 7 illustrates the formation of FinFETs 160 and 260 in device region 100 and device region 200 , respectively. First, well dopants are introduced into the exposed fins 138 and 238 by, for example, implantation. In one embodiment, the device region 100 is a p-type fin field effect transistor region, the device region 200 is an n-type fin field effect transistor region, and the n-type impurity implantation is performed in the fin plate 138 to dope the n-type impurity. a p-type impurity such as phosphorus, and a p-type impurity implant is performed in the fin 238 to dope the p-type impurity such as boron. Gate dielectrics 150 and 250 are formed to cover the top surfaces and sidewalls of fins 138 and 238 , respectively. Gate dielectrics 150 and 250 may be formed by thermal oxidation and thus may include thermal silicon oxidation. Gate electrodes 152 and 252 are then formed on gate dielectrics 150 and 250, respectively. In one embodiment, each gate electrode 152 and 252 covers more than one fin 138 and 238 , such that each resulting FinFET 160 and 260 includes more than one fin 138 and 238 , respectively. In another embodiment, each fin 138 and 238 may be used to form a FinFET. The remaining components of the FinFET are then formed, including source and drain regions and source and drain silicides (not shown). The processes for forming these components are well known, so they will not be repeated here.

8 to 10 show another embodiment. The initial structure in this embodiment is similar to that in FIG. 1 . Then, referring to FIG. 8 , after forming the photoresist 234 in the device region 200 , a first implantation is performed with a first dose to dope the first impurity in the shallow trench isolation region 30_1 . The resulting shallow trench isolation region has a first impurity concentration. Next, as shown in FIG. 9 , the photoresist 234 is removed to form the photoresist 134 . A second implant is performed with a second dose to dope the second impurity in the STI region 30_2. The resulting shallow trench isolation region has a second impurity concentration. In one embodiment, the first impurity includes phosphorus and the second impurity includes boron.

Then, as shown in FIG. 10 , the photoresist 134 is removed, and the shallow trench isolation region 30 is recessed, for example, by wet etching or other methods. Due to the different doping concentration of the shallow trench isolation regions 30_1 and 30_2 , the etching rates of the shallow trench isolation regions 30_1 and 30_2 are different, and thus the formed fin heights H _fin1 and H _fin2 are different. By making the patterning density of the STI region 30_1 different from that of the STI region 30_2 to introduce a pattern loading effect, the difference between the fin heights H _fin1 and H _fin2 can be increased, so that The difference between the etch rates of the STI regions 30_1 and 30_2 increases even more. In another embodiment, the doping of the shallow trench isolation as shown in FIG. 8 and FIG. 9 is not performed. However, the patterning density of the STI region 30_1 is different from the patterning density of the STI region 30_2 , and the difference in fin height is caused by the pattern loading effect.

In subsequent steps, the hard mask 24 and pad layer 22 are removed to form the structure shown in FIG. 6 . As shown in FIG. 7 , the process continues to form FinFETs 160 and 260 .

By means of different fin heights in different device regions, the junction window can be increased, that is, the fin heights of FinFETs in different device regions are no longer considered as one (tiedtogether). There are different heights of the fins in different device regions, which can make the performance regulation of the device regions easier. In addition, in one embodiment, the FinFET 160 ( FIG. 7 ) is a p-type FinFET in the device region 100 , and the FinFET 260 is an n-type FinFET in the device region 200 , the height of the fin formed on the p-type FinFET 160 is greater than the height of the fin on the n-type FinFET 260 . Accordingly, the p-type FinFET 160 and the n-type FinFET 260 can be applied to the same SRAM device ( FIG. 18 ). For example, the p-type FinFET 160 may be a pull-up transistor, and the n-type FinFET 260 may be a pull-down transistor. Compared with the n-type FinFET 260 which has higher electron mobility, the larger fin height of the p-type FinFET 160 can compensate for its lower hole mobility. The performance of the p-type FinFET 160 and the performance of the n-type FinFET 260 can thus be balanced.

FIGS. 11A-16B show intermediate stages of manufacturing a FinFET according to another embodiment, wherein the STI region 30 has different recess depths in a single FinFET. First, referring to FIG. 11A and FIG. 11B , a semiconductor fin 310 is formed, which may be a silicon fin made of the same material as the underlying substrate 20 . The formation of the semiconductor fin 310 may be substantially the same as the formation of the fins 138 and 238 in FIGS. 2-6 . FIG. 11A shows a longitudinal cross-sectional view, where the dotted line indicates that the fin plate 310 is connected to the substrate 20 by a semiconductor strip. Figure 1 IB shows a transverse cross-sectional view. The fin height of the semiconductor fin 310 is H _fin , and the fin width of the fin 310 is W _fin .

Then, as shown in perspective view in FIG. 12 , a gate dielectric 314 and a gate electrode 316 are formed. A gate dielectric 314 is formed on the top surface and sidewalls of the fin 310 . A gate electrode is formed on the gate dielectric 314 . The semiconductor fin 310 may then be implanted to form lightly doped source and drain (LDD) regions. In one embodiment, as shown in FIG. 13 , fine spacers 318 can be formed on the sidewalls of the gate dielectric 314 and the gate electrode 316, wherein the shallowly doped source and drain regions can be formed in the fine gaps. before or after the formation of object 318. Optionally, a masking layer 317 is formed, which may be nitride. FIG. 13 also shows masking layer 317 .

Next, as shown in FIG. 14A , gate spacers 320 are formed. The gate spacers 320 may include the previously formed fine spacers 318 . It should be understood that the gate spacer 320 can have many different variations. For example, as shown in FIG. 14A , each gate spacer 320 may have a nitride-oxide-nitride-oxide (NONO structure). In another embodiment, each gate spacer 320 may only include a nitride layer on an oxide layer (referred to as an NO structure). A recess is formed on the exposed portion of the STI region 30 on the opposite sidewall of the semiconductor fin 310 , which portion is not covered by the gate electrode 316 . A perspective view of the structure of Figure 14A is shown in Figure 14B. The height of the fin 310 and the gate spacer 320 are not shown for clarity. The fin 310 of the resulting structure has two heights. The portion of the fin 310 (also including the channel region of the formed FinFET) covered by the gate spacer 320 and the gate electrode 316 has a fin height H _fin which is the same as that shown in FIG. 11B . Due to the recess of the STI region 30 , the uncovered portion of the semiconductor fin 310 has an increased fin height H _fin ′. In one embodiment, H _fin ′ is about 2 nm, or greater than about 10 nm, greater than the fin height H _fin . Alternatively, the ratio of H _fin '/H _fin can be greater than about 1.05, more alternatively can be greater than about 1.08, or between about 1.05 and about 1.5.

Then, as shown in FIG. 15A , the exposed portion of the semiconductor fin 310 is epitaxially grown to form an epitaxial semiconductor layer 324 . The epitaxial semiconductor layer 324 may include silicon, germanium, carbon, and/or other known semiconductor materials. In one embodiment, the resulting FinFET is p-type, and the epitaxial semiconductor layer 324 may include silicon and may further include germanium. In another embodiment, where the resulting FinFET is n-type, the epitaxial semiconductor layer 234 may include silicon and may further include carbon. The thickness T of the epitaxially grown semiconductor layer may be greater than about 10 nanometers.

FIG. 15B shows another cross-sectional view of the structure shown in FIG. 15A, wherein the cross-sectional view is taken through the vertical plane crossing line 15B-15B in FIG. 15A. The fin height _Hfin is indicated in Figure 15B. Figure 15C shows another cross-sectional view of the structure of Figure 15A, where the cross-sectional view is taken through the vertical plane crossing line 15C-15C in Figure 15A. The fin height _Hfin ' is indicated in Figure 15C. Compared with FIGS. 15B and 15C , it can be found that the volume of the epitaxial semiconductor layer 234 increases due to the increase of the fin height H _fin . If the fin height of the semiconductor fin does not increase from the value H _fin to the value H _fin ′, the epitaxial semiconductor layer 234 is only limited within the region of the dotted line 328 . In FIGS. 15B and 15C , the bottom of semiconductor fin 310 is considered to be flush with the upper surface of the STI region on the opposite side of fin 310 , although there is no clearly visible bottom. Accordingly, as shown in FIG. 15B , the bottom of semiconductor fin 310 is directly under gate electrode 316 , as indicated by line 327 . Also, in FIG. 15C , the bottom of semiconductor fin 310 is not covered by gate electrode 316 and gate spacer 320 , as indicated by line 329 . Line (bottom) 329 is below line (bottom) 327 .

Referring to FIG. 16A , implantation is performed to form source and drain regions in the semiconductor fin 310 and the epitaxial semiconductor layer 324 . The mask layer (hard mask) 317 is removed, and a source/drain silicide region 330 and a gate silicide region 332 are formed on the epitaxial semiconductor layer 324 . The source/drain silicide region and the gate silicide region 332 can be formed using known methods. After the silicide regions 330 and 332 are formed, the epitaxial semiconductor layer 324 may be completely or partially consumed. In the resulting structure, the silicide region 330 is separated from the semiconductor fin 310 by the remainder of the epitaxial semiconductor layer, or is in direct contact with the fin 310 .

FIG. 16B shows another cross-sectional view of the structure shown in FIG. 16A, wherein the cross-sectional view is taken through the vertical plane crossing line 16B-16B in FIG. 16A. The volume of the source and drain regions is increased by recessing the STI region 30 before epitaxially forming the epitaxial semiconductor layer 324 . This has the positive effect of reducing current crowding in the source and drain regions. Due to the increased volume of the stressed source and drain regions, the tensile and compressive stresses on the channel region of the FinFET are also increased. In addition, the size of the silicide region 330 increases due to the increase in the area of the sidewall of the epitaxial semiconductor layer 324 , which also reduces the current crowding effect of the silicide region 330 .

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any skilled person in the art can make arbitrary changes and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention should be determined by the scope defined by the appended claims.

Claims (6)

1. An integrated circuit structure comprising: a semiconductor substrate comprising a first portion in a first element region and a second portion in a second element region; a first semiconductor fin on the semiconductor substrate and having a first fin height; a second semiconductor fin on the semiconductor substrate and having a second fin height, wherein the first fin height is greater than the second fin height; A first shallow trench isolation region and a second shallow trench isolation region are located on opposite sides of the first semiconductor fin plate, and the first and second shallow trench isolation regions have a first impurity having - the first impurity concentration; A third shallow trench isolation region and a fourth shallow trench isolation region are located on opposite sides of the second semiconductor fin plate, and the third and fourth shallow trench isolation regions have a second impurity having a second impurity concentration, and the first impurity concentration is different from the second impurity concentration; A first FinFET comprising: a first gate dielectric on a top surface and sidewalls of the first semiconductor fin; and a first gate electrode on the first gate on a dielectric; and A second FinFET comprising: a second gate dielectric on a top surface and sidewalls of the second semiconductor fin; and a second gate electrode on the second gate On the dielectric; wherein the first FinFET is a p-type FinFET, and the second FinFET is an n-type FinFET, and wherein the first FinFET and the The second FinFET is a FinFET in the same SRAM cell. 2. The integrated circuit structure of claim 1, wherein the top surface of the first semiconductor fin is at the same height as the top surface of the second semiconductor fin. 3. The integrated circuit structure of claim 1, wherein the first STI region and the second STI region have a first top surface flush with a bottom surface of the first semiconductor fin; and wherein the third shallow trench isolation region and the fourth shallow trench isolation region have a second top surface flush with a bottom surface of the second semiconductor fin plate, and wherein the first top surface is lower than the second top surface surface. 4. The integrated circuit structure of claim 1, wherein a ratio of the first fin height to the second fin height is greater than 1.25. 5. A method for forming an integrated circuit structure, comprising: providing a semiconductor substrate including a first portion in a first element region and a second portion in a second element region; forming a first semiconductor fin on the semiconductor substrate and having a first fin height; and forming a second semiconductor fin on the semiconductor substrate and having a second fin height, wherein the first fin height is greater than the second fin height; Wherein the forming steps of the first semiconductor fin plate and the second semiconductor fin plate include: A first shallow trench isolation region and a second shallow trench isolation region are formed in the semiconductor substrate, wherein the first shallow trench isolation region is in the first element region, and the second shallow trench isolation region is in the first element region in the second element area; doping the first STI region with a first impurity to a first impurity concentration; doping the second shallow trench isolation region with a second impurity to a second impurity concentration different from the first impurity concentration; and Simultaneously recess the first shallow trench isolation region and the second shallow trench isolation region. 6. The forming method of the integrated circuit structure as claimed in claim 5, further comprising: Forming a first FinFET includes: forming a first gate dielectric on a top surface and sidewalls of the first semiconductor fin; and forming a first gate electrode on the first gate dielectric; and Forming a second FinFET includes: forming a second gate dielectric on a top surface and sidewalls of the second semiconductor fin; and A second gate electrode is formed on the second gate dielectric.

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