CN102074215A - Liquid crystal display and control method thereof - Google Patents

Abstract

A method for controlling a liquid crystal display accumulates a count value when a backlight module of the liquid crystal display is closed. When the counting value is larger than a preset shutdown time, the liquid crystal display is indicated to enter a power-saving mode. Therefore, through discharging a plurality of pixels of the liquid crystal display, the liquid crystal display can be prevented from generating a flicker phenomenon after being recovered from the power saving mode, and the plurality of pixels are prevented from being damaged due to direct current bias voltage.

Description

Liquid crystal display and its control method

technical field

The invention relates to a method for controlling a liquid crystal display, and more specifically, relates to a method for preventing the liquid crystal display from flickering after recovering from a power-saving mode.

Background technique

Please refer to Figure 1. FIG. 1 is a circuit diagram illustrating a discharge signal generating circuit 100 of the background art. The discharge signal generating circuit 100 is used to discharge the pixels of the liquid crystal display when the liquid crystal display is turned off, so as to prevent the pixels of the liquid crystal display from being damaged by the DC bias voltage for a long time. The discharge signal generating circuit 100 includes a voltage dividing circuit 110 , a comparator CMP, a transistor Q1 and a resistor R1 . The transistor Q1 includes a first terminal (1), a second terminal (2), and a control terminal (C). The first end of the transistor Q1 is coupled to the resistor R1 for generating the discharge signal SXON. The second end of the transistor Q1 is coupled to the ground. The control terminal C of the transistor Q1 is coupled to the comparator CMP. One end of the resistor R1 is coupled to the first end of the transistor Q1, and the other end of the resistor R1 is coupled to the voltage source VTCON_PW, wherein the voltage source VTCON_PW is used to provide the voltage VTCON_PW as a power supply for a display controller in the LCD. The voltage dividing circuit 110 includes resistors R2 and R3. The resistors R2 and R3 are coupled between the voltage source VTCON_PW and the ground. The voltage dividing circuit 110 is used to generate a voltage VDET_PW equal to the voltage VTCON_PW. The comparator CMP compares the voltage VDET_PW with a reference voltage VREF. When the voltage VDET_PW is greater than the reference voltage VREF, it means that the power supply VTCON_PW of the display controller is not turned off. At this time, the comparator CMP controls the transistor Q1 to be non-conductive through the control terminal C of the transistor Q1. In this way, the voltage source VTCON_PW pulls the voltage on the first terminal of the transistor Q1 to a high potential through the resistor R1, so that the first terminal of the transistor Q1 generates a discharge signal SXON indicating “no discharge”. When the voltage VDET_PW is lower than the reference voltage VREF, it means that the power supply VTCON_PW of the display controller of the liquid crystal display is turned off. Since when the power supply VTCON_PW of the display controller of the LCD is turned off, it means that the LCD is turned off, so the comparator CMP controls the transistor Q1 to be turned on through the control terminal C of the transistor Q1 at this time. In this way, the ground terminal pulls the voltage on the first terminal of the transistor Q1 to a low potential, so that the first terminal of the transistor Q1 generates a discharge signal SXON indicating “discharge”. When the gate driving circuit of the liquid crystal display receives the discharge signal SXON indicating "discharge", the gate driving circuit will simultaneously activate all the gate lines of the liquid crystal display to discharge the pixels of the liquid crystal display. In this way, the pixels of the liquid crystal display can be prevented from being damaged by the DC bias voltage for a long time.

However, when the display controller of the liquid crystal display communicates with an external graphics processing unit (Graphic processing unit, GPU) through the display port (Display Port) interface, the external graphics processor can directly communicate with the GPU through the display port interface. The display controller issues a command to control the liquid crystal display to enter the power saving mode, and keeps the power supply (VTCON_PW) of the display controller turned on when the liquid crystal display enters the power saving mode. Therefore, at this time, the discharge signal generating circuit 100 of the background art does not generate the discharge signal SXON. In other words, when the external graphics processor controls the LCD to enter the power saving mode through the DisplayPort interface, the gate driving circuit will not discharge the pixels of the LCD. In this way, when the LCD is in the power-saving mode, the pixels in the LCD may be damaged due to long-term DC bias (DC stress), and cause flickering when the LCD recovers from the power-saving mode.

Contents of the invention

The invention provides a method for controlling a liquid crystal display. The method includes: when a backlight module of a liquid crystal display is turned off, accumulating a count value; comparing the count value with a predetermined shutdown time to generate a comparison result; and according to the comparison result, multiple The pixel discharges. The backlight module includes a plurality of light-emitting diodes, and the backlight module receives a backlight power supply voltage to drive the plurality of light-emitting diodes; wherein when the backlight module of the liquid crystal display is turned off, accumulating the count value includes: generating a value equal to a detection voltage of the backlight power supply voltage; and accumulating the count value when the detection voltage is less than a threshold voltage.

According to the comparison result, discharging the plurality of pixels of the liquid crystal display includes: when the comparison result indicates that the count value is greater than the preset shutdown time, discharging the plurality of pixels of the liquid crystal display.

When the comparison result indicates that the count value is greater than the preset shutdown time, discharging the plurality of pixels of the liquid crystal display includes: controlling a gate drive circuit of the liquid crystal display and simultaneously starting the liquid crystal display coupled to the plurality of pixels a plurality of gate lines to discharge the plurality of pixels.

When the comparison result indicates that the count value is greater than the predetermined shutdown time, the count value is reset after a delay time. In this way, it is possible to prevent the liquid crystal display from flickering after recovering from the power saving mode, and to prevent the plurality of pixels from being damaged due to the direct current bias.

The invention further provides a liquid crystal display. The liquid crystal display includes a display panel, including a gate driving circuit, a plurality of gate lines, a plurality of data lines and a plurality of pixels, when the gate driving circuit activates a gate line in the plurality of gate lines , the pixel coupled to the gate line among the plurality of pixels receives data through the corresponding data line; a backlight module is used to provide backlight to the display panel; a display controller is used to turn off the backlight module , accumulating a count value, and comparing the count value with a predetermined power-off time to generate a control signal; and a discharge signal generating circuit, used for according to the control signal and a first voltage received by the display controller, to generate a discharge signal; wherein when the gate drive circuit receives the discharge signal representing discharge, the gate drive circuit simultaneously drives the plurality of gate lines to discharge the plurality of pixels.

The backlight module includes a plurality of light-emitting diodes, and the backlight module receives a backlight power supply voltage to drive the plurality of light-emitting diodes; wherein the display controller includes: a detection circuit, used for according to the backlight power supply voltage and a threshold voltage, A start signal is generated; a counter is used to accumulate a count value when the start signal indicates start; and a first comparator is used to compare the count value with a predetermined shutdown time, and when the count value is less than the predetermined shutdown time time, the first comparator generates the control signal representing a first predetermined logic, and when the count value is greater than the predetermined shutdown time, the first comparator generates the control signal representing a second predetermined logic.

The detection circuit includes: a voltage divider circuit for generating a detection voltage equal to the backlight power supply voltage; and a second comparator for comparing the detection voltage with the threshold voltage, when the detection voltage is less than the threshold voltage, the second comparator generates the enable signal indicating enable.

The display controller further includes: a delay circuit, when the delay circuit receives the control signal representing the second predetermined logic, after a delay time, the delay circuit generates a reset signal; wherein the counter is reset according to the signal to reset the count value.

The discharge signal generation circuit includes: a voltage divider circuit for generating a second voltage equal to the first voltage; a third comparator for generating a comparison signal according to the second voltage and a reference voltage , when the second voltage is greater than the reference voltage, the comparison signal represents a first predetermined logic, and when the second voltage is less than the reference voltage, the comparison signal represents a second predetermined logic; a resistance, including a first terminal Used to receive the first voltage, and a second terminal used to output the discharge signal; a transistor, including a first terminal coupled to the second terminal of the resistor, a second terminal coupled to the ground terminal, and a a control terminal; and an OR gate, comprising a first input terminal for receiving the control signal, a second input terminal for receiving the comparison signal, and an output terminal coupled to the control terminal of the transistor, when the comparison signal or the control signal represents the second predetermined logic, the OR gate controls the transistor to be turned on so that the discharge signal represents discharge, and when both the comparison signal and the control signal represent the first predetermined logic, the OR gate The gate controls the transistor to turn off so that the discharge signal indicates no discharge. In this way, it is possible to prevent the liquid crystal display from flickering after recovering from the power saving mode, and to prevent the plurality of pixels from being damaged due to the direct current bias.

Description of drawings

1 is a circuit diagram illustrating a discharge signal generating circuit of the background art;

Figure 2 is a schematic diagram illustrating a liquid crystal display of the present invention;

3 is a schematic diagram illustrating a display controller and a discharge signal generating circuit of the present invention;

[Description of main component symbols]

1, 2, C endpoint

110, 2311, 241 Voltage divider circuit

200 LCD display

201 Graphics processor

210 Display panel

211 Gate drive circuit

212 Data drive circuit

220 Backlight Module

230 Display controller

232 counter

233 Delay circuit

240, 100 Discharge signal generating circuit

242 OR gate

CLC LCD Capacitor

CST Storage Capacitor

CMP, CMP1～CMP3 Comparator

D1～DM data line

G1～GN Gate line

I1, I2 input terminals

NC counter value

NOFF Scheduled shutdown time

O output terminal

PIX1 Pixel

Q, Q1 Transistor

R1～R5 Resistance

SC Control Signal

SCLK clock signal

SCMP Comparison Signal

SRST reset signal

SXON discharge signal

VDET1 Detection voltage

VDET_PW voltage

VREF Reference voltage

VTCON_PW Voltage source

VTH Threshold voltage

Detailed ways

Please refer to Figure 2. FIG. 2 is a schematic diagram illustrating a liquid crystal display 200 of the present invention. The liquid crystal display 200 includes a display panel 210 , a backlight module 220 , a display controller 230 , and a discharge signal generation circuit 240 . The display panel 210 includes a gate driving circuit 211 , a data driving circuit 212 , gate lines G1 -GN, data lines D1 -DM and a plurality of pixels. The structure of the plurality of pixels can be illustrated by taking the pixel PIX1 as an example. The pixel PIX1 includes a transistor Q, a liquid crystal capacitor CLS and a storage capacitor CST. The transistor Q includes a first terminal (1), a second terminal (2), and a control terminal (C). A first terminal of the transistor Q is coupled to the data line D1, a second terminal of the transistor Q is coupled to the liquid crystal capacitor CLS and the storage capacitor CST, and a control terminal of the transistor Q is coupled to the gate line G1. The liquid crystal capacitor CLS and the storage capacitor CST are coupled in parallel between the second terminal of the transistor Q and the ground terminal. When the gate driving circuit 211 activates the gate line G1, the transistor Q is turned on, so the data driving circuit 212 can write data to the storage capacitor CST of the pixel PIX1 through the data line D1 and the transistor Q. Therefore, it can be known from the above description that when the gate driving circuit 211 activates one of the gate lines G1˜GN, the pixels coupled to the gate line among the plurality of pixels can pass through the corresponding data lines D1˜GN. DM receives data. The backlight module 220 is used to provide backlight for the display panel 210 . The display controller 230 is used to communicate with an external graphics processor 201 . The graphics processor 201 can send a command to the display controller 230 to control the LCD 200 to enter the power saving mode. For example, the graphics processor 201 communicates with the display controller 230 through a DisplayPort interface. Because when the graphics processor 201 sends a command through the display port interface to control the liquid crystal display 200 to enter the power saving mode, the graphics processor 201 controls the backlight module 220 to turn off at the same time, so the display controller 230 can be accumulated when the backlight module 220 is turned off. A count value, and compare the count value with a predetermined shutdown time. When the count value is greater than the preset shutdown time, it means that the liquid crystal display 200 enters the power saving mode. At this time, the display controller 230 generates a control signal SC representing logic “1” to control the discharge signal generating circuit 240 to generate a discharge signal SXON representing “discharge”. In this way, when the gate driving circuit 211 activates the gate lines G1 -GN simultaneously according to the discharge signal SXON indicating “discharge”, so as to discharge a plurality of pixels of the liquid crystal display 200 . The structure and working principle of the display controller 230 and the discharge signal generating circuit 240 will be further described below.

Please refer to Figure 3. FIG. 3 is a schematic diagram illustrating the display controller 230 and the discharge signal generating circuit 240 . In FIG. 3 , it is assumed that the backlight module 220 is a light-emitting diode (Light-Emitting Diode, LED) backlight module. The backlight module 220 includes a plurality of light emitting diodes, and the backlight module 220 receives a backlight power supply voltage VLED to drive the plurality of light emitting diodes in the backlight module 220 . The display controller 230 accumulates the count value NC when the backlight module 220 is turned off, and compares the count value NC with a predetermined off time NOFF to generate the control signal SC. The display controller 230 includes a detection circuit 231 , a counter 232 , a comparator CMP1 , and a delay circuit 233 . The detection circuit 231 generates

Signal SEN. The detection circuit 231 includes a voltage dividing circuit 2311 and a comparator CMP2. The voltage dividing circuit 2311 includes resistors R4 and R5. One end of the resistor R4 receives the backlight power supply voltage VLED, and the other end of the resistor R4 is coupled to the resistor R5. One end of the resistor R5 is coupled to the resistor R4, and the other end of the resistor R5 is coupled to the ground. In this way, the voltage dividing circuit 2311 can generate the detection voltage VDET1 equivalent to the backlight power supply voltage VLED. The comparator CMP2 is used to compare the detection voltage VDET1 with a threshold voltage VTH. When the detection voltage VDET1 is greater than the threshold voltage VTH, it indicates that the backlight module 220 is not turned off. At this time, the comparator CMP2 generates an enable signal SEN indicating "not start". When the detection voltage VDET1 is lower than the threshold voltage VTH, it means that the backlight module 220 is turned off. At this time, the comparator CMP2 generates an enable signal SEN indicating "start". The counter 232 receives the enable signal SEN. When the start signal SEN indicates “start”, the counter 232 accumulates and outputs a count value NC. For example, the counter 232 can accumulate the count value NC according to the clock signal SCLK received by the display controller 230 . Whenever the counter 232 receives a clock signal SCLK, the counter 232 increases the count value NC by one. The comparator CMP1 is used to compare the count value NC with a predetermined off time NOFF. When the count value NC is less than the predetermined off time NOFF, the comparator CMP1 generates a control signal SC representing logic "0". When the count value NC is accumulated beyond the preset shutdown time NOFF, it means that the liquid crystal display 200 is not turned off, but enters the power saving mode. At this time, the comparator CMP1 generates a control signal SC representing logic "1". The delay circuit 233 is used for generating a reset signal SRST after a delay time when receiving the control signal SC representing a predetermined logic “1”. The counter 232 can reset the count value NC according to the reset signal SRST. In this way, when the backlight module 220 is turned off next time, the counter 232 can accumulate the count value NC again.

The discharge signal generation circuit 240 is used for generating the discharge signal SXON according to the control signal SC and a voltage VTCON_PW received by the display controller 230 (wherein VTCON_PW is the power supply of the display controller 230 ). The discharge signal generating circuit 240 includes a voltage dividing circuit 241 , a comparator CMP3 , a resistor R1 , a transistor Q1 , and an OR gate 242 . The transistor Q1 includes a first terminal (1), a second terminal (2), and a control terminal (C). The first end of the transistor Q1 is coupled to the resistor R1 for generating the discharge signal SXON. The second end of the transistor Q1 is coupled to the ground. The control terminal C of the transistor Q1 is coupled to the OR gate 242 . One end of the resistor R1 is coupled to the first end of the transistor Q1, and the other end of the resistor R1 is coupled to the voltage source VTCON_PW. The voltage dividing circuit 241 includes resistors R2 and R3. The resistors R2 and R3 are coupled between the voltage source VTCON_PW and the ground. The voltage dividing circuit 241 is used to generate a voltage VDET_PW equal to the voltage VTCON_PW. The comparator CMP3 compares the voltage VDET_PW with a reference voltage VREF. When the voltage VDET_PW is greater than the reference voltage VREF, it means that the power supply VTCON_PW of the display controller 230 is not turned off. At this time, the comparator CMP3 generates a comparison signal SCMP representing logic "0". When the voltage VDET_PW is lower than the reference voltage VREF, it means that the power supply VTCON_PW of the display controller 230 is turned off. At this time, the comparator CMP3 generates a comparison signal SCMP representing logic "1". The OR gate 242 includes input terminals I1 and I2, and an output terminal O. The input terminal I1 is used to receive the control signal SC, the input terminal I2 is used to receive the comparison signal SCMP, and the output terminal O is coupled to the control terminal of the transistor Q1. When both the comparison signal SCMP and the control signal SC represent logic “0”, it means that neither the power supply VTCON_PW nor the backlight module of the display controller 230 is turned off. In other words, the liquid crystal display 200 is not turned off, nor enters the power saving mode. At this time, the OR gate 242 controls the transistor Q1 to be turned off through the control terminal C of the transistor Q1. In this way, the voltage source VTCON_PW pulls the voltage on the first end of the transistor Q1 to a high potential through the resistor R1, so that the discharge signal SXON indicates “no discharge”. When the comparison signal SCMP represents logic “1”, it means that the power supply VTCON_PW of the display controller 230 is turned off. In other words, the liquid crystal display 200 may be turned off or enter the power saving mode. At this time, the OR gate 242 controls the transistor Q1 to be turned on through the control terminal C of the transistor Q1. In this way, the ground terminal pulls the voltage on the first terminal of the transistor Q1 to a low potential through the resistor R1, so that the discharge signal SXON indicates “discharge”. When the control signal SC represents logic “1”, it means that the backlight module 220 is turned off for more than the predetermined shutdown time NOFF, and the power supply VTCON_PW of the display controller 230 is not turned off. In other words, the LCD 200 enters the power saving mode. For example, the graphics processor 201 sends commands through the DisplayPort interface to control the LCD 200 to enter the power saving mode. Therefore, at this time, the OR gate 242 controls the transistor Q1 to be turned on through the control terminal C of the transistor Q1. In this way, the ground terminal pulls the voltage on the first terminal of the transistor Q1 to a low potential through the resistor R1, so that the discharge signal SXON indicates “discharge”. When the gate driving circuit 211 receives the discharge signal SXON indicating “discharging”, the gate driving circuit 211 simultaneously activates the gate lines G1 -GN of the LCD 200 to discharge the pixels of the LCD 200 . In this way, the pixels of the liquid crystal display 200 can be prevented from being damaged by the DC bias voltage for a long time, and flickering phenomenon after the liquid crystal display 200 recovers from the power saving mode can be avoided.

To sum up, in the liquid crystal display 200, when the backlight module 220 is turned off, the display controller 230 accumulates the count value NC, and the display controller 230 compares the count value NC with the predetermined off time NOFF to generate a comparison result. The discharge signal generation circuit 240 generates a discharge signal SXON according to the comparison result to discharge a plurality of pixels of the liquid crystal display 200 . More specifically, when the comparison result indicates that the count value NC is greater than the predetermined shutdown time NOFF, it means that the liquid crystal display 200 is not powered off, but enters the power saving mode. Therefore, the display controller 230 generates the control signal SC representing logic "1". The delay circuit 233 generates a reset signal SRST to reset the count value NC after a delay time according to the control signal SC representing logic “1”. And the OR gate 242 in the discharge signal generating circuit 240 controls the transistor Q1 to be turned on according to the control signal SC representing logic "1". In this way, the ground terminal pulls the voltage on the first terminal of the transistor Q1 to a low potential through the transistor Q1, so that the first terminal of the transistor Q1 generates a discharge signal SXON indicating “discharge”. In other words, at this moment, the discharge signal generating circuit 240 controls the gate driving circuit 211 to activate the gate lines G1 -GN coupled to a plurality of pixels in the LCD 200 to discharge the pixels in the LCD 200 . In this way, the LCD 200 of the present invention can be prevented from flickering after recovering from the power saving mode, and the pixels in the LCD 200 of the present invention can be prevented from being damaged due to long-term DC bias.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (10)

1. method of controlling LCD comprises:

When a backlight module of a LCD is closed, accumulative total one count value; Relatively this count value and is scheduled to the unused time, to produce a comparative result; And, a plurality of pixels of this LCD are discharged according to this comparative result.

2. the method for control LCD as claimed in claim 1 is characterized in that: this backlight module comprises a plurality of light emitting diodes, and this backlight module receives a backlight electric power voltage, to drive these a plurality of light emitting diodes; Wherein when this backlight module of this LCD was closed, this count value of accumulative total comprised: produce geometric ratio and detect voltage in one of this backlight electric power voltage; And when this detects voltage less than a critical voltage, this count value of accumulative total.

3. the method for control LCD as claimed in claim 1, it is characterized in that: according to this comparative result, a plurality of pixels of this LCD are discharged comprise: when this comparative result is represented this count value greater than this predetermined unused time, a plurality of pixels of this LCD are discharged.

4. the method for control LCD as claimed in claim 3, it is characterized in that: when this comparative result is represented this count value greater than this predetermined unused time, a plurality of pixels of this LCD are discharged comprise: a gate driver circuit of controlling this LCD starts many gate lines that are coupled to these a plurality of pixels in this LCD simultaneously, so that these a plurality of pixels are discharged.

5. the method for control LCD as claimed in claim 1 is characterized in that further comprising: when this comparative result is represented this count value greater than this predetermined unused time, and after through a time delay, this count value of resetting.

6. LCD comprises:

One display panel, comprise a gate driver circuit, many gate lines, many data lines and a plurality of pixel, when this gate driver circuit started a gate line in these many gate lines, the pixel that is coupled to this gate line in these a plurality of pixels saw through corresponding data line and receives data;

One backlight module is used to provide this display panel of giving backlight;

One display controller is used for when this backlight module is closed, accumulative total one count value, and relatively this count value and is scheduled to the unused time, to produce a control signal; And

One discharge signal produces circuit, is used for one first voltage that received according to this control signal and this display controller, to produce a discharge signal;

Wherein when this gate driver circuit received this discharge signal of expression discharge, this gate driver circuit drove this many gate lines simultaneously, so that these a plurality of pixels are discharged.

7. LCD as claimed in claim 6 is characterized in that: this backlight module comprises a plurality of light emitting diodes, and this backlight module receives a backlight electric power voltage, to drive these a plurality of light emitting diodes;

Wherein this display controller comprises:

One testing circuit is used for producing an enabling signal according to this a backlight electric power voltage and a critical voltage;

One counter is used for when this enabling signal is represented to start, accumulative total one count value; And

One first comparer, be used for relatively this count value and a predetermined unused time, when this count value during less than this predetermined unused time, this first comparer produces this control signal of expression one first predetermined logic, and when this count value during greater than this predetermined unused time, this first comparer produces this control signal of expression one second predetermined logic.

8. LCD as claimed in claim 7 is characterized in that this testing circuit comprises:

One bleeder circuit is used for producing geometric ratio and detects voltage in one of this backlight electric power voltage; And

One second comparer is used for relatively this detection voltage and this critical voltage, and when this detected voltage less than this critical voltage, this second comparer produced this enabling signal that expression starts.

9. LCD as claimed in claim 6 is characterized in that this display controller comprises in addition:

One delay circuit, when this delay circuit received this control signal of this second predetermined logic of expression, after a time delay, this delay circuit produced a reset signal;

Wherein this counter is according to this reset signal this count value of resetting.

10. LCD as claimed in claim 6 is characterized in that this discharge signal produces circuit and comprises:

One bleeder circuit is used for producing one second voltage of geometric ratio in this first voltage;

One the 3rd comparer is used for producing a comparison signal according to this second voltage and a reference voltage, when this second voltage greater than this reference voltage, this comparison signal is represented one first predetermined logic, and works as this second voltage less than this reference voltage, and this comparison signal is represented one second predetermined logic;

One resistance comprise that one first end is used for receiving this first voltage, and one second end is used for exporting this discharge signal;

One transistor comprises that one first end is coupled to this second end of this resistance, and one second end couples earth terminal, and a control end; And

One or the door, comprise that a first input end is used for receiving this control signal, one second input end is used for receiving this comparison signal, and one output terminal be coupled to this transistorized this control end, when this comparison signal or this control signal are represented this second predetermined logic, should or this transistor turns of gate control, so that this discharge signal is represented discharge, and when this comparison signal and this control signal are all represented this first predetermined logic, should or this transistor of gate control close so that this discharge signal is represented not discharge.

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