CN102064839B - High-speed low-power consumption multi-code-rate Viterbi decoder - Google Patents

Abstract

The invention discloses a Viterbi decoder with high speed, low power consumption and multiple code rates, which includes a branch measurement unit, a comparison selection unit, a path measurement storage unit, a survival path storage unit, an output unit and a control unit, and the comparison selection unit receives The branch metric value of the branch metric unit and the processed surviving path are sent to the surviving path storage unit for decoding processing to obtain decoding bits, and at the same time, the path metric value obtained by adding and comparing is stored in the path metric storage unit for the next time Gabi selection processing. The invention is applicable to a Viterbi decoder of (2, 1, 7) convolutional codes, has the characteristics of high throughput and low power consumption, and can support 1/2, 2/3, 3/4, 5/6 code rates. The decoder adopts a fully parallel add ratio select (ACS) unit, the highest bit is cleared to prevent overflow processing, and a register exchange method that can reduce power consumption is adopted, which can effectively reduce the dynamic power consumption of register flipping, and can be based on the signal-to-noise ratio The size automatically adjusts the power.

Description

A Viterbi Decoder with High Speed and Low Power Consumption and Multiple Code Rates

technical field

The invention relates to a Viterbi decoder in the communication field, in particular to a Viterbi decoder with high speed, low power consumption and multiple code rates.

Background technique

In wireless communication systems, multipath fading caused by reflection, scattering, and diffraction in wireless channels will cause dispersion in the time, frequency, and space domains, which will inevitably introduce distortion and signal judgment errors to transmitted data. Channel coding technology discovers and corrects signal errors that occur during transmission by adding redundant symbols to the information sequence, thereby improving the reliability of the system.

At present, wireless communication has put forward higher and higher requirements for data throughput. For example, the next-generation wireless local area network (WLAN) protocol IEEE 802.11n adopts orthogonal frequency division multiplexing (OFDM), multiple input multiple output (MIMO), and space-time coding. (STBC) and other technologies, the ideal rate of the physical layer is up to 600Mbps. To counteract the effect of OFDM subcarrier fading due to frequency-selective fading channels, it employs forward error correction codes (FEC) and interleaving. One of the channel coding methods in IEEE 802.11n is the convolutional code, and there are four code rates: 1/2, 2/3, 3/4 and 5/6. In modern wireless communication, the data throughput rate of hundreds of megabytes is often required, which puts forward high requirements on the operating frequency and data throughput rate of the decoder. At the same time, the requirements on the cost and power consumption of the wireless device put forward the need to reduce the complexity and power consumption of the decoder implementation. In order to improve the utilization rate of spectrum, multi-rate convolutional codes are generally applied in modern wireless communication. Therefore, the requirements for convolutional codes in practical applications require the corresponding Viterbi decoder to be designed with high speed, low power consumption, and multiple code rates.

Therefore, in the actual implementation of the Viterbi decoder, it is necessary to comprehensively consider the three aspects of speed, power consumption and multi-code rate, and how to reduce the power consumption of the decoder as much as possible on the premise of improving the data throughput.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a high-speed low-power multi-code rate Viterbi decoder.

(2) Technical solution

In order to achieve the above object, the present invention provides a high-speed low-power multi-code rate Viterbi decoder, comprising a branch metric unit, an addition ratio selection unit, a path metric storage unit, a survival path storage unit, an output unit and a control unit, in:

The branch measurement unit is used to calculate the distance between the receiving symbol and the corresponding branch symbol on the branch of the grid graph, and output the calculation result to the addition and selection unit;

The addition and comparison selection unit is used to add the surviving path metrics at the previous moment of the two branches entering each state to the corresponding branch metrics, compare and select the smaller one as the updated surviving path metric, The corresponding path is a surviving path, and then the metric value of the surviving path is output to the path metric storage unit, and the surviving path is output to the surviving path storage unit;

The path metric storage unit is used to store the updated path metric value output by the addition and comparison selection unit;

The survival path storage unit is used to obtain decoding bits by processing the survival paths output by the addition and comparison selection unit, and output them to the output unit;

The output unit is used to complete the buffer output of the decoder;

The control unit is used to control the coordinated work and synchronization of the branch metric unit, the add compare selection unit, the path metric storage unit, the survivor path storage unit and the output unit in the decoder.

In the above solution, each module of the decoder has an input enabling signal, which allows the decoder to work at different code rates and different input data formats.

In the above solution, the branch measurement unit expresses the distance between the received symbol and the corresponding branch symbol on the trellis graph branch in absolute distance, and is realized by a subtractor.

In the above-mentioned scheme, described branch measurement unit adopts the method for absolute distance, for different code rates, in the patching unit, according to the coding rate, add a flag bit before the quantization number of corresponding patching holes to sign the code symbol here is The hole filling value, correspondingly, the calculation of the metric value of the corresponding bit is prohibited through this flag bit in the branch metric calculation unit, and at this time, the absolute distance at the corresponding code symbol is 0.

In the above scheme, the addition and selection unit is based on the butterfly operation unit, the number of the butterfly operation unit is related to the number of states of the decoder, and each butterfly operation unit includes 4 adders, 2 comparators and 2 selectors.

In the above solution, the surviving path storage unit includes an input selection unit, a register exchange unit and an output selection unit, wherein:

The input selection unit writes the surviving path obtained by the addition and comparison selection unit to the register exchange group of the register exchange unit in turn. This cycle write is to control the serial number of the written register exchange group through a counter, and the serial number is from 0 Increase to the maximum number of register groups, increase the counter by 1 when the surviving path is valid, and then store the corresponding surviving path into the register exchange group with the same value as the counter according to the value of the counter. When the counter reaches the maximum value, the register When exchanging the number of groups, the counter is set to 0, and then the previous process is repeated;

The register exchange unit is composed of a certain number of register exchange group units. The number of groups is generally 5 to 7 times the constraint length. The output of the register exchange group is fed back to the input selection unit, and the current register exchange is selected through the counter in the input selection unit. The input of the group is the output of the current register exchange group or the current survival path. When the value of the counter is equal to the serial number of the register exchange group, the survival path is input into the current register exchange group. If not, the current register exchange is performed. The output of the group is used as input to the current register exchange group;

The output selection unit reads the data in the register exchange group sequentially and cyclically to obtain the decoded bits.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. In the high-speed, low-power multi-code rate Viterbi decoder provided by the present invention, the parallel adding, comparing and selecting units improve the data throughput.

2. This high-speed, low-power multi-code rate Viterbi decoder provided by the present invention, a dynamic input and output selection unit, dynamically inputs the surviving path obtained by the processing of the addition ratio selection unit to the register exchange in the surviving path storage unit In the group, after a certain clock cycle of decoding processing, the output selection unit dynamically selects the data in the register exchange group as the decoding output, thereby reducing the power consumption of the decoder while obtaining the decoded bits.

3. The high-speed, low-power multi-code rate Viterbi decoder provided by the present invention adopts the design method of the enable signal in the module, which can flexibly process different input data stream forms under different code rates.

Description of drawings

Fig. 1 is (2,1,7) convolution code encoder;

Fig. 2 is the trellis diagram of the Viterbi decoding utilized in the present invention;

Fig. 3 is the structural representation of high-speed low-power multi-code rate Viterbi decoder provided by the present invention;

Fig. 4 is the structural diagram of the ratio selection unit of the present invention;

Fig. 5 is the butterfly unit figure in the ratio selection unit;

Fig. 6 is a structural diagram of the highest clearing circuit;

Fig. 7a is a schematic structural diagram of a survivor path storage unit in the present invention;

Fig. 7b is a schematic structural diagram of the register switching group unit of the present invention;

Fig. 8 is a bit error rate curve diagram of the decoder of the present invention under TGN channel A;

Fig. 9 is a bit error rate curve diagram of the decoder of the present invention under TGN channel B;

Fig. 10 is a reduction ratio diagram of register flipping under TGN channel A;

FIG. 11 is a graph showing the reduction ratio of register flipping under TGN channel B.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Take the convolutional codes used in WLANs as an example. In WLAN, the convolutional code of 1/2 code rate is defined by generating polynomials G1=133OCT and G1=171OCT, and the constraint length is 7, as shown in Figure 1, and the remaining code rates (2/3, 3/4, 4/5) is obtained by performing puncturing according to a corresponding puncturing mode on the basis of a code rate of 1/2.

As shown in Fig. 2, it is a trellis diagram of (2, 1, 7) convolutional code. The essence of the Viterbi decoding algorithm is to select a path with the shortest distance from the received symbol sequence on the trellis diagram as shown in Figure 2 as the result for decoding. It can be seen from the grid diagram in Figure 2 that if the two paths starting from state 0 will converge in a certain state, and these two paths will always be combined together in the future, since the contribution of the compound part branch to the path metric is The same, so the one with the larger metric in the front part of the two paths can be deleted at the confluence point. Therefore, at any moment, for all the paths entering each state, only one of the paths with the smallest partial path metric needs to be reserved, and this preserved path is called the survivor path. The number of states of the (2, 1, 7) convolutional code is 64. At any moment, the decoder needs to save 64 surviving paths, and at the same time save the path metric values corresponding to these 64 surviving paths. After time 6, each state has two paths to enter, and the partial path metric value of each path is equal to the sum of the surviving path metric value of the departure state at the previous moment and the corresponding branch metric, compare these two sums, and take The smaller one is the metric value of the surviving path, and the corresponding path is the surviving path, and the metric value of the surviving path and the surviving path are stored in a corresponding memory. In this way, a similar operation is performed at a later time to obtain the survivor path metric value and the survivor path, and the obtained survivor path is processed to obtain decoding.

Fig. 3 is a schematic structural diagram of a high-speed low-power multi-code rate Viterbi decoder provided by the present invention. The input data appears in the form of blocks, and the start and end of the data block are marked by the signals frame_start and frame_end respectively, and the data is marked by the signal din_valid The validity of the input decoder data in the block, the three flag signals defined on the decoder interface are generated by the control unit in the system outside the decoder according to the actual situation, and such signal flag definitions can be Let the decoder be flexible in the form of processing different input data streams.

Referring to Fig. 3 again, the high-speed low-power multi-code rate Viterbi decoder provided by the present invention includes a branch metric unit, an addition and comparison selection unit, a path metric storage unit, a survivor path storage unit, an output unit and a control unit. Among them, the branch measurement unit is used to calculate the distance between the received symbol and the corresponding branch symbol on the branch of the grid graph, and output the calculation result to the addition and selection unit; the branch measurement unit expresses the absolute distance between the received symbol and the grid graph branch The distance between the corresponding branch symbols on the upper, and through the subtractor to achieve. The addition and selection unit is used to add the metric value of the survival path at the previous moment of the two branches entering each state to the metric of the corresponding branch, compare and select the smaller one as the updated metric value of the surviving path, corresponding to The path is the survival path, and then the survival path metric value is output to the path metric storage unit, and the surviving path is output to the surviving path storage unit; the path metric storage unit is used to store the updated path metric value output by the addition and selection unit; the survival path The storage unit is used to process the surviving path output by the addition and selection unit to obtain decoded bits and output to the output unit; the output unit is used to complete the buffer output of the decoder; the control unit is used to control the branch in the decoder The coordination and synchronization of the metric unit, the addition and selection unit, the path metric storage unit, the surviving path storage unit and the output unit.

As shown in Figure 4, the addition and selection unit includes 32 parallel butterfly units and normalized anti-overflow processing units. (2, 1, 7) has a total of 64 states and requires 32 butterfly units. Each butterfly unit The structural diagram of the unit is shown in Figure 5, so that each butterfly operation unit needs 4 adders, 2 comparators and 2 selectors.

As shown in Figure 6, the input of the normalized anti-overflow processing unit comes from the highest bits of the 64 path metrics obtained by the 32 butterfly operation units, and when the highest bits of the 64 path metrics are judged to be 1 simultaneously, a The flag_clear signal, whether the signal is 1 or not, sets the highest position of the 64 path metric values to 0, thus completing the anti-overflow processing.

Fig. 7a is a schematic diagram of the structure of the survival path storage unit of the present invention. The survival path storage unit includes an input selection unit, a register exchange unit and an output selection unit. The input selection unit writes the survival path obtained by adding the ratio selection unit to the register exchange unit in turn. In the register exchange group, this kind of cyclic writing is controlled by a counter to control the serial number of the written register exchange group. The serial number is increased from 0 to the number of the largest register group, and the counter is increased by 1 when the survival path is valid, and then According to the value of the counter, the corresponding surviving path is stored in the register exchange group with the same value as the counter. When the counter reaches the maximum value, that is, the number of register exchange groups, the counter is set to 0, and then the previous process is repeated.

Fig. 7b is a schematic structural diagram of the register switching group unit of the present invention. The register exchange unit is composed of a certain number of register exchange group units shown in Figure 7(b). The number of groups is generally 5 to 7 times the constraint length. Here we choose the number of groups to be 40, and each register exchange group unit consists of 64 registers. Composed of 64 2-to-1 selectors, the output of the register exchange group is fed back to the input selection unit, and the counter in the input selection unit is used to select whether the input of the current register exchange group is the output of the current register exchange group or the current survivor Path, when the value of the counter is equal to the serial number of the register exchange group, then input the surviving path into the current register exchange group, if not, then use the output of the current register exchange group as input to the current register exchange group. The output selection unit reads the data in the register exchange group sequentially and cyclically to obtain the decoded bits. This method does not need to transfer data between register exchange groups, but only selects and transfers data within the register exchange group. After a certain number of selection exchanges, the registers in each group will converge to the decoded bits, which will reduce The state inversion caused by data transfer between register groups can achieve the purpose of reducing power consumption.

Fig. 8 is a bit error rate curve diagram of the decoder of the present invention under TGN channel A. This channel has only one path, and the bit error rate curve diagrams under different modulation modes and code rates are respectively obtained.

Fig. 9 is a bit error rate curve diagram of the decoder of the present invention under TGN channel B. This channel has nine paths, and respectively obtained bit error rate curve diagrams under different modulation modes and code rates.

FIG. 10 is a graph of the reduction ratio of register flips obtained under TGN channel A, where the depth of the register bank is 40. As the signal-to-noise ratio increases, the reduction ratio of register flipping also increases, and the power can be automatically adjusted according to the signal-to-noise ratio. Under BPSK and 1/2 code rate (MCS=1), from SNR 5 to 25, the ratio of register flip reduction has been above 0.6; under 64QAM and 2/3 code rate (MCS=7), register flip The reduction ratio also increases as the signal-to-noise ratio increases. It can be seen that this method can reduce register flipping, and the reduced power consumption increases as the signal-to-noise ratio increases.

FIG. 11 is a graph of the reduction ratio of register flips obtained under TGN channel B, where the register bank depth is 40. Similar conclusions can be drawn. The magnitude of its reduction is not as obvious as that of channel A due to the influence of multipath.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (5)

1. a kind of Viterbi decoder of high speed and low power consumption multi-code rate, it is characterized in that, comprise branch metric unit, add and compare selection unit, path metric storage unit, surviving path storage unit, output unit and control unit, wherein: The branch measurement unit is used to calculate the distance between the receiving symbol and the corresponding branch symbol on the branch of the grid graph, and output the calculation result to the addition and selection unit; The addition and comparison selection unit is used to add the surviving path metrics at the previous moment of the two branches entering each state to the corresponding branch metrics, compare and select the smaller one as the updated surviving path metric, The corresponding path is a surviving path, and then the metric value of the surviving path is output to the path metric storage unit, and the surviving path is output to the surviving path storage unit; The path metric storage unit is used to store the updated path metric value output by the addition and comparison selection unit; The survival path storage unit is used to obtain decoding bits by processing the survival paths output by the addition and comparison selection unit, and output them to the output unit; The output unit is used to complete the buffer output of the decoder; The control unit is used to control the coordination and synchronization of the branch metric unit, the addition and comparison selection unit, the path metric storage unit, the surviving path storage unit and the output unit in the decoder; Wherein, the surviving path storage unit includes an input selection unit, a register exchange unit and an output selection unit, wherein: The input selection unit writes the surviving path obtained by the addition and comparison selection unit to the register exchange group of the register exchange unit in turn. This cycle write is to control the serial number of the written register exchange group through a counter, and the serial number is from 0 Increase to the maximum number of register groups, increase the counter by 1 when the surviving path is valid, and then store the corresponding surviving path into the register exchange group with the same value as the counter according to the value of the counter. When the counter reaches the maximum value, the register When exchanging the number of groups, the counter is set to 0, and then the previous process is repeated; The register exchange unit is composed of a certain number of register exchange group units, the number of groups is 5 to 7 times the constraint length, the output of the register exchange group is fed back to the input selection unit, and the current register exchange group is selected by the counter in the input selection unit Is the input of the current register exchange group the output of the current surviving path? When the value of the counter is equal to the serial number of the register exchange group, the surviving path is input into the current register exchange group. If not, the current register exchange group is The output of is used as input to the current register exchange group; The output selection unit reads the data in the register exchange group sequentially and cyclically to obtain the decoded bits. 2. the Viterbi decoder of multiple code rates with low power consumption at a high speed according to claim 1, is characterized in that, each module of this decoder all has the signal that input enables, can allow decoder work like this At different bit rates and in different forms of input data. 3. the Viterbi decoder of the multi-code rate of low power consumption at a high speed according to claim 1, is characterized in that, described branch measurement unit represents with absolute distance the distance between receiving symbol and the corresponding branch symbol on trellis graph branch distance, and implemented by a subtractor. 4. the Viterbi decoder of the multi-code rate of high speed and low power consumption according to claim 3, is characterized in that, described branch measurement unit adopts the method for absolute distance, for different code rates, in the patching unit according to code The ratio is to add a flag bit in front of the quantized number of the corresponding patching hole to mark the code symbol here as the hole patching value, and correspondingly use this flag bit in the branch metric calculation unit to prohibit the calculation of the metric value of the corresponding bit. At this time, we get The absolute distance at the corresponding code symbol is zero. 5. the Viterbi decoder of the multi-code rate of high speed and low power consumption according to claim 1, it is characterized in that, described addition ratio selection unit is based on the butterfly operation unit, the number of the butterfly operation unit and the decoder Regarding the number of states, each butterfly unit includes 4 adders, 2 comparators and 2 selectors.

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