CN102062962B - Gate drive circuit - Google Patents

Abstract

A gate driving circuit of a liquid crystal display includes a plurality of driving units, each of which receives an input signal and generates an output signal or a carrier signal as an input signal of a next stage driving unit. The output signal of each driving unit is used for driving a column of pixels, the driving time is prolonged to two pulse widths, and the purpose of saving power is achieved by reducing the number of clock signals and clocks.

Description

Gate drive circuit

technical field

The invention relates to a gate drive circuit, and in particular to a gate drive circuit for a liquid crystal display.

Background technique

A liquid crystal display usually includes an array substrate, which is mainly composed of a pixel array divided by m data lines (D ₁ -D _m ) and n data lines (G ₁ -G _n ), wherein the m data lines are driven by multiple data For chip driving, the n gate lines are driven by multiple gate driving chips. In addition, the timing controller controls the gate driving chips and the data driving chips.

To meet the requirement of resolution, the number of pixels, gate lines, data lines, data driver chips, and gate driver chips in the pixel array must be increased, resulting in high manufacturing cost of the liquid crystal display. In order to reduce the cost, an integrated gate driver (integrated gate driver; IGD) replaces the gate drive chip. This integrated gate driver integrates the gate drive circuit on the array substrate, that is, it is integrated with the pixel array Manufactured on the array substrate, the component cost of the gate driver chip can be saved.

The design of an integrated gate driver usually includes multiple stages of drive units, each drive unit drives a column of pixel switching elements, and each drive unit, through circuit layout design, makes the input signal of the nth stage It is equal to the output signal of the n-1th stage, and the output signal of the nth stage is equal to the input signal of the n+1th stage. With the concept similar to the shift register (shift register), the number of output signals of the control gate lines is greatly reduced.

As the resolution requirements increase, a pre-charged integrated gate drive circuit is proposed. The difference between this pre-charged integrated gate drive circuit and the existing integrated gate drive circuit is that, The high-level pulse of the output signal of each level of driving unit maintains a longer period of time, so that the switching elements of the column of pixels driven by the level of driving unit have a longer turn-on time, so as to ensure sufficient charging time of the column of pixels.

An existing pre-charged integrated gate drive circuit is shown in FIGS. 1A and 1B , wherein FIG. 1A is a block diagram of a pre-charged integrated gate drive circuit, and FIG. 1B is a timing diagram of FIG. 1A . As shown in the figure, the pre-charged integrated gate driving circuit is divided into two groups, an odd group includes odd-numbered driving units, and an even-numbered group includes even-numbered driving units. Each group must use two clock signals, the odd group uses the clock signals CK1 and CKB1 , and the even group uses the clock signals CK2 and CKB2 to drive the circuit. The output signal of each level of driving unit passes through the gate lines (such as G1-G5) to drive the switching elements of a column of pixels. As shown in Figure 1B, the high-level pulse of the output signal of each level of driving unit has an overlap with the high-level pulse of the previous level of driving unit, that is, the previous level of driving unit has not returned to the low level At the same time, each level of driving unit starts to output a high-level pulse first, that is, the pre-charge operation is performed, and during the second half of the pulse (that is, the period that does not overlap with the pulse of the previous level of driving unit), the data driver Output (source driver output) write pixel voltage time.

Although the above-mentioned circuit achieves the purpose of a pre-charged driving circuit, its design requires the circuit to be divided into two groups, which is too complicated to design, and requires a total of four clock signals, which makes it difficult to change the design and consumes a lot of power. In addition, there is still room for improvement in the stability and reliability of the integrated gate driving circuit in the prior art.

Therefore, there is an urgent need to provide a new gate driving circuit to improve the above defects.

Contents of the invention

The purpose of the present invention is to provide a new gate drive circuit with good stability and reliability, simple circuit design and less substrate area, and the power consumption can be greatly reduced compared with the prior art.

According to the above purpose, an embodiment of the present invention provides a gate drive circuit, which includes a plurality of drive units connected in series, and each drive unit includes: a signal input terminal for receiving an input signal; a feedback signal input terminal for receiving a feedback signal; a carrier signal The output terminal outputs a carrier signal; the signal output terminal outputs an output signal to drive a column of pixels; the first switch has a first terminal and a control terminal coupled to the signal input terminal to receive the input signal, and a second terminal coupled to the first node; The second switch, its first end is coupled to the clock signal, the second end is coupled to the second node and the carrier signal output end to output the carrier signal, the control end is coupled to the first node; the third switch, its first end is coupled to the first node A node, the second terminal is coupled to the low voltage source, the control terminal is coupled to the feedback signal input terminal to receive the feedback signal; the fourth switch, the first terminal of which is coupled to the high voltage source, the second terminal is coupled to the signal output terminal, and the control terminal Coupled to the first node; the fifth switch, the first end of which is coupled to the second end of the fourth switch and the signal output end, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; and the sixth switch , the first end of which is coupled to the second node, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; wherein the carrier signal output end of each drive unit is coupled to the signal input end of the next drive unit 1. The feedback signal input terminal is coupled to the output signal terminals of the lower two-stage drive units.

The above-mentioned gate drive circuit, wherein the signal input terminal of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the input signal of the first-level drive unit, and the start The pulse width of the signal is the first width (W), the pulse width of the clock signal is also the first width (W), and the duty cycle is 1/2, and the clock signal lags behind the start signal with the The time difference of the first width (W).

The above-mentioned gate drive circuit, wherein the pulse width of the output signal of each drive unit is the second width (2W), and the second width is twice the first width (W), and the adjacent The pulses of the output signals of the two driving units partially overlap with each other.

In the aforementioned gate drive circuit, the width of the overlapping portion is the first width (W).

In the above-mentioned gate driving circuit, the output signal of the first-level driving unit and the pulse of the start signal partially overlap with each other, and the width of the overlapping part is the first width.

The above-mentioned gate driving circuit only includes two clock signals, which have a time difference of the first width (W) between them, and each driving unit receives one of the two clock signals as their respective The above clock signal, and two adjacent drive units receive different clock signals.

In the above gate driving circuit, the dimensions of the fourth switch and the fifth switch are tens to hundreds of times larger than the dimensions of the second switch and the sixth switch.

The above-mentioned gate drive circuit, wherein the carrier signal output by each drive unit lags behind the input signal received by the drive unit by a time difference of the first width (W), and the output signal of each drive unit has a pulse width of Twice the first width, and except for the first-level driving unit, the output signal of each level of driving unit lags behind the output signal of the previous driving unit by a time difference of the first width.

According to the above purpose, an embodiment of the present invention provides a gate drive circuit, which includes a plurality of drive units connected in series, and each drive unit includes: a signal input terminal for receiving an input signal; a feedback signal input terminal for receiving a feedback signal; a carrier signal The output terminal outputs the carrier signal; the signal output terminal outputs the output signal to drive a column of pixels; the first switch, the first terminal of which is coupled to the first clock signal, and the second terminal is coupled to the first node, the signal output terminal and the control terminal coupled to the signal input terminal; the second switch, whose first terminal is coupled to the second clock signal, the second terminal is coupled to the second node and the carrier signal output terminal, and the control terminal is coupled to the first node; the third switch, whose first The end is coupled to the first node, the second end is coupled to the low voltage source, the control end is coupled to the feedback signal input end; the fourth switch, the first end of which is coupled to the second node and the carrier signal output end, and the second end is coupled to the low The voltage source and the control terminal are coupled to the feedback signal input terminal; the carrier signal output terminal of each drive unit is coupled to the signal input terminal of the next-level drive unit, and the feedback signal input terminal is coupled to the output signal terminals of the next two drive units.

The above-mentioned gate drive circuit, wherein the signal input terminal of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the input signal of the first-level drive unit, and the start The pulse width of the signal is the first width (W), the duty cycles of the first clock signal and the second clock signal are both 1/2, and the pulse width is also the first width (W), the second The second clock signal lags behind the first clock signal by a time difference of the first width (W), and the first clock signal is synchronized with the start signal.

The above-mentioned gate driving circuit only includes the first clock signal and the second clock signal.

The above-mentioned gate drive circuit, wherein the pulse width of the output signal of each drive unit is the second width (2W), and the second width is twice the first width (W), and the adjacent The pulses of the output signals of the two drive units partially overlap with each other.

In the above-mentioned gate driving circuit, the width of the overlapping portion of the output signal of the first-level driving unit and the pulse of the start signal is the first width.

In the above gate drive circuit, the size of the first switch and the third switch is tens to hundreds of times larger than the size of the second switch and the fourth switch.

The above-mentioned gate drive circuit, wherein the carrier signal output by each drive unit lags behind the input signal received by the drive unit by a time difference of the first width (W), and the output signal of each drive unit has a pulse width of Twice the first width (W), and except for the first level of driving unit, the output signal of each level of driving unit lags behind the output signal of the previous driving unit by a time difference of the first width (W).

According to the above purpose, an embodiment of the present invention provides a gate drive circuit, which includes a plurality of drive units connected in series, and each drive unit includes: a signal input terminal for receiving an input signal; a feedback signal input terminal for receiving a feedback signal; a signal output terminal end, outputting an output signal to drive a row of pixels; the first switch, whose first end is coupled to the clock signal, the second end, which is coupled to the node and the signal output end, and the control end, which is coupled to the signal input end; the second switch, whose first The terminal is coupled to the node and the signal output terminal, the second terminal is coupled to the low voltage source, and the control terminal is coupled to the feedback signal input terminal; the signal output terminal of each drive unit is coupled to the signal input terminal of the next drive unit, and the feedback signal The input end is coupled to the output signal ends of the lower two-stage drive units.

The above-mentioned gate drive circuit, wherein the signal input terminal of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the input signal of the first-level drive unit, and the start signal The pulse width is the first width (W), the duty cycle of the clock signal is 1/2, the pulse width is also the first width (W), and the clock signal is synchronized with the start signal.

The above-mentioned gate driving circuit only includes two clock signals, which have a time difference of the first width (W) between them, and each driving unit receives one of the two clock signals as their respective The above clock signal, and two adjacent drive units receive different clock signals.

The above gate drive circuit, wherein the pulse width of the output signal of each drive unit is the second width (2W), the second width is twice the first width (W), and any two adjacent A part of the pulses of the output signal of the driving unit overlaps with each other, and a part of the pulses of the output signal of the first driving unit and the start signal overlaps with each other.

The above-mentioned gate drive circuit, wherein the output signal of each drive unit has a pulse width twice the first width (W), and is behind the output signal of the previous drive unit by one of the first width (W) Time difference.

According to the above purpose, an embodiment of the present invention provides a gate drive circuit, which includes a plurality of drive units connected in series, and each drive unit includes: a signal input terminal for receiving an input signal; a feedback signal input terminal for receiving a feedback signal; a signal output terminal end, outputting an output signal to drive a column of pixels; the first switch, whose first end and control end are coupled to the input signal end, and the second end coupled to the node; the second switch, whose first end is coupled to the clock signal, and the second end The end is coupled to the signal output end, the control end is coupled to the node; and the third switch, the first end of which is coupled to the node, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; wherein each drive unit The signal output end is coupled to the signal input end of the next-level drive unit, and the feedback signal input end is coupled to the output signal end of the next three-level drive unit.

The above-mentioned gate drive circuit, wherein the signal input terminal of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the input signal of the first-level drive unit, and the start signal The pulse width is the first width (W), the duty cycle of the clock signal is 2/3, the pulse width is twice the first width (W), and the start signal is synchronized with the clock signal.

In the above-mentioned gate driving circuit, the pulse width of the output signal of each driving unit is twice the first width (W), the pulses of the output signals of any two adjacent driving units partially overlap each other, and the first A width of a pulse overlapping part of the output signal of the primary driving unit and the start signal is the first width.

The above-mentioned gate driving circuit only includes two clock signals, which have a time difference of the first width (W) between them, and each driving unit receives one of the two clock signals as their respective The above clock signal, and two adjacent drive units receive different clock signals.

The above-mentioned gate drive circuit, wherein the output signal of each drive unit has a pulse width twice the first width (W), and is behind the output signal of the previous drive unit by one of the first width (W) Time difference.

In the above gate drive circuit, the pulse width of the signal at the node is three times of the first width.

According to the above purpose, an embodiment of the present invention provides a gate drive circuit, which includes a plurality of drive units connected in series, and each drive unit includes: a signal input terminal for receiving an input signal; a signal output terminal for outputting an output signal to drive a column pixel; the first switch, the first end of which is coupled to the signal input end, the second end is coupled to the node, and the control end is coupled to the first clock signal; the second switch, the first end of which is coupled to the second clock signal, and the second end The signal output terminal is coupled to the control terminal, and the control terminal is coupled to the node; wherein the signal output terminal of each drive unit is coupled to the signal input terminal of the next-level drive unit, wherein the first-level drive unit of the plurality of series-connected drive units The signal input end receives a start signal as the input signal of the first-stage drive unit, the pulse width of the start signal is a first width (W), and the duty cycle of the first clock signal is 1 /3, the pulse width is also the first width (W), the duty cycle of the second clock signal is 2/3, the pulse width is twice the first width (W), the start signal Synchronized with the first clock signal and the second clock signal.

In the aforementioned gate drive circuit, the pulses of the first clock signal and the second clock signal partially overlap with each other, and the width of the overlapping portion is the first width.

In the above-mentioned gate driving circuit, wherein the pulse width of the output signal of each driving unit is twice the first width (W), some of the pulses of the output signals of any two adjacent driving units overlap each other, and the The width of the overlapping portion of the output signal of the first-level driving unit and the pulse of the start signal is the first width.

In the above gate drive circuit, the pulse width of the signal at the node is three times of the first width.

The above gate drive circuit includes a first group and a second group of clock signals, wherein each group of clock signals includes three clock signals, the pulse width of the first group of clock signals is the first width, and the The pulse width of the second group of clock signals is twice the first width, and each drive unit only receives one of the first group of clock signals and one of the second group of clock signals, As the respective first and second clock signals, and two adjacent driving units receive different clock signals.

In the above gate drive circuit, the pulse width of the output signal of each driving unit is twice the first width (W), and except for the first level of driving unit, the output signal of each level of driving unit lags behind the previous one The output signal of the driving unit has a time difference of the first width (W).

Description of drawings

1A and 1B show a conventional pre-charged gate drive circuit and its timing diagram;

FIG. 2A shows a block diagram of a gate drive circuit 10 according to an embodiment of the present invention;

FIG. 2B shows a timing diagram of clock signals received by the gate drive circuit 10 of the embodiment of the present invention;

FIG. 3 shows a circuit diagram of a driving unit of the gate driving circuit 10 according to an embodiment of the present invention;

4A and 4B illustrate the driving method of the gate driving circuit 10 according to the embodiment of the present invention;

FIG. 5A shows a block diagram of a gate drive circuit 30 according to an embodiment of the present invention;

FIG. 5B shows a timing diagram of clock signals received by the gate drive circuit 30 of the embodiment of the present invention;

FIG. 6 shows a circuit diagram of a driving unit of the gate driving circuit 30 according to an embodiment of the present invention;

7A and 7B illustrate the driving method of the gate driving circuit 30 according to the embodiment of the present invention;

FIG. 8A shows a block diagram of a gate drive circuit 40 according to an embodiment of the present invention;

FIG. 8B shows a timing diagram of clock signals received by the gate drive circuit 40 of the embodiment of the present invention;

FIG. 9 shows a circuit diagram of two drive units of the gate drive circuit 40 according to an embodiment of the present invention;

FIG. 10A and FIG. 10B illustrate the driving method of the gate driving circuit 40 according to the embodiment of the present invention;

FIG. 11A shows a block diagram of a gate drive circuit 50 according to an embodiment of the present invention;

FIG. 11B shows a timing diagram of clock signals received by the gate drive circuit 50 of the embodiment of the present invention;

FIG. 12 shows a circuit diagram of a driving unit of the gate driving circuit 50 according to an embodiment of the present invention;

13A and 13B illustrate the driving method of the gate driving circuit 50 according to the embodiment of the present invention;

FIG. 14A shows a block diagram of a gate drive circuit 60 according to an embodiment of the present invention;

FIG. 14B shows a timing diagram of clock signals received by the gate drive circuit 60 of the embodiment of the present invention;

FIG. 15 shows a circuit diagram of a driving unit of the gate driving circuit 60 according to an embodiment of the present invention; and

16A and 16B illustrate the driving method of the gate driving circuit 60 according to the embodiment of the present invention.

[Description of main component symbols]

10 Gate drive circuit 11-15 Drive unit

20 Clock Generator 30 Gate Drive Circuit

40 Gate Drive Circuit 50 Gate Drive Circuit

60 Gate drive circuit G1-G5 Gate line

IP Signal Input Port OP Signal Output Port

RP Feedback signal input terminal CP Carrier signal output terminal

CKV CKB 1-CKB2 Clock signal

M ₁ -M ₆ switch CK1-CK6 clock signal

V _SS low voltage source V _dd high voltage source

X Node Z Node

Input Input Signal Output Output Signal

Carrier carrier signal W first width

Detailed ways

Various embodiments of the present invention will be described in detail below and illustrated with accompanying drawings. In addition to these detailed descriptions, the present invention can also be widely practiced in other embodiments, and any substitution, modification, and equivalent change of any of the described embodiments are included within the scope of the present invention, and defined by the appended claims. range prevails. In the description of the specification, many specific details are provided in order to enable readers to have a more complete understanding of the present invention; however, the present invention may still be practiced under the premise of omitting some or all of these specific details. Also, well-known steps or elements have not been described in detail in order to avoid unnecessarily limiting the invention.

FIG. 2A shows a block diagram of a gate driving circuit 10 according to an embodiment of the present invention. The gate drive circuit 10 includes a plurality of drive units 11 connected in series, such as the first drive unit S1, the second drive unit S2, the third drive unit S3, the fourth drive unit S4, etc. shown in the figure, each of which The driving unit 11 receives an input signal, a feedback signal, and a clock signal, wherein the clock signals CK1 and CK2 are provided by a clock generator 20 , and the clock generator 20 may or may not be included in the gate driving circuit 10 .

Each driving unit 11 includes a signal input terminal IP for receiving an input signal Input, a feedback signal input terminal RP for receiving a feedback signal, a signal output terminal OP for outputting an output signal, and a carrier signal output terminal CP for outputting a carrier signal Carrier.

The carrier signal output terminal CP of each drive unit 11 is coupled to the signal input terminal IP of the next-level drive unit, and the feedback signal input terminal RP is coupled to the output signal terminal OP of the next two levels of drive units; therefore, each level of drive unit 11 The input signal Input is the carrier signal Carrier output by the previous drive unit, and the feedback signal is the output signal Output of the next two drive units. However, since the first drive unit S1 is the first drive unit of these serially connected drive units, The difference with other drive units is that its signal input terminal IP receives, for example, a start signal (start pulse), as the input signal (Input) of the first drive unit S1, and the pulse width of the start signal is set to be first width W.

FIG. 2B shows a timing diagram of clock signals received by the gate drive circuit 10 of the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2 in total, and their duty cycles are 1/2. The pulse width is also the first width (W), and the two clock signals have a phase difference, for example, a time difference of the first width (W). In addition, as shown in FIG. 2A , in this embodiment, each driving unit receives one of the two clock signals as its own clock signal, and any two adjacent driving units receive different clock signals.

FIG. 3 shows a circuit diagram of a driving unit of the gate driving circuit 10 according to an embodiment of the present invention. In this embodiment, the second driving unit S2 is taken as an example for illustration, and it is assumed to be an nth level driving unit.

The nth level drive unit 11 has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, a carrier signal output terminal CP, and switches _M1 to _M6 , wherein the switches _M1 to _M6 can be thin film transistors (TFT ) or any semiconductor switching element, such as NMOS transistors, PMOS transistors, BJT transistors, etc. As mentioned above, the nth level drive unit 11 receives the input signal Input(n) through the signal input terminal IP, receives the feedback signal Output(n+2) through the feedback signal input terminal RP, and outputs the output signal Output(n+2) through the signal output terminal OP. n) To drive a column of pixels in the pixel array (for example, the nth column of pixels), and output the carrier signal Carrier (n) to the N+1th level driving unit through the carrier signal output terminal CP as the input signal of the n+1th level driving unit Input(n+1). Each switch has a control terminal, a first terminal and a second terminal. A first terminal and a control terminal of the switch M ₁ are coupled to the signal input terminal IP for receiving the input signal Input(n), and a second terminal is coupled to the node X. A first terminal of the switch _M2 is coupled to the clock signal CK2, a second terminal is coupled to the node Z and a carrier signal output terminal CP to output the carrier signal Carrier(n), and a control terminal is coupled to the node X. The first terminal of the switch _M3 is coupled to the node X, the second terminal is coupled to the low voltage source V _SS (with a low potential, for example -10V), and the control terminal is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2 ). A first terminal of the switch _M4 is coupled to a high voltage source Vdd (with a high potential, such as 15V), a second terminal is coupled to the signal output terminal OP and the first terminal of the switch M5 , and a control terminal is coupled to the node X. The first terminal of the switch _M5 is coupled to the second terminal of the switch _M4 and the signal output terminal OP, the second terminal is coupled to the low voltage source V _SS , and the control terminal is coupled to the feedback signal input terminal RP. A first terminal of the switch M ₆ is coupled to the node Z, a second terminal is coupled to the low voltage source V _SS , and a control terminal is coupled to the feedback signal input terminal RP.

The size of the above-mentioned switches _M4 and _M5 is larger than the size of the switches _M2 and _M6 . For example, preferably, the size difference between the two can be dozens of times or even a hundred times, because the switches _M4 and _M5 are coupled to The signal output terminal OP is used to drive the switching elements of a column of pixels, and its capacitive load is relatively large, which requires a relatively large switching element to drive, and the switches _M2 and _M6 are coupled to the carrier signal output terminal CP to output the carrier signal as the next The input signal of the level drive unit does not require large-sized switching elements.

4A and 4B show the driving method of the gate driving circuit 10 according to the embodiment of the present invention, wherein FIG. 4A shows the driving unit of the gate driving circuit 10 according to FIG. The input signal Input(n), the clock signal CK2, the feedback signal Output(n+2), the potential of the node X, the carrier signal Carrier(n), the output signal Output(n), the output signal Output( n+1), and FIG. 4B is the operating state of switches M ₁ to M ₆ relative to FIG. 4A . In addition, in the following description, the high level can be, for example, 15 volts; the low level can be, for example, -10 volts, but this is not intended to limit the present invention.

During T1, the input signal Input(n) received by the signal input terminal IP is at a high level, and the feedback signal Output(n+2) is at a low level, so the switch M ₁ is turned on, and the switches M ₃ , M ₅ , M ₆ off. The input signal Input(n) is coupled to the node X and charges the potential of the node X to a high level. The high level potential of node X turns on switch _M2 so that the low level potential of clock signal CK2 is coupled to node Z to output a low level carrier signal Carrier(n). In addition, the high level potential of node X also The switch _M4 is turned on so that the high-level potential of the high-voltage source Vdd is coupled to the signal output terminal OP to output a high-level output signal Output(n).

During T2, the input signal Input(n) and the feedback signal Output(n+2) are at low level, so the switches M ₁ , M ₃ , M ₅ , and M ₆ are turned off. The potential of the node X remains at a high level because there is no discharge path, so that the switches M ₂ and M ₄ are turned on. At this time, the clock signal CK2 is at a high level, and the high level potential of the clock signal CK2 is coupled to the node Z through the switch _M2 to output a high level carrier signal Carrier(n). In addition, the high level of the high voltage source Vdd The bit potential is coupled to the signal output terminal OP via the switch _M4 to output a high-level output signal Output(n).

During T3, the input signal Input is at a low level, and the switch _M1 is turned off. The feedback signal Output(n+2) is at a high level, and the switches M ₃ , M ₅ , and M ₆ are turned on, so that the potential of the node X is discharged to a low level through the switch M ₃ , and the potential of the node Z is discharged through the switch M ₆ Discharged to a low level, the potential of the signal output terminal OP is discharged to a low level through the switch _M5 , so the carrier signal output terminal CP outputs a low level carrier signal Carrier(n), and the signal output terminal OP outputs a low level output signal Output(n).

During T4, the input signal Input is at a low level, the switch M ₁ is closed, and the potential of the node X is maintained at a low level, so that the switches M ₂ and M ₄ are closed, and the potentials of the node Z and the signal output terminal OP are not conducted due to the charging path. generally maintained at a low level. On the other hand, the feedback signal Output(n+2) is at a high level, and the switches M ₃ , M ₅ , and M ₆ are turned on, so that the potentials of node X, node Z, and the signal output terminal OP are kept at a low level, so the carrier The signal output terminal CP outputs a low-level carrier signal Carrier(n), and the signal output terminal OP outputs a low-level output signal output(n).

The output signals Output(n+1) and Output(n+2) are the output signals of the next level and the next two levels of driving units, and their timing diagrams can be deduced according to the above description. According to the gate driving circuit and driving method described in the embodiment of FIG. 2A to FIG. 4B of the present invention, if the pulse width W of the start signal is used as a reference, the carrier signal Carrier output by each level of driving unit will lag behind the received input signal Input a time difference of the first width (W); the output signal Output of each level of drive unit, its pulse width is twice the pulse width W of the start signal, that is, the pulse width of the output signal Output is 2W, and Except for the first level of driving unit, the output signal of each level of driving unit lags behind the output signal of the previous level of driving unit by a time difference of the first width (W), that is, the output signals of adjacent two levels of driving units will partially overlap each other , and the overlapping period is the first width (W), so the turn-on time of the switching elements driving the pixels in this column can be extended, achieving the effect of pre-charging. In addition, it can also be seen from FIG. 4A that the output signal of the nth level driving unit will partially overlap with its input signal Input, and the overlapping width is also the first width (W). In addition, the input signal received by each level of drive unit is the carrier signal output by the previous level of drive unit, not the output signal, so the cumulative resistance and capacitance effect of the output signal of each level of drive unit will not be coupled to the next level of drive unit . In addition, each level of drive unit only needs one clock signal, in other words, the entire gate drive circuit only needs two clock signals and does not need to be divided into two groups. The advantage of being easy. In addition, when the first terminal or the second terminal of the switching element in the prior art is coupled to the clock signal, the circuit stability may be affected due to the coupling effect (coupling effect) between the parasitic capacitance of the switch and the control terminal of the switch. In the embodiment of the present invention, since the size of the switch _M2 can be tens or even hundreds of times smaller than the size of the switch _M4 , its coupling effect can be almost ignored. In addition, in the embodiment of the present invention, there is no DC power supply (for example, high voltage source Vdd) or clock signal coupled to the control terminal of any switch element, so after long-term use, the threshold voltage (threshold voltage) of each switch element will not change. Offset, reliability is better.

FIG. 5A shows a block diagram of a gate driving circuit 30 according to an embodiment of the present invention. The gate drive circuit 30 includes a plurality of drive units 12 connected in series, such as the first drive unit S1 to the fourth drive unit S4, etc., wherein each drive unit 12 receives an input signal, a feedback signal, and two clock signals, wherein the clock The signals CK1 and CK2 are provided by the clock generator 20 , and the clock generator 20 may or may not be included in the gate driving circuit 30 .

Each driving unit 12 includes a signal input terminal IP for receiving an input signal Input, a feedback signal input terminal RP for receiving a feedback signal, a signal output terminal OP for outputting an output signal Output, and a carrier signal output terminal CP for outputting a carrier signal Carrier.

The feedback signal input terminal RP of each level of driving unit 12 is coupled to the signal output terminal OP of the rear two-level driving unit, and the carrier signal output terminal CP is coupled to the signal input terminal IP of the next level of driving unit; therefore, each level of driving unit 12 The received input signal Input is the carrier signal Carrier output by the previous drive unit, and the received feedback signal is the output signal Output of the last two drive units. However, since the first drive unit S1 is the output signal of these series drive units The signal input terminal IP of the first-level driving unit receives the input signal received by the gate driving circuit 30 , for example, a start signal, and the pulse width of the start signal is the first width W.

FIG. 5B shows a timing diagram of clock signals received by the gate drive circuit 30 of the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2 in total, and their pulse widths are also equal to the first width (W), The duty cycle is 1/2, and the clock signals have a phase difference, for example, a time difference of the first width (W). In addition, the pulse waveforms of these two clock signals do not overlap with each other, and have the same period as each other. In addition, as shown in FIG. 5A , in this embodiment, each driving unit will receive the two clock signals (CK1 and CK2) to drive the unit circuit.

FIG. 6 shows a circuit diagram of a driving unit of the gate driving circuit 30 according to an embodiment of the present invention. In this embodiment, the second driving unit S2 is taken as an example for illustration, and it is assumed to be an nth level driving unit.

The nth level drive unit 12 has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, a carrier signal output terminal CP, switches _M1 to _M4 , wherein the switches _M1 to _M4 can be thin film transistors or any Semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors and the like. As mentioned above, the nth level drive unit 12 receives the input signal Input(n) through the signal input terminal IP, receives the feedback signal Output(n+2) through the feedback signal input terminal RP, and outputs an output signal Output through the signal output terminal OP. (n) To drive the nth row of pixels in the pixel array, output a carrier signal Carrier(n) to the n+1th driver unit through the carrier signal output terminal CP as the input signal Input(n) of the n+1th driver unit +1).

Each switch has a control terminal, a first terminal and a second terminal. The first terminal of the switch _M1 is coupled to the clock signal CK1, the second terminal is coupled to the node X and the signal output terminal OP to output the output signal Output(n), and the control terminal is coupled to the signal input terminal IP to receive the input signal Input(n ). A first terminal of the switch _M2 is coupled to the clock signal CK2, a second terminal is coupled to the node Z and a carrier signal output terminal CP to output the carrier signal Carrier(n), and a control terminal is coupled to the node X. The first terminal of the switch _M3 is coupled to the node X, the second terminal is coupled to the low voltage source _VSS (with a low potential, for example -30V), and the control terminal is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2 ). The first terminal of the switch _M4 is coupled to the node Z and the carrier signal output terminal CP, the second terminal is coupled to the low voltage source Vss, and the control terminal is coupled to the feedback signal input terminal RP. The size of the above-mentioned switches _M1 and _M3 may be larger than the size of the switches _M2 and _M4 . For example, preferably, the size difference between the two may be dozens of times or even a hundred times.

7A and 7B show the driving method of the gate driving circuit 30 according to the embodiment of the present invention, wherein FIG. 7A shows the driving unit of the gate driving circuit 30 according to FIG. The input signal Input(n), clock signal CK1, clock signal CK2, potential of node X, potential of node Z, carrier signal Carrier(n), output signal Output(n), output signal Output( n+1), the timing diagram of the feedback signal Output(n+2), and FIG. 7B shows the operating states of the switches M ₁ to M ₄ relative to FIG. 7A .

During T1, the input signal Input(n) is at a high level, and the feedback signal Output(n+2) is at a low level, so the switch M ₁ is turned on, and the switches M ₃ and M ₄ are turned off. The high level of the clock signal CK1 is coupled to the node X through the switch _M1 and the potential of the node X is charged to a high level to output a high level output signal Output(n), and the high level of the node X is turned on The switch _M2 enables the low level potential of the clock signal CK2 to be coupled to the node Z to output a low level carrier signal Carrier(n).

During T2, the input signal Input and the feedback signal Output(n+2) are at low level, so the switches M ₁ , M ₃ , and M ₄ are turned off. The potential of the node X remains at a high level because there is no discharge path, and the output signal Output(n) of a high level is output through the signal output terminal OP, and the high level of the node X turns on the switch M ₂ . At this time, the clock signal CK2 is at a high level, and the high level potential of the clock signal CK2 is coupled to the node Z through the switch _M2 to output a high level carrier signal Carrier(n).

During T3, the input signal Input is at a low level, and the switch _M1 is turned off. The feedback signal Output(n+2) is at a high level, and the switches M ₃ and M ₄ are turned on, so that the potential of node X is discharged to a low level through the switch M ₃ , and the potential of node Z is discharged to a low level through the switch M ₄ Therefore, the carrier signal output terminal CP outputs a low-level carrier signal Carrier(n), and the signal output terminal OP outputs a low-level output signal Output(n).

During T4, the input signal Input is at a low level, the switch _M1 is closed, and the potential of the node X is maintained at a low level, so that the switch _M2 is closed, and the potential of the node Z is maintained at a low level due to the non-conduction of the charging path. On the other hand, the feedback signal Output(n+2) is at a high level, and the switches M ₃ and M ₄ are turned on, so that the potentials of nodes X and Z are guaranteed to be at a low level, so the carrier signal output terminal CP outputs a low level The carrier signal Carrier(n), the signal output terminal OP outputs a low-level output signal output(n).

The output signals Output(n+1) and Output(n+2) are respectively the output signals of the driving units of the next stage and the next two stages, and their timing diagrams can be deduced according to the above description. According to the gate driving circuit and driving method described in the embodiment of FIG. 5A to FIG. 7B of the present invention, if the pulse width of the start signal is a first width W as a reference, the carrier signal Carrier output by each level of driving unit lags behind The received input signal Input has a time difference of the first width (W); the output signal Output of each level of driving unit has a pulse width that is twice the first width, that is, 2W, and except for the first level of driving unit, each The output signal of the first-level drive unit lags behind the output signal of the previous-level drive unit by a time difference of the first width (W), that is, the pulses of the output signals of two adjacent drive units will partially overlap, and the overlap width is With the first width (W), the turn-on time of the switching elements driving the pixels in this row can be extended, achieving the effect of pre-charging. In addition, it can also be seen from FIG. 7A that the output signal Output(n) of the nth level driving unit will partially overlap with the input signal Input(n), and the overlapping width is also the first width (W). In addition, the first clock signal CK1 is synchronous with the input signal or the start signal, that is, the pulses of the input signal and the pulses of the first clock signal CK1 will be generated simultaneously.

In addition, the advantages of the embodiment shown in Fig. 5A to Fig. 7B are the same as those in the embodiment shown in Fig. 2A to Fig. 4B , the difference is that each level of driving unit of the latter needs two clock signals, while the former only needs one clock signal, but each of the latter Compared with the former, the level drive unit has two less switching elements and requires less layout area, so it is easier to design.

FIG. 8A shows a block diagram of a gate driving circuit 40 according to an embodiment of the present invention. The gate drive circuit 40 includes a plurality of drive units 13 connected in series, such as the first drive unit S1 to the fourth drive unit S4, etc., wherein each drive unit 13 receives an input signal, a feedback signal, and a clock signal, wherein the clock signal CK1 and CK2 are provided by the clock generator 20 , and the clock generator 20 may or may not be included in the gate driving circuit 40 .

Each driving unit 13 includes a signal input terminal IP for receiving an input signal Input, a feedback signal input terminal RP for receiving a feedback signal, and a signal output terminal OP for outputting an output signal Output. The signal output terminal OP of each level of drive unit 13 is coupled to the signal input terminal IP of the next level of drive unit, and the feedback signal input terminal RP is coupled to the signal output terminal OP of the next two levels of drive units; therefore, each level of drive unit 13 The received input signal Input is the output signal Output output by the previous drive unit, and the received feedback signal is the output signal Output of the latter two drive units. However, since the first drive unit S1 is the first drive unit of these serially connected drive units The signal input terminal IP of the primary driving unit receives the input signal received by the gate driving circuit 40 , for example, a start signal, and the pulse width of the start signal is set as the first width W.

FIG. 8B shows a timing diagram of clock signals received by the gate drive circuit 40 of the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2 in total, and their pulse widths are also equal to the first width (W), The duty cycle is 1/2, and there is a phase difference between the two clock signals, for example, a time difference of the first width (W). In addition, the pulse waveforms of these two clock signals do not overlap with each other. In addition, as shown in FIG. 8A , in this embodiment, each driving unit receives one of the two clock signals as its own clock signal, and any two adjacent driving units receive different clock signals. 9 shows a circuit diagram of two driving units of the gate driving circuit 40 of the embodiment of the present invention. In this embodiment, the first driving unit S1 and the second driving unit S2 are used as examples for illustration, and it is assumed that they are the n-th Level 1 drive unit and level n drive unit.

The n-1th level drive unit and the nth level drive unit each have a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, and two switches—the former has switches _M1 and _M2 and the latter has switch _M3 and M ₄ , wherein the switches M ₁ to M ₄ can be thin film transistors or any semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors and so on.

The drive unit of level n-1 receives the input signal Input(n-1) through the signal input terminal IP, receives the feedback signal Output(n+1) through the feedback signal input terminal RP, and outputs the output signal Output(n-1) through the signal output terminal OP. 1) to drive the n-1th column of pixels in the pixel array, and output the output signal Output(n-1) to the signal input terminal IP of the n-th level drive unit via the signal output terminal OP as its input signal Input(n) . The nth level driving unit then receives the feedback signal Output(n+2) through the feedback signal input terminal RP, and outputs the output signal Output(n) through the signal output terminal OP to drive the nth column of pixels in the pixel array.

Each switch has a control terminal, a first terminal and a second terminal. For the n-1th level drive unit, the first end of the switch _M1 is coupled to the clock signal CK1, the second end is coupled to the node X and the signal output end OP to output the output signal Output(n-1), and the control end is coupled to Connect to the signal input terminal IP to receive the input signal Input(n-1). The first terminal of the switch _M2 is coupled to the node X and the signal output terminal OP, the second terminal is coupled to the low voltage source V _SS (with a low potential, such as -10V), and the control terminal is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+1).

For the nth level drive unit, the first terminal of the switch _M3 is coupled to the clock signal CK2, the second terminal is coupled to the node Y and the signal output terminal OP to output the output signal Output(n), and the control terminal is coupled to the signal input Terminal IP to receive the input signal Input(n). A first terminal of the switch M ₄ is coupled to the node Y and the signal output terminal OP, a second terminal is coupled to the low voltage source V _SS , and a control terminal is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2).

10A and FIG. 10B show the driving method of the gate driving circuit 40 according to the embodiment of the present invention, wherein FIG. 10A shows that the gate driving circuit 40 according to the input signals Input(n-1), Clock signal CK1, clock signal CK2, potential of node X, potential of node Y, output signal Output(n-1), output signal Output(n), feedback signal Output(n+1), feedback signal Output(n+2 ), and FIG. 10B is the operating state of switches _M1 to _M4 relative to FIG. 10A.

During T1, the input signal Input(n-1) is at a high level, and the feedback signals Output(n+1) and Output(n+2) are at a low level, so the switch M ₁ is turned on, and the switches M ₂ and M ₄ closure. The high level of the clock signal CK1 is coupled to the node X through the switch _M1 and the potential of the node X is charged to a high level to output a high level output signal Output(n-1), and the high level potential of the node X The switch _M3 is turned on so that the low level potential of the clock signal CK2 is coupled to the node Y to output a low level output signal Output(n).

During T2, the input signal Input(n-1) and the feedback signals Output(n+1) and Output(n+2) are at a low level, so the switches M ₁ , M ₂ , and M ₄ are turned off. The potential of the node X remains at a high level because there is no discharge path, and the output signal Output(n-1) of a high level is output through the signal output terminal OP, and the high level of the node X turns on the switch _M3 . At this time, the clock signal CK2 is at a high level, and the high level potential of the clock signal CK2 is coupled to the node Y through the switch _M3 to output a high level output signal Output(n).

During T3, the input signal Input(n−1) is at a low level, and the switch _M1 is turned off. The feedback signal Output(n+1) is at a high level, and the switch _M2 is turned on, so that the potential of the node X is discharged to a low level through the switch _M2 , so the signal output terminal OP outputs a low level output signal Output(n- 1). For the n-th level drive unit, the node X is at a low level, the switch _M3 is closed, and the feedback signal Output(n+2) is at a low level, so the potential of the node Y is maintained at a high level because there is no discharge path, A high-level output signal Output(n) is output through the signal output terminal OP.

During T4, the input signal Input(n-1) is at a low level, the switch _M1 is closed, the potential of node X is maintained at a low level, the output signal Output(n-1) is maintained at a low level, and the potential of node X is maintained at a low level. The level potential makes the switch _M3 close. The feedback signal Output(n+2) is at a high level, so that the switch _M4 is turned on, the potential of the node Y is discharged to a low level, and a low level output signal Output(n) is output through the signal output terminal OP.

According to the gate driving circuit and driving method described in the embodiment of FIG. 8A to FIG. 10B of the present invention, if the pulse width of the start signal is used as the first width W as a reference, the output signal Output of each level of driving unit has a pulse The width is 2W, and the output signal of each level of driving unit lags behind the output signal of the previous level of driving unit by a time difference of the first width (W), that is, the overlapping width of the pulses of two adjacent driving units will be the first width (W), so the turn-on time of the switching elements driving the pixels in this column can be extended, achieving the effect of pre-charging. In addition, it can also be seen from FIG. 10A that the output signal Output(n-1) of the n-1th level drive unit will partially overlap with its input signal Input(n-1), and the overlapping width is also the first width (W ).

In addition, the advantages of the embodiments shown in FIGS. 8A to 10B are the same as those in the embodiments shown in FIGS. 2A to 4B . easy.

In addition, in each of the above embodiments, the clock generator only needs to generate a set of clock signals (wherein each set of clock signals includes two corresponding clock signals CK1 and CK2) to drive all the driving units in the gate driver, instead of It is necessary to divide all the driving units in the gate driver into an odd group of driving units and an even group of driving units as in the prior art (such as shown in FIG. 1A ), and two sets of clock signals (a total of four clock signals) must be provided to drive Odd groups of drive units and even groups of drive units. In addition, in the above-mentioned embodiment, the pulse width of the output signal of each driving unit is twice the pulse width of the start signal pulse or the clock signal, while in the prior art, the pulse width of the output signal of each driving unit is equal to the pulse width of the clock signal. The pulse width of the signals is the same. FIG. 11A shows a block diagram of a gate driving circuit 50 according to an embodiment of the present invention. The gate drive circuit 50 includes a plurality of drive units 14 connected in series, such as the first drive unit S1 to the fourth drive unit S4, etc., wherein each drive unit 14 receives an input signal, a feedback signal, and a clock signal, wherein the clock signal CK1 and CK2 are provided by a clock generator 20 , and the clock generator 20 may or may not be included in the gate driving circuit 50 .

Each driving unit 14 includes a signal input terminal IP for receiving an input signal Input, a feedback signal input terminal RP for receiving a feedback signal, and a signal output terminal OP for outputting an output signal Output. The signal output terminal OP of each level of driving unit 14 is coupled to the signal input terminal IP of the next level of driving unit, and the feedback signal input terminal RP is coupled to the signal output terminal OP of the third level of driving unit; therefore, each level of driving unit 14 The received input signal Input is the output signal Output output by the previous drive unit, and the received feedback signal is the output signal of the last three drive units. However, since the first drive unit 14 is the first of these series-connected drive units In the stage driving unit, the signal input terminal IP thereof receives the input signal received by the gate driving circuit 50 , for example, a start signal, and the pulse width of the start signal is set as the first width W.

11B shows a timing diagram of clock signals received by the gate drive circuit 50 of the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2 in total, and the duty cycle of each clock signal is 2/3, the pulse width is twice the first width (W), that is, 2W, and the clock signal CK2 lags behind the clock signal CK1 by a time difference of the first width (W), that is, the clock signal CK1 and CK2 partially overlap , and the overlapping width is the first width (W). In addition, as shown in Figure 11A, in this embodiment, only two clock signals are required, and each drive unit will receive one of the two clock signals as its own clock signal, and any two adjacent drive units receive different clock signals.

FIG. 12 shows a circuit diagram of a driving unit of the gate driving circuit 50 according to an embodiment of the present invention. In this embodiment, the second driving unit S2 is taken as an example for illustration, and it is assumed to be an nth level driving unit.

The nth-level drive unit has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, and switches _M1 to _M3 , wherein the switches _M1 to _M3 can be thin film transistors or any semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors, etc.

As mentioned above, the drive unit of level n receives the input signal Input(n) through the signal input terminal IP, receives the feedback signal Output(n+3) through the feedback signal input terminal RP, and outputs the output signal Output(n) through the signal output terminal OP. ) to drive a column of pixels in the pixel array, for example, the nth column of pixels.

Each switch has a control terminal, a first terminal and a second terminal. A first terminal and a control terminal of the switch M ₁ are coupled to the input signal terminal IP for receiving the input signal Input(n), and a second terminal is coupled to the node X. A first terminal of the switch M ₂ is coupled to the clock signal CK1 , a second terminal is coupled to the signal output terminal OP to output the output signal Output(n), and a control terminal is coupled to the node X. The first terminal of the switch _M3 is coupled to the node X, the second terminal is coupled to the low voltage source _VSS (with a low potential, for example -10V), and the control terminal is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+3 ).

13A and 13B show the driving method of the gate drive circuit 50 according to the embodiment of the present invention, wherein FIG. 13A shows that the gate drive circuit 50 according to the input signal Input(n) and the clock signal CK1 in a drive unit of FIG. 12 , the potential of node X, the timing diagram of the output signal Output(n), and the feedback signal Output(n+3), and FIG. 13B is the operating state of the switches _M1 to _M2 relative to FIG. 13A.

During T1, the input signal Input(n) is at a high level and the feedback signal Output(n+3) is at a low level, so the switch _M1 is turned on and the switch _M3 is turned off. The high level of the input signal Input(n) is coupled to the node X through the switch _M1 and the potential of the node X is charged to the high level, and the high level potential of the node X turns on the switch _M2 so that the high level of the clock signal CK1 The bit potential is coupled to the signal output terminal OP to output a high-level output signal Output(n).

During T2, the input signal Input(n) and the feedback signal Output(n+3) are at a low level, so the switches M ₁ and M ₃ are turned off. The potential of the node X remains at a high level because there is no discharge path, so that the switch _M2 is turned on, and the high level of the clock signal _CK1 is coupled to the signal output terminal OP via the switch M2 to output a high level output signal Output( n).

During T3, the input signal Input(n) and the feedback signal Output(n+3) are at a low level, so the switches M ₁ and M ₃ are turned off. The potential of node X remains at a high level because there is no discharge path, so that the switch _M2 is turned on. At this time, the clock signal CK1 is at a low level, and the low level of the clock signal CK1 is coupled to the signal output terminal OP through the switch _M2 . And output a low-level output signal Output(n).

During T4 and T5, the input signal Input(n) is at a low level, so the switch _M1 is turned off. The feedback signal Output(n+3) is at a high level, and the potential of the node X is discharged to a low level through the switch _M3 , so the switch _M2 is closed, and the output signal Output(n) remains at a low level.

During T6, T7, and T8, the input signal Input(n) is at a low level, so the switch _M1 is closed, so the potential of the node X is maintained at a low level, so the switch _M2 is closed, and the potential of the output signal terminal OP remains The low level output signal Output(n) is output at the low level.

The output signals Output(n+1), output(n+2), and output(n+3) are the output signals of the next-level, lower-two-level, and lower-three-level drive units, and their timing diagrams can be based on the above description. analogy. According to the gate driving circuit and driving method described in the embodiment of FIG. 11A to FIG. 13B of the present invention, if the pulse width of the start signal is used as the first width W as a reference, the output signal of each level of driving unit has a pulse width of Twice the first width (W), that is, 2W, and the output signal of each level of driving unit lags behind the output signal of the previous level of driving unit by a time difference of the first width (W), so the row of pixels is driven The turn-on time of the switching element can be extended to achieve the effect of pre-charging. In addition, it can also be seen from FIG. 13A that the output signal Output(n) of the nth level drive unit partially overlaps with its input signal Input(n), and the overlapping width is also the first width (W); and the first clock signal CK1 Synchronous with the input signal or the start signal, that is, the pulse of the input signal and the pulse of the clock signal CK1 will be generated simultaneously. In addition, the signal pulse at node X is three times the first width (W).

In addition, the advantages of the embodiment shown in Fig. 11A to Fig. 13B are substantially the same as those of the previous embodiment, the difference is that the duty cycle of the clock signal used in this embodiment is 2/3, while that of the previous embodiment is 1/2, but because each The first-level drive unit only needs one clock signal, so it still has the effect of saving power. In addition, in this embodiment, only three switching elements are required for each stage of the driving unit, the required layout area is small, and the design is easy.

FIG. 14A shows a block diagram of a gate driving circuit 60 according to an embodiment of the present invention. The gate drive circuit 60 includes a plurality of drive units 15 connected in series, such as the first drive unit S1 to the fourth drive unit S4, etc., wherein each drive unit 15 receives an input signal and two clock signals, wherein the clock signals CK1 to CK6 is provided by a clock generator 20 , and the clock generator 20 may or may not be included in the gate driving circuit 60 .

Each driving unit 15 includes a signal input terminal IP for receiving an input signal Input, and a signal output terminal OP for outputting an output signal Output. The signal output terminal OP of each level of driving unit 15 is coupled to the signal input terminal IP of the next level of driving unit; therefore, the input signal Input received by each level of driving unit 15 is the output signal Output output by the previous level of driving unit, However, since the first drive unit 15 is the first-level drive unit of these series-connected drive units, its signal input terminal IP receives the input signal received by the gate drive circuit 60, such as a start signal, and sets the start signal The pulse width of is the first width W.

14B shows a timing diagram of clock signals received by the gate drive circuit 60 of the embodiment of the present invention. The clock generator 20 generates six clock signals CK1 to CK6 in total, and the duty cycle of the clock signals CK1 to CK3 is 1/3. , the pulse width is also the first width (W), and there is a phase difference between them, such as a time difference of the first width (W), and they do not overlap with each other; the duty cycle of the clock signals CK4 to CK6 is 2/3 , the pulse width is twice the first width (W), that is, 2W, and there is a phase difference between them, for example, a time difference of the first width (W), in other words, in CK4 to CK6, two adjacent clock signals The pulses of are partially overlapped with each other, and the overlapping width is the first width (W). That is, this embodiment includes two groups of clock signals, the first group and the second group of clock signals, wherein the first group of clock signals includes three clock signals CK1 to CK3, and the pulse width of the first group of clock signals is the first group of clock signals The second group of clock signals includes three clock signals CK4 to CK6, and the pulse width of the second group of clock signals is twice the first width. In addition, as shown in FIG. 14A, each driving unit only receives one of the first group of clock signals and one of the second group of clock signals to drive the unit circuit, and two adjacent driving units receive different clock signal.

FIG. 15 shows a circuit diagram of a driving unit of the gate driving circuit 60 according to an embodiment of the present invention. In this embodiment, the second driving unit S2 is taken as an example for illustration, and it is assumed to be an nth level driving unit.

The nth-level drive unit has a signal input terminal IP, a signal output terminal OP, and switches _M1 to _M2 , wherein the switches _M1 to _M2 can be thin film transistors or any semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors, etc. wait.

As mentioned above, the nth level driving unit receives the input signal Input(n) through the signal input terminal IP, and outputs the output signal Output(n) through the signal output terminal OP to drive a column of pixels in the pixel array, for example, the nth column of pixels.

Each switch has a control terminal, a first terminal and a second terminal. A first terminal of the switch _M1 is coupled to the signal input terminal IP to receive the input signal Input(n), a second terminal is coupled to the node X, and a control terminal is coupled to the clock signal CK1. A first terminal of the switch M ₂ is coupled to the clock signal CK4 , a second terminal is coupled to the signal output terminal OP to output the output signal Output(n), and a control terminal is coupled to the node X.

16A and 16B show the driving method of the gate drive circuit 60 according to the embodiment of the present invention, wherein FIG. 16A shows the gate drive circuit 60 according to the input signal Input(n), clock signal CK1, The clock signal CK4, the potential of node X, the output signal Output(n), the output signal Output(n+1), the timing diagram of the output signal Output(n+2), and Fig. 16B is the switch M ₁ relative to Fig. 16A to the operating state of switch _M2 .

During T1, the clock signal CK1 and the input signal Input(n) are at a high level, so the switch _M1 is turned on, and the high level of the input signal Input(n) is coupled to the node X through the switch _M1 and the node X The potential of the node X is charged to a high level, and the high level potential of the node X turns on the switch _M2 so that the high level potential of the clock signal CK4 is coupled to the signal output terminal OP to output a high level output signal Output(n).

During T2, the clock signal CK1 is at a low level, so the switch _M1 is turned off. The potential of node X remains at a high level because there is no discharge path, so that the switch _M2 is turned on, and the high level of the clock signal _CK4 is coupled to the signal output terminal OP via the switch M2 to output a high level output signal Output( n).

During T3, the clock signal CK1 is at a low level, so the switch _M1 is turned off. The potential of the node X remains at a high level because there is no discharge path, so that the switch _M2 is turned on, and the low level of the clock signal CK4 is coupled to the signal output terminal OP through the switch _M2 to output a low level output signal Output( n).

During T4, the clock signal CK1 is at a high level, so the switch _M1 is turned on. At this time, the low level of the input signal Input(n) is coupled to the node X, so that the potential of the node X is at a low level, and the switch _M2 When it is turned off, the signal output terminal OP maintains a low level and outputs a low level output signal Output(n).

During T5 and T6, the clock signal CK1 is at the low level, so the switch _M1 is closed, the node X remains at the low level, the switch _M2 remains closed, the signal output terminal OP maintains the low level and outputs a low level output Signal Output(n).

During T7, the clock signal CK1 is at a high level, so the switch _M1 is turned on. At this time, the low level of the input signal Input(n) is coupled to the node X, so that the potential of the node X is at a low level, and the switch _M2 When it is turned off, the signal output terminal OP maintains a low level and outputs a low level output signal Output(n).

During T8, the clock signal CK1 is at a low level, so the switch _M1 is closed, the node X remains at a low level, the switch _M2 remains closed, and the signal output terminal OP maintains a low level to output a low level output signal Output (n).

The output signal (n+1) and the output signal (n+2) are the output signals of the next level and the next two levels of driving units, and their timing diagrams can be deduced according to the above description. According to the gate driving circuit and driving method described in the embodiment of FIG. 14A to FIG. 16B of the present invention, if the pulse width of the input signal or the clock signal CK1 is used as the first width W as a reference, the output signal Output of each level of driving unit, Its pulse width is 2W, and the output signal of each level of driving unit lags behind the output signal of the previous level of driving unit by a W, that is, the pulses of adjacent output signals partially overlap each other by a first width (W), so the driven column The turn-on time of the switching element of the pixel can be extended to achieve the effect of pre-charging. In addition, it can also be seen from FIG. 16A that the output signal Output(n) of the nth level driving unit partially overlaps with its input signal Input(n), and the overlapping width is also the first width (W). In addition, the signal pulse of the node X is three times the first width (W), and the clock signals CK1 , CLK4 and the input signal (or start signal) are generated synchronously with each other.

In addition, the advantages of the embodiments shown in Figures 14A to 16B are roughly the same as those of the previous embodiments, the difference being that the duty cycle of the clock signal used in this embodiment is 2/3, while that of the previous embodiments is 1/2, but because each The first-level drive unit only needs one clock signal, so it still has the effect of saving power. In addition, in this embodiment, only two switching elements are required for each stage of the driving unit, the required layout area is small, and the design is easy.

As mentioned above, according to the gate driving circuit and driving method of the embodiment of the present invention, not only the stability and reliability of the operation are improved, but also the power consumption of the overall driving circuit is significantly reduced by reducing the number of clock signals and the duty cycle of the clock signal. reduce.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention; all other equivalent modifications or variations that do not deviate from the spirit disclosed in the present invention should be included in the appended claims In the range.

Claims (32)

1. A gate drive circuit, comprising a plurality of drive units connected in series, each drive unit comprising: The signal input terminal receives the input signal; The feedback signal input terminal receives the feedback signal; Carrier signal output terminal, output carrier signal; The signal output terminal outputs an output signal to drive a column of pixels; a first switch, the first end and the control end of which are coupled to the signal input end to receive the input signal, and the second end is coupled to the first node; The second switch has a first end coupled to a clock signal, a second end coupled to a second node and the carrier signal output end to output the carrier signal, and a control end coupled to the first node; a third switch, the first end of which is coupled to the first node, the second end is coupled to a low voltage source, and the control end is coupled to the feedback signal input end to receive the feedback signal; A fourth switch, the first end of which is coupled to a high voltage source, the second end is coupled to the signal output end, and the control end is coupled to the first node; A fifth switch, the first end of which is coupled to the second end of the fourth switch and the signal output end, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; and A sixth switch, the first end of which is coupled to the second node, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; The carrier signal output end of each drive unit is coupled to the signal input end of the next-stage drive unit, and the feedback signal input end is coupled to the output signal ends of the next two-stage drive units. 2. The gate drive circuit according to claim 1, wherein the signal input terminal of the first-level drive unit of the plurality of serially connected drive units receives a start signal as the first-level drive unit The input signal, the pulse width of the start signal is the first width (W), the pulse width of the clock signal is also the first width (W), and the duty cycle is 1/2, and the clock signal A time difference of the first width (W) behind the start signal. 3. The gate drive circuit according to claim 2, wherein the pulse width of the output signal of each drive unit is a second width (2W), and the second width is the first width (W) twice, and the pulses of the output signals of two adjacent driving units partially overlap with each other. 4. The gate driving circuit according to claim 3, wherein a width of the overlapping portion is the first width (W). 5. The gate driving circuit according to claim 3, wherein the output signal of the first-level driving unit and the pulse of the start signal partially overlap with each other, and the width of the overlapping portion is the first width. 6. The gate drive circuit according to claim 2, comprising only two clock signals with a time difference of the first width (W) between them, and each drive unit receives the two clock signals One of them is used as the respective clock signal, and two adjacent drive units receive different clock signals. 7. The gate driving circuit according to claim 2, wherein the size of the fourth switch and the fifth switch is tens to hundreds of times larger than the size of the second switch and the sixth switch. 8. The gate drive circuit according to claim 2, wherein the carrier signal output by each drive unit lags behind the input signal received by the drive unit by a time difference of the first width (W), and each drive unit The pulse width of the output signal is twice the first width, and except for the first level of driving unit, the output signal of each level of driving unit lags behind the output signal of the previous driving unit by a time difference of the first width. 9. A gate drive circuit, comprising a plurality of drive units connected in series, each drive unit comprising: The signal input terminal receives the input signal; The feedback signal input terminal receives the feedback signal; Carrier signal output terminal, output carrier signal; The signal output terminal outputs an output signal to drive a column of pixels; a first switch, the first end of which is coupled to the first clock signal, the second end is coupled to the first node and the signal output end, and the control end is coupled to the signal input end; A second switch, the first end of which is coupled to the second clock signal, the second end is coupled to the second node and the carrier signal output end, and the control end is coupled to the first node; a third switch, the first end of which is coupled to the first node, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; A fourth switch, the first end of which is coupled to the second node and the carrier signal output end, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; The carrier signal output end of each drive unit is coupled to the signal input end of the next-stage drive unit, and the feedback signal input end is coupled to the output signal ends of the next two-stage drive units. 10. The gate drive circuit according to claim 9, wherein the signal input end of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the first-level drive unit The input signal, the pulse width of the start signal is the first width (W), the duty cycles of the first clock signal and the second clock signal are both 1/2, and the pulse width is also the first Width (W), the second clock signal lags behind the first clock signal by a time difference of the first width (W), and the first clock signal is synchronized with the start signal. 11. The gate driving circuit according to claim 9, comprising only the first clock signal and the second clock signal. 12. The gate drive circuit according to claim 10, wherein the pulse width of the output signal of each drive unit is a second width (2W), and the second width is the first width (W) twice of that, and the pulses of the output signals of two adjacent drive units partially overlap with each other. 13. The gate driving circuit according to claim 10, wherein a width of an overlapping portion of the output signal of the first-level driving unit and the pulse of the start signal is the first width. 14. The gate driving circuit according to claim 9, wherein the size of the first switch and the third switch is tens to hundreds of times larger than the size of the second switch and the fourth switch. 15. The gate drive circuit according to claim 10, wherein the carrier signal output by each drive unit lags behind the input signal received by the drive unit by a time difference of the first width (W), and each drive unit The output signal, its pulse width is twice the first width (W), and except for the first-level drive unit, the output signal of each level of drive unit lags behind the output signal of the previous drive unit by one of the first width (W) time difference. 16. A gate drive circuit, comprising a plurality of drive units connected in series, each drive unit comprising: The signal input terminal receives the input signal; The feedback signal input terminal receives the feedback signal; The signal output terminal outputs an output signal to drive a column of pixels; a first switch, the first end of which is coupled to a clock signal, the second end is coupled to a node and the signal output end, and the control end is coupled to the signal input end; a second switch, the first terminal of which is coupled to the node and the signal output terminal, the second terminal is coupled to the low voltage source, and the control terminal is coupled to the feedback signal input terminal; The signal output terminal of each driving unit is coupled to the signal input terminal of the next-level driving unit, and the feedback signal input terminal is coupled to the output signal terminals of the next two-level driving units. 17. The gate drive circuit according to claim 16, wherein the signal input end of the first-level drive unit of the plurality of series-connected drive units receives a start signal as the input of the first-level drive unit signal, the pulse width of the start signal is the first width (W), the duty cycle of the clock signal is 1/2, and the pulse width is also the first width (W), and the clock signal and the The start signal is synchronized. 18. The gate drive circuit according to claim 17, comprising only two clock signals with a time difference of the first width (W) between them, and each drive unit receives the two clock signals One of them is used as the respective clock signal, and two adjacent drive units receive different clock signals. 19. The gate driving circuit according to claim 17, wherein the pulse width of the output signal of each driving unit is a second width (2W), and the second width is the first width (W) twice, the pulses of the output signals of any two adjacent driving units partly overlap with each other, and the output signal of the first driving unit and the pulses of the start signal partly overlap with each other. 20. The gate driving circuit according to claim 17, wherein the output signal of each driving unit has a pulse width twice the first width (W), and is one behind the output signal of the previous driving unit The time difference of the first width (W). 21. A gate drive circuit, comprising a plurality of drive units connected in series, each drive unit comprising: The signal input terminal receives the input signal; The feedback signal input terminal receives the feedback signal; The signal output terminal outputs an output signal to drive a column of pixels; a first switch, the first end and the control end of which are jointly coupled to the input signal end, and the second end is coupled to the node; a second switch, the first end of which is coupled to the clock signal, the second end is coupled to the signal output end, and the control end is coupled to the node; and a third switch, the first end of which is coupled to the node, the second end is coupled to the low voltage source, and the control end is coupled to the feedback signal input end; The signal output terminal of each drive unit is coupled to the signal input terminal of the next-level drive unit, and the feedback signal input terminal is coupled to the output signal terminals of the next three-level drive units. 22. The gate drive circuit according to claim 21, wherein the signal input terminal of the first-level drive unit of the plurality of serially connected drive units receives a start signal as the input of the first-level drive unit signal, the pulse width of the start signal is the first width (W), the duty cycle of the clock signal is 2/3, the pulse width is twice the first width (W), and the start signal is synchronized with the clock signal. 23. The gate drive circuit according to claim 22, wherein the pulse width of the output signal of each driving unit is twice the first width (W), and the pulse width of the output signal of any two adjacent driving units partly overlap with each other, and the width of the overlapping portion of the pulses of the output signal of the first-level driving unit and the start signal is the first width. 24. The gate drive circuit according to claim 22, comprising only two clock signals with a time difference of the first width (W) between them, and each drive unit receives the two clock signals One of them is used as the respective clock signal, and two adjacent drive units receive different clock signals. 25. The gate driving circuit according to claim 22, wherein the output signal of each driving unit has a pulse width twice the first width (W), and is behind the output signal of the previous driving unit by one The time difference of the first width (W). 26. The gate driving circuit according to claim 22, the pulse width of the signal of the node is three times of the first width. 27. A gate drive circuit, comprising a plurality of drive units connected in series, each drive unit comprising: The signal input terminal receives the input signal; The signal output terminal outputs an output signal to drive a column of pixels; a first switch, the first end of which is coupled to the signal input end, the second end is coupled to the node, and the control end is coupled to the first clock signal; a second switch, the first end of which is coupled to a second clock signal, the second end is coupled to the signal output end, and the control end is coupled to the node; The signal output end of each driving unit is coupled to the signal input end of the next-level driving unit, wherein the signal input end of the first-level driving unit of the plurality of series-connected driving units receives a start signal as the For the input signal of the first-level drive unit, the pulse width of the start signal is the first width (W), the duty cycle of the first clock signal is 1/3, and the pulse width is also the first width (W), the duty cycle of the second clock signal is 2/3, and the pulse width is twice the first width (W), the start signal and the first clock signal and the second The clock signal is synchronized. 28. The gate driving circuit according to claim 27, wherein pulses of the first clock signal and the second clock signal partially overlap with each other, and the width of the overlapping portion is the first width. 29. The gate drive circuit according to claim 27, wherein the pulse width of the output signal of each driving unit is twice the first width (W), and the pulse width of the output signal of any two adjacent driving units Some of them overlap with each other, and the width of the overlapping portion of the output signal of the first-level driving unit and the pulse of the start signal is the first width. 30. The gate driving circuit according to claim 27, the pulse width of the signal of the node is three times of the first width. 31. The gate drive circuit according to claim 27, comprising a first group and a second group of clock signals, wherein each group of clock signals includes three clock signals, and the pulse width of the first group of clock signals is The first width, and the pulse width of the second group of clock signals is twice the first width, and each drive unit only receives one of the first group of clock signals and the second One of the group of clock signals is used as the respective first and second clock signals, and two adjacent driving units receive different clock signals. 32. The gate driving circuit according to claim 27, wherein the pulse width of the output signal of each driving unit is twice the first width (W), and except for the first-level driving unit, each level The output signal of the driving unit lags behind the output signal of the previous driving unit by a time difference of the first width (W).

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