CN102055446B - Drive circuit of power transistor - Google Patents
Drive circuit of power transistor Download PDFInfo
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- CN102055446B CN102055446B CN200910209932A CN200910209932A CN102055446B CN 102055446 B CN102055446 B CN 102055446B CN 200910209932 A CN200910209932 A CN 200910209932A CN 200910209932 A CN200910209932 A CN 200910209932A CN 102055446 B CN102055446 B CN 102055446B
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Abstract
The invention discloses a drive circuit of a power transistor, comprising a first switch, a second switch, a third switch and a fourth switch. The first switch is connected to a first node, a second node and a first power supply end providing a first voltage. The second switch is connected to the first node, the second node and a first earthing end. The third switch is connected to the second node, a third node and the first power supply end. The fourth switch is connected to the second node, the third node and a second earthing end. The power transistor is connected to the third node, and a pulse-width regulating signal is input from the first node. The pulse-width regulating signal is provided with a second voltage smaller than the first voltage.
Description
Technical field
The present invention refers to a kind of drive circuit that can effectively reduce conducting loss (conduction loss) with the exchange loss (switching loss) of power transistor especially about a kind of drive circuit of power transistor.
Background technology
See also Fig. 1, Fig. 1 is the sketch map of known boosting (boost) circuit 1.Known booster circuit 1 comprises inductance (inductor) 10, Schottky diode (Schottky diode) 12, load (loading) 14, PWM (Pulse Width Modulation; PWM) signal generation unit 16 and power transistor (power MOSFET) 18; Wherein the annexation of said modules such as Fig. 1 illustrate; And its action principle can be reached by the people of known skill easily, repeats no more at this.
As shown in Figure 1, when the carrier structure was attached most importance in load 14, power transistor 18 need be selected high-power specification for use, drove the required high voltage of heavy duty to reach.Yet; Because the power transistor of being selected for use 18 needs can be high pressure resistant; So its inner conducting resistance (drain-sourceon-state resistance, Rds (on)) is all very big with parasitic capacitance, the conducting loss when making power transfer will become very big with the exchange loss.Under power loss became big situation, conversion efficiency is variation thereupon also.
In addition, United States Patent (USP) announces the 7th, 459, and No. 945 (hereinafter to be referred as ' 945 patent) is provided with a gate driver circuit (gate driving circuit) between power transistor and pwm signal, with driving force and the reduction loss that increases power transistor.' the 945 disclosed gate driver circuit of patent mainly comprises a control switching circuit (switching control circuit), four diverter switches, four Schottky diodes and an inductance.' 945 patent is to control four diverter switches respectively by control switching circuit, so that inductance is discharged and recharged.In other words, ' 945 patent need be provided with control switching circuit (as the usefulness of SECO) and inductance (as the usefulness of energy storage), just can reach the conversion efficiency of improving power transistor.Yet the setting of control switching circuit and inductance will increase the area of circuit design, and inductance is in charge and discharge process, the disturbing effect that will generate electromagnetic waves.
Summary of the invention
Therefore, one of the object of the invention is to provide a kind of drive circuit of power transistor, and it is arranged between pwm signal generation unit and the power transistor, can effectively reduce the conducting loss and exchange loss of power transistor, to address the above problem.
According to an embodiment, the drive circuit of power transistor of the present invention comprises one first switch, a second switch, one the 3rd switch and one the 4th switch.This first switch is connected in a first node, a Section Point and one first power end, and this first power end provides one first voltage.This second switch is connected in this first node, this Section Point and one first ground end.The 3rd switch is connected in this Section Point, one the 3rd node and this first power end.The 4th switch is connected in this Section Point, the 3rd node and one second ground end.
In this embodiment, a power transistor is connected in the 3rd node, and a PWM signal is from this first node input.This PWM signal has one second voltage, and this second voltage is less than this first voltage.When this PWM signal is high levle, promptly by this first switch and the 4th switch, and this second switch of conducting and the 3rd switch, and this first voltage is via the 3rd switch and the output of the 3rd node, with this power transistor of conducting.On the other hand, when this PWM signal is low level, i.e. this first switch of conducting and the 4th switch, and by this second switch and the 3rd switch, and this power transistor discharges to this second ground end via the 4th switch.
Can graphicly further be understood by following detailed Description Of The Invention and appended about advantage of the present invention and spirit.
Description of drawings
Fig. 1 is the sketch map of known booster circuit.
Fig. 2 is the sketch map of drive circuit according to an embodiment of the invention.
Fig. 3 is the sequential chart of the operation waveform of each signal in drive circuit.
Fig. 4 is the simulation waveform figure at the pulse wave signal of the gate terminal of power transistor.
Fig. 5 is applied to the sketch map of booster circuit for drive circuit of the present invention.
Fig. 6 is applied to the sketch map of LED-backlit drive circuit for drive circuit of the present invention.
Embodiment
See also Fig. 2, Fig. 2 is the sketch map of drive circuit 30 according to an embodiment of the invention.As shown in Figure 2, drive circuit 30 is connected between pwm signal generation unit 32 and the power transistor 34.Drive circuit 30 comprises first switch 300, second switch 302, the 3rd switch 304 and the 4th switch 306.In this embodiment, first switch 300 and the 3rd switch 304 can be the P transistor npn npn, and second switch 302 and the 4th switch 306 can be the N transistor npn npn.In other words, first switch 300 constitutes reversers (inverter) with second switch 302, and the 3rd switch 304 and the 4th switch 306 also constitute a reverser.
The grid G 1 of first switch 300 is connected in first node N1, and source S 1 is connected in Section Point N2, and drain D 1 is connected in the first power end VDD.The grid G 2 of second switch 302 is connected in first node N1, and drain D 2 is connected in Section Point N2, and source S 2 is connected in the first ground end GND1.The grid G 3 of the 3rd switch 304 is connected in Section Point N2, and source S 3 is connected in the 3rd node N3, and drain D 3 is connected in the first power end VDD.The grid G 4 of the 4th switch 306 is connected in Section Point N2, and drain D 4 is connected in the 3rd node N3, and source S 4 is connected in the second ground end GND2.
In this embodiment, power transistor 34 also is the N transistor npn npn.The grid G 5 of power transistor 34 is connected in the 3rd node N3, and drain D 5 is connected in second source end VCC, and source S 5 is connected in three locations end GND3.In addition, pwm signal generation unit 32 is connected in first node N1, so the pwm signal that pwm signal generation unit 32 produces is from first node N1 input driving circuit 30.
See also Fig. 3, Fig. 3 is the sequential chart of the operation waveform of each signal in drive circuit 30.At time t1 to t2, the pwm signal of importing from first node N1 is a high levle, at this moment, and by first switch 300, and conducting second switch 302, make that pwm signal is a low level when Section Point N2 exports.Since obtain low level at Section Point N2, thus conducting the 3rd switch 304, and, make that pwm signal is a high levle when the 3rd node N 3 outputs by the 4th switch 306.At this moment, first voltage that the first power end VDD is provided can be via the 3rd switch 304 and the 3rd node N3 output, with conducting power transistor 34.
In this embodiment; First voltage that the first power end VDD is provided (for example 5 volts) is set at second voltage (for example 3.3 volts) greater than pwm signal; By this; Drive circuit 30 of the present invention can amplify the output pulse wave of pwm signal, makes gate-source voltage (gate-to-source voltage, the V of power transistor 34
CS) become big.Therefore, the conducting currier in power transistor 34 passages can increase (can be imagined as channel depth also increases), makes electricity lead increase or is equivalent to resistance to reduce, and then reduce the conducting loss, promotes conversion efficiency.What need explanation is, first voltage is as long as set than second voltage more greatly, does not exceed with above-mentioned 5 volts and 3.3 volts, can determine according to practical application.
At time t2 to t3, the pwm signal of importing from first node N1 is a low level, at this moment, and conducting first switch 300, and, make that pwm signal is a high levle when Section Point N2 exports by second switch 302.Because obtain high levle at Section Point N2, so by the 3rd switch 304, and conducting the 4th switch 306, make that pwm signal is a low level when the 3rd node N3 exports.At this moment, power transistor 34 can discharge via the 4th switch 306 pairs second ground end GND2.
More than be the explanation when in one-period, being high levle and low level to pwm signal, follow-up action principle can the rest may be inferred, repeats no more at this.
See also Fig. 4, Fig. 4 is the simulation waveform figure at the pulse wave signal of grid G 5 ends of power transistor 34.As shown in Figure 4, solid line A representes to use the simulation waveform behind the drive circuit 30 of the present invention, and dotted line B representes to use the simulation waveform before the drive circuit 30 of the present invention.Significantly, drive circuit 30 of the present invention can reduce discharging and recharging the time of parasitic capacitance in the power transistor 34, and wherein discharge path is via the 4th switch 306 pairs second ground end GND2 and discharges.Therefore, can reduce exchange loss, make that the pulse wave signal at grid G 5 ends of power transistor 34 presents more complete square wave, like the solid line A that Fig. 4 illustrated.
See also Fig. 5, Fig. 5 is applied to the sketch map of booster circuit 3 for drive circuit 30 of the present invention.Booster circuit 3 comprises drive circuit 30, pwm signal generation unit 32, power transistor 34, inductance 36, Schottky diode 38 and load 40, wherein the load 40 carrier structure of attaching most importance to.As shown in Figure 5, drive circuit 30 is connected between pwm signal generation unit 32 and the power transistor 34, and its action principle repeats no more at this as stated.In addition, annexation such as Fig. 5 of above-mentioned other assembly illustrate, and its action principle can be reached by the people of known skill easily, also repeat no more at this.
See also Fig. 6, Fig. 6 is applied to the sketch map of LED-backlit drive circuit 5 for drive circuit 30 of the present invention.LED-backlit drive circuit 5 comprises drive circuit 30, pwm signal generation unit 32, power transistor 34, inductance 36, Schottky diode 38, a plurality of LED-backlit module 50 and currents match unit 52; Wherein a plurality of LED-backlit modules 50 are the many frameworks also of many strings, are equivalent to the load 40 among Fig. 5.As shown in Figure 6, drive circuit 30 is connected between pwm signal generation unit 32 and the power transistor 34, and its action principle repeats no more at this as stated.In addition, annexation such as Fig. 6 of above-mentioned other assembly illustrate, and its action principle can be reached by the people of known skill easily, also repeat no more at this.
Though the drive circuit 30 that Fig. 2 illustrated is to utilize two reversers to reduce the conducting loss and exchange loss of power transistor 34, the present invention is not exceeded with two reversers.If frequency of pwm signal higher or above-mentioned first, second, third and/or the 4th switch 300-306 are non-to be perfect condition; The present invention also can be provided with plural reverser (for example four, six, by that analogy) in drive circuit 30; With the conducting loss and exchange loss that more effectively reduces power transistor 34, and then let the pulse wave signal of grid G 5 ends of power transistor 34 present more complete square wave.
Compared to prior art, the drive circuit that the present invention only utilizes four switch modules to form, and directly utilize pwm signal to control the switching of four switches, can reduce the conducting loss and exchange loss of power transistor effectively.Drive circuit of the present invention is not only simple in structure, and can not take too many circuit layout area.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (6)
1. the drive circuit of a power transistor is characterized in that, comprises:
One first switch is connected in a first node, a Section Point and one first power end, and this first power end provides one first voltage; This first switch is a P transistor npn npn, has a grid, is connected in this first node; One source pole is connected in this Section Point; With a drain electrode, be connected in this first power end;
One second switch is connected in this first node, this Section Point and one first ground end; This second switch is a N transistor npn npn, has a grid, is connected in this first node; One drain electrode is connected in this Section Point; With one source pole, be connected in this first ground end;
One the 3rd switch is connected in this Section Point, one the 3rd node and this first power end; The 3rd switch is a P transistor npn npn, has a grid, is connected in this Section Point; One source pole is connected in the 3rd node; With a drain electrode, be connected in this first power end; And
One the 4th switch is connected in this Section Point, the 3rd node and one second ground end; The 4th switch is a N transistor npn npn, has a grid, is connected in this Section Point; One drain electrode is connected in the 3rd node; With one source pole, be connected in this second ground end;
Wherein, a power transistor is connected in the 3rd node, and a PWM signal is from this first node input, and this PWM signal has one second voltage, and this second voltage is less than this first voltage;
Wherein, when this PWM signal is high levle, promptly by this first switch and the 4th switch, and this second switch of conducting and the 3rd switch, and this first voltage is via the 3rd switch and the output of the 3rd node, so that this power transistor conducting;
When this PWM signal is low level, i.e. this first switch of conducting and the 4th switch, and by this second switch and the 3rd switch, and this power transistor discharges to this second ground end via the 4th switch.
2. the drive circuit of power transistor as claimed in claim 1 is characterized in that, this power transistor has a grid, is connected in the 3rd node; One drain electrode is connected in a second source end; With one source pole, be connected in a three locations end.
3. the drive circuit of power transistor as claimed in claim 1 is characterized in that, when this PWM signal is high levle, and by this first switch, and this second switch of conducting, this PWM signal is a low level when this Section Point output.
4. the drive circuit of power transistor as claimed in claim 3 is characterized in that, when when this Section Point is low level, and by the 4th switch, and conducting the 3rd switch, this PWM signal is a high levle when the 3rd node is exported.
5. the drive circuit of power transistor as claimed in claim 1 is characterized in that, when this PWM signal is low level, and this first switch of conducting, and by this second switch, this PWM signal is a high levle when this Section Point output.
6. the drive circuit of power transistor as claimed in claim 5 is characterized in that, when when this Section Point is high levle, and conducting the 4th switch, and by the 3rd switch, this PWM signal is a low level when the 3rd node is exported.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209932A CN102055446B (en) | 2009-10-29 | 2009-10-29 | Drive circuit of power transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209932A CN102055446B (en) | 2009-10-29 | 2009-10-29 | Drive circuit of power transistor |
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| CN102055446A CN102055446A (en) | 2011-05-11 |
| CN102055446B true CN102055446B (en) | 2012-09-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2981228B1 (en) * | 2011-10-05 | 2013-12-20 | Valeo Systemes Thermiques | CONTROL CIRCUIT FOR VOLTAGE ELEVATOR CIRCUIT, CONTROL DEVICE AND CORRESPONDING CONTROL SYSTEM. |
| CN104124951B (en) * | 2013-04-29 | 2017-05-17 | 联发科技（新加坡）私人有限公司 | Circuit for driving high-side transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1097344C (en) * | 1995-10-27 | 2002-12-25 | 皇家菲利浦电子有限公司 | CMOS driver circuit |
| CN1815866A (en) * | 2004-12-16 | 2006-08-09 | 半导体元件工业有限责任公司 | Power MOSFET driver and method therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080186004A1 (en) * | 2005-11-29 | 2008-08-07 | Advanced Analogic Technologies, Inc. | High-Frequency Power MESFET Boost Switching Power Supply |
| JP4436406B2 (en) * | 2007-12-12 | 2010-03-24 | 矢崎総業株式会社 | Load control device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1097344C (en) * | 1995-10-27 | 2002-12-25 | 皇家菲利浦电子有限公司 | CMOS driver circuit |
| CN1815866A (en) * | 2004-12-16 | 2006-08-09 | 半导体元件工业有限责任公司 | Power MOSFET driver and method therefor |
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Effective date of registration: 20230530 Address after: Lake 558, Fen Hu Town, Wujiang District, Jiangsu, Suzhou Patentee after: Wujiang FenHu technology entrepreneurship Service Co.,Ltd. Address before: 215217, No. 88, Tung Hing Road, Tongli District, Wujiang Economic Development Zone, Suzhou, Jiangsu Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |