CN102054743B - Method for forming contact hole in semiconductor device - Google Patents
Method for forming contact hole in semiconductor device Download PDFInfo
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- CN102054743B CN102054743B CN200910197944.1A CN200910197944A CN102054743B CN 102054743 B CN102054743 B CN 102054743B CN 200910197944 A CN200910197944 A CN 200910197944A CN 102054743 B CN102054743 B CN 102054743B
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Abstract
The invention discloses a method for forming a contact hole in a semiconductor device. The method comprises the following steps of: providing a dielectric layer on a front end device layer; depositing a layer of polycrystalline silicon which serves as a hard mask layer on the dielectric layer; performing spin coating on a first bottom anti-reflection coating on the hard mask layer and coating a patterned photoresist layer; etching the first bottom anti-reflection coating and the hard mask layer by taking the photoresist layer as a mask; removing the photoresist layer and the first bottom anti-reflection coating; etching the contact hole on the dielectric layer by taking the hard mask layer as a mask; backfilling a second bottom anti-reflection coating into the contact hole and etching the second bottom anti-reflection coating back until the upper surface of the second bottom anti-reflection coating is flush with or a slightly higher than the lower surface of the hard mask layer; removing the hard mask layer by dry etching; and removing the second bottom anti-reflection coating remaining inside the contact hole.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of method of in semiconductor device, making contact hole.
Background technology
Along with the development of very lagre scale integrated circuit (VLSIC) technique, semiconductor technology has now entered the sub-micro epoch.The development of technique forms so-called SoC (SOC (system on a chip)) so that will comprise that processor, memory, analog circuit, interface logic even radio circuit are integrated on the large-scale chip and become.As the in-line memory of SoC important component part, proportion shared in SoC increases gradually.In a lot of equipment such as in-line memory, comprise non-volatile memories (NVM) medium, be used for using after restarting in order to equipment in storage data after the device powers down.Non-volatile memory medium comprises EPROM (EPROM), Electrically Erasable Read Only Memory (EEORPM), NAND type flash memory, NOR type flash memory etc.Wherein, NOR type flash memory has more widely application in actual applications.
The technique of making in-line memory faces a lot of challenges, is not easy to combine with the Technology development that is used for logical circuit because be used for the common process technology of nonvolatile memory.The performance of non-volatile memory medium is embedded among the high speed MOS must be in conjunction with the manufacturing step that is used for the NVM device and the step of high-voltage CMOS element of the common needs of operation that is used for the memory element of non-volatile memory medium.The floating gate structure of NOR type flash memory requires inter-level dielectric very thick, and therefore, the making of the contact hole on the inter-level dielectric just becomes the technology of a key.This is because contact hole is the passage that connects front road transistor unit and rear road metal wiring, should connect transistorized grid, be connected to again source-drain electrode, its critical size (Critical Dimension) and appearance profile are extremely important for performance of devices, mainly can affect static leakage current (IDDQ), the critical size that is contact hole is less, and the probability that larger static leakage current occurs is less.A lot of flash memories require the critical size of contact hole little, and the degree of depth is larger, and the ratio of critical size and the contact hole degree of depth is about 0.1～0.4 at high proportion degree as reaching.
In the method for traditional making contact hole, in the larger situation of critical dimension of contact hole, only can etching form contact hole with photoresist layer as mask.Yet, along with critical size reduce or the ratio of critical size and the contact hole degree of depth more and more less, only make with photoresist mask and can serve problem at technique band.This is because the material quality of photoresist is softer, if the depth requirements of contact hole is very large, then the duration can be very long in the process of etching formation contact hole, therefore may produce damage to photoresist layer along with the carrying out of etching, thereby destroy the figure of mask layer, so that the contact hole that etches does not all reach required requirement at aspects such as critical size or the degree of depth.
In order to overcome this problem, available technology adopting the technique of independent increase by one hard mask layer, first the pattern of photoresist is transferred on the hard mask layer first, and then is gone out contact hole with hard mask layer as mask etching.Because the material of hard mask layer is usually harder, therefore can bears long-term etching and can not sustain damage, thereby can produce the dark and less contact hole of critical size of the degree of depth.
Utilize above-mentioned technique to form the method for contact hole shown in Figure 1A to 1D.Shown in Figure 1A, made semiconductor device, for example provide a dielectric layer 101 on the front end device layer 100 of MOS transistor, material can be chosen as phosphorous oxide.This layer plays the purposes of insulation, the metal interconnecting layer that is used for isolating device and forms afterwards.With CVD method deposition one deck hard mask layer 102, material is chosen as amorphous carbon on dielectric layer 101, and its thickness for example is that 3000 Izods are right.Then, spin coating one bottom antireflective coating (BARC) 103 on hard mask layer 102, thickness is approximately 1000 dusts, then is with figuratum photoresist layer 104 in bottom antireflective coating 103 coatings.Then, as shown in Figure 1B, etch contact hole 105 at bottom antireflective coating 103 and hard mask layer 102, thus with the design transfer of photoresist to hard mask layer 102.Then carry out cineration technics, remove photoresist layer 104 and bottom antireflective coating 103.Next, shown in Fig. 1 C, take hard mask layer 102 as mask plate, etch contact hole 106.Then, shown in Fig. 1 D, carry out the high temperature cineration technics, remove hard mask layer 102, finish the formation of contact hole in the dielectric layer 101.
The material of the hard mask layer that uses in the above-mentioned process is amorphous carbon, and this can bring new problem.At first, amorphous carbon is expensive, has greatly improved cost of manufacture.Secondly, because the amorphous carbon material has porousness, quality is loose, therefore removes in the step of photoresist damaged easily at the above-mentioned cineration technics that passes through.If change and adopt acid solution to clean to remove photoresist, because the porous character of amorphous carbon, acid solution remains in the amorphous carbon again easily, thereby further injures other structure of the semiconductor device that lower floor formed.
So, need a kind of hard mask material of new making contact hole, can adopt self-aligned technology, be not easy again in the process of etching contact hole, to be damaged, and cost of manufacture is descended.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The problems referred to above that produce when solving the darker contact hole of existing making the invention provides a kind of method of making the contact hole in the semiconductor device, and described method comprises the following steps: to provide a dielectric layer at the front end device layer; Deposit one deck polysilicon as hard mask layer at described dielectric layer; Spin coating the first bottom antireflective coating on described hard mask layer; Be with figuratum photoresist layer in described the first bottom antireflective coating coating; With described photoresist layer as mask, described the first bottom antireflective coating of etching and described hard mask layer, thus with the design transfer of described photoresist layer to described hard mask layer; Remove described photoresist layer and the first bottom antireflective coating; As mask, etch contact hole at described dielectric layer with described hard mask layer; Back-filling the second bottom antireflective coating in described contact hole is until the upper surface of the second bottom antireflective coating is higher than the upper surface of described hard mask layer; Eat-back described the second bottom antireflective coating, the upper surface of described the second bottom antireflective coating is flushed or a little more than the latter with the lower surface of described hard mask layer; Utilize dry etching to remove described hard mask layer; Remove the second inner residual bottom antireflective coating of described contact hole.
Preferably, the thickness of described hard mask layer is selected according to the degree of depth of described contact hole.
Preferably, the thickness of described hard mask layer is 500～3000 dusts.
Preferably, the source gas of the described hard mask layer of described dry etching is CF
4And O
2Mist.Described CF
4Flow velocity be 300～600sccm, O
2Flow velocity be 400～800sccm.
Preferably, the material of described the first and second bottom antireflective coatings is organic materials, and main component is the polymerization amino acid.
Preferably, the ratio of the critical size of described contact hole and the contact hole degree of depth is 0.1～0.4.
Preferably, utilize cineration technics to remove described photoresist layer, described the first and second bottom antireflective coatings.
The polysilicon that utilizes according to the present invention can adopt self-aligned technology as the method for hard mask manufacture contact hole, is not easy again to be damaged in the process of etching contact hole, and cost of manufacture is descended.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 D is traditional technological process generalized section that forms contact hole structure with amorphous carbon as hard mask layer;
Fig. 2 A to Fig. 2 F is the contact hole structure generalized section according to employing polysilicon hard mask layer of the present invention;
Fig. 3 is the manufacturing process flow diagram according to the contact hole structure of employing polysilicon hard mask layer of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention utilizes polycrystalline silicon material to make hard mask layer in order to solve a difficult problem of making the large contact hole of the little degree of depth of critical size in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Utilize amorphous carbon to make the problems that contact hole brings as hard mask layer in the traditional handicraft in order to overcome, for example cost is high and can't make preferably the large contact hole of the little degree of depth of critical size, the present invention proposes a kind ofly to overcome this problem with polysilicon as the technique of hard mask layer making contact hole.With reference to Fig. 2 A to Fig. 2 F, illustrate according to of the present invention and have polysilicon firmly as the cutaway view of each step in the fabrication processing of the contact hole structure of mask layer.
At first, shown in Fig. 2 A, made semiconductor device, for example provide a dielectric layer 201 on the front end device layer 200 of MOS transistor, material can be chosen as phosphorous oxide.This layer adopts insulating material, plays the purposes of insulation, the metal interconnecting layer that is used for isolating device and forms afterwards.On dielectric layer 201 by boiler tube deposition one deck polycrystalline silicon material as hard mask layer 202, the thickness of this layer is decided according to the diameter of the degree of depth of required contact hole and contact hole, for example is the 500-3000 dust.Particularly, when the degree of depth of contact hole is about 7000 dusts, during about 120 nanometer of contact hole diameter, the thickness of hard mask layer 202 can be 1500 dusts.In follow-up technique, will carry out take the hard mask layer 202 of this polycrystalline silicon material as etch mask layer the etching of dielectric layer 201, to make contact hole.
Because polycrystalline silicon material has light tight character, is difficult to carry out self-registered technology, therefore to carry out first a step KV lithography step in order to remove light non-transmittable layers, thereby realize self-registered technology.This KV lithography step is optional, on the basis that alignment precision and the alignment ability of board improves gradually, also can save this step.
Then, spin coating one bottom antireflective coating (BARC) 203 on hard mask layer 202, thickness is approximately 1000 dusts, and the material of the BARC layer that adopts here is organic material, and main component is the polymerization amino acid.The problem of reflection occurs in the light beam that this layer shines when reducing photoetching.Then be with figuratum photoresist layer 204 in bottom antireflective coating 203 coatings.
Then, shown in Fig. 2 B, as mask, etch through hole 205 at bottom antireflective coating 203 and hard mask layer 202 with this photoresist layer 204, etching reaches the surface of dielectric layer 201, so as with the design transfer on the photoresist layer 204 to hard mask layer 202.Then carry out cineration technics, remove photoresist layer 204 and bottom antireflective coating 203.
Next, shown in Fig. 2 C, as mask, utilize the dry etching method with this hard mask layer 202, such as plasma etching, etch contact hole 206 at dielectric layer 201.
Then, shown in Fig. 2 D, in contact hole 206, with mode backfill one deck bottom antireflective coating (BARC) 207 of spin coating, and be higher than the upper surface certain altitude of hard mask layer 202.The gross thickness of bottom antireflective coating 207 is about 5000～15000 dusts for example.The material of described BARC layer is organic material, and main component is the polymerization amino acid.The effect of this bottom antireflective coating is to protect the contact hole 206 that has formed, and prevents from being damaged in the etching process of next removing hard mask layer 202 marginal portion of contact hole 206, causes the critical size of contact hole 206 undesirable., because hard mask layer 202 is that polycrystalline silicon material is made, therefore have conductivity here, and what fill in the contact hole 206 is the metal level of connection function of electrifying, so hard mask layer 202 must be removed with formation connection between the metal level that prevents from forming afterwards with it.
Then, shown in Fig. 2 E, the using plasma lithographic method eat-backs a part of bottom antireflective coating 207, until the upper surface of bottom antireflective coating 207 flushes with the lower surface of hard mask layer 202 or a little more than the latter.
Then, shown in Fig. 2 F, adopt dry etching, for example the plasma etching method is removed polysilicon hard mask layer 202.The source gas of etching adopts CF
4And O
2Mist, CF wherein
4Flow velocity be 300～600sccm, O
2Flow velocity be 400～800sccm, wherein, sccm is under the standard state, namely the flow of 1 atmospheric pressure, 25 degrees centigrade of lower per minutes 1 cubic centimetre (1ml/min).Then, adopt ashing method to remove the bottom antireflective coating 207 that remains in contact hole inside, finish the etching of contact hole 208.
Because the etch rate of polysilicon is slower, the effect that can serve as well hard mask in the process that forms contact hole has guaranteed that the width of the top and bottom of contact hole differs very little.Be easy to get owing to polycrystalline silicon material in addition, cheap, in making the large contact hole of the little degree of depth of critical size, adopt polycrystalline silicon material to do hard mask layer, so that production cost reduces greatly, therefore adopt polycrystalline silicon material to do hard mask layer and can solve a difficult problem of making the large contact hole of the little degree of depth of critical size.The critical size of the contact hole of making according to the present invention and the ratio of the contact hole degree of depth can reach 0.1～0.4.
The flow chart of Fig. 3 shows makes the semiconductor device technology flow chart that improves the heavily stressed trigger layer of process deposits according to the employing of the embodiment of the invention.In step 301, provide a dielectric layer at the front end device layer, on dielectric layer with deposition one deck polysilicon with as hard mask layer.Alternatively, to the figuratum photoresist layer of deposition one deck tool on this hard mask, carry out KV photoetching and KV etching.In step 302, then at polysilicon hard mask layer spin coating one bottom antireflective coating, then be with figuratum photoresist layer in the bottom antireflective coating coating.In step 303, with this photoresist layer as mask, etching bottom antireflective coating and polysilicon hard mask layer, thus with the design transfer of this photoresist layer to hard mask layer.Then carry out cineration technics, remove photoresist layer and bottom antireflective coating.In step 304, as mask, etch contact hole at dielectric layer with this hard mask layer.In step 305, back-filling bottom antireflective coating in contact hole, until the upper surface of bottom antireflective coating is higher than the upper surface of hard mask layer, then eat-back this bottom antireflective coating, the upper surface of bottom antireflective coating is flushed or a little more than the latter with the lower surface of hard mask layer.In step 306, utilize dry etching to remove the polysilicon hard mask layer.In step 307, adopt ashing method to remove the inner residual bottom antireflective coating of contact hole, finish the etching of contact hole.
The polysilicon that adopts in contact hole is made according to aforesaid embodiment manufacturing is that the semiconductor device of hard mask can be applicable in the multiple integrated circuit (IC).For example be memory circuitry according to IC of the present invention, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, such as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or any other circuit devcies.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. method of making the contact hole in the semiconductor device, described method comprises the following steps:
Provide a dielectric layer at the front end device layer;
Deposit one deck polysilicon as hard mask layer at described dielectric layer;
Spin coating the first bottom antireflective coating on described hard mask layer;
Be with figuratum photoresist layer in described the first bottom antireflective coating coating;
With described photoresist layer as mask, described the first bottom antireflective coating of etching and described hard mask layer, thus with the design transfer of described photoresist layer to described hard mask layer;
Remove described photoresist layer and the first bottom antireflective coating;
As mask, etch contact hole at described dielectric layer with described hard mask layer;
Back-filling the second bottom antireflective coating in described contact hole is until the upper surface of the second bottom antireflective coating is higher than the upper surface of described hard mask layer;
Eat-back described the second bottom antireflective coating, the upper surface of described the second bottom antireflective coating is flushed or a little more than the latter with the lower surface of described hard mask layer;
Utilize dry etching to remove described hard mask layer;
Remove the second inner residual bottom antireflective coating of described contact hole.
2. the method for claim 1 is characterized in that, the thickness of described hard mask layer is selected according to the degree of depth and the contact hole diameter of described contact hole.
3. the method for claim 1 is characterized in that, the thickness of described hard mask layer is 500 ~ 3000 dusts.
4. the method for claim 1 is characterized in that, the source gas of the described hard mask layer of described dry etching is CF
4And O
2Mist.
5. method as claimed in claim 4 is characterized in that, described CF
4Flow velocity be 300 ~ 600sccm, O
2Flow velocity be 400 ~ 800sccm.
6. the method for claim 1 is characterized in that, the material of described the first and second bottom antireflective coatings is organic materials, and main component is the polymerization amino acid.
7. the method for claim 1 is characterized in that, the ratio of the critical size of described contact hole and the contact hole degree of depth is 0.1 ~ 0.4.
8. the method for claim 1 is characterized in that, utilizes cineration technics to remove described photoresist layer, described the first and second bottom antireflective coatings.
9. integrated circuit that comprises the semiconductor device of making by the method for claim 1, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and radio circuit.
10. electronic equipment that comprises the semiconductor device of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| KR101944280B1 (en) * | 2011-05-18 | 2019-01-31 | 엘지이노텍 주식회사 | Camera Module |
| CN104217964B (en) * | 2013-06-05 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of conductive plunger |
| CN103646922B (en) * | 2013-11-29 | 2016-06-01 | 上海华力微电子有限公司 | The forming method of through hole or contact hole |
| CN105097662B (en) * | 2014-05-22 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108962726B (en) * | 2017-05-17 | 2022-01-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN116844948A (en) * | 2023-09-01 | 2023-10-03 | 合肥晶合集成电路股份有限公司 | Preparation method of semiconductor device |
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| CN1694237A (en) * | 2004-05-06 | 2005-11-09 | 海力士半导体有限公司 | Method of manufacturing a semiconductor device having a recessed channel region |
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| CN101202228A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Method of protecting plow groove bottom in deep plow groove technics |
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