CN102054695A - Method for improving performance of semiconductor components - Google Patents
Method for improving performance of semiconductor components Download PDFInfo
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- CN102054695A CN102054695A CN2009101980928A CN200910198092A CN102054695A CN 102054695 A CN102054695 A CN 102054695A CN 2009101980928 A CN2009101980928 A CN 2009101980928A CN 200910198092 A CN200910198092 A CN 200910198092A CN 102054695 A CN102054695 A CN 102054695A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 230000008569 process Effects 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims description 53
- 150000002500 ions Chemical class 0.000 claims description 42
- 238000002347 injection Methods 0.000 claims description 28
- 239000007924 injection Substances 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 18
- -1 germanium ion Chemical class 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 2
- 238000002513 implantation Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000035755 proliferation Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention discloses a method for improving the performance of semiconductor components, which comprises the following steps of: forming a gate oxide layer and a polycrystalline silicon layer on a substrate; etching the gate oxide layer and the polycrystalline silicon layer to form a grid electrode; forming first side walls on both sides of the grid electrode; performing a shallow ion implantation process to form a shallow doping source-drain area; forming second side walls on outer sides of the first side walls; performing a pre-amorphous implantation process; performing a deep source/drain area ion implantation process; forming a buffer oxide layer and a high-stress nitride layer on the formed grid area, source area and drain area sequentially; performing a quick thermal annealing process; and removing the high-stress nitride layer and the buffer oxide layer. By the method provided by the invention, the electron mobility can be improved, so the electrical properties of the semiconductor components are improved effectively.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of method that improves the performance of semiconductor components and devices.
Background technology
In the conventional semiconductor manufacturing process, introduced a kind of stress memory technique (SMT, Stress Memorization Technology), after being used for source/drain (S/D) ion implantation step, to bring out the channel region of stress, improve the electrology characteristic of the components and parts of manufacturing whereby in metal oxide semiconductor field effect tube (MOSFET).
In traditional SMT technology, usually adopt deposition stressor layers and S/D annealing process, to bring out stress in substrate, promptly make the polysilicon gate crystallization again that is positioned at stress cap layer (stress capping layer) lower floor, thereby improve the electrical property of N NMOS N-channel MOS N (NMOS) components and parts by the S/D annealing process.Above-mentioned stressor layers will be removed in the subsequent technique reach.
Figure 1A～1E is the schematic diagram of SMT technology of the prior art.Shown in Figure 1A, at first can form gate oxide 2, again deposition one polysilicon layer on gate oxide 2 in substrate 1 deposition; And then to described gate oxide 2 with technologies such as polysilicon layer exposes, etchings, thereby form grid 3; Then, shown in Figure 1B, will form first side wall 4, and then be mask, carry out the shallow ion injection technology, thereby on substrate 1, form shallow doped source drain region 5 with first side wall 4 and grid 3 in the both sides of above-mentioned grid 3; Subsequently, shown in Fig. 1 C, to form second side wall 6 in the outside of first side wall 4 by series of process flow processs such as deposition, photoetching, corrosion, and then be mask with grid 3, first side wall 4 and second side wall 6, and with second side wall, 6 defined windows, carry out the deep/source drain extensions ion and inject, formation source on substrate 1/leakage (S/D) district 7; Moreover, shown in Fig. 1 D, to on formed grid, source and drain region, form buffer oxide layer 8, be used to avoid 9 pairs of above-mentioned formed grids of follow-up formed heavily stressed nitride layer to cause unnecessary destruction, and then on formed buffer oxide layer 8, form heavily stressed nitride layer 9, be used for bringing out the channel region of stress in substrate.After forming above-mentioned heavily stressed nitride layer 9, can carry out rapid thermal annealing (RTA) technology, thereby make the horizontal proliferation of shallow ion injection region, and repair lattice impaired when carrying out shallow ion injection technology and deep/source drain extensions ion implantation technology, and make the ion distribution of being injected more even.At last, shown in Fig. 1 E, remove above-mentioned heavily stressed nitride layer 9 and buffering oxide layer 8, finish whole SMT technology.
As from the foregoing, though traditional SMT technology can be improved the performance of components and parts by the mode that imposes stress, but be to use the electron mobility in traditional formed semiconductor components and devices of SMT technology relatively still lower, so the electric property of semiconductor components and devices is still waiting to improve.
Summary of the invention
In view of this, the invention provides a kind of method that improves the performance of semiconductor components and devices, thereby improve the electric property of semiconductor components and devices effectively.
According to above-mentioned purpose, technical scheme of the present invention is achieved in that
A kind of method that improves the performance of semiconductor components and devices, this method comprises:
On substrate, form gate oxide and polysilicon layer successively; Described gate oxide and polysilicon layer are carried out etching, form grid;
Form first side wall in the both sides of described grid; Carry out the shallow ion injection technology, to form shallow doped source drain region;
Form second side wall in the outside of above-mentioned first side wall;
Carry out pre-amorphous injection technology;
Carry out the deep/source drain extensions ion implantation technology;
On formed grid, source and drain region, form buffer oxide layer and heavily stressed nitride layer successively;
Carry out rapid thermal anneal process; Remove above-mentioned heavily stressed nitride layer and buffering oxide layer.
In described pre-amorphous injection technology, employed ion is a germanium ion.
The energy of described germanium ion is: 10～30Kev;
The dosage of described germanium ion is: 3 * 10
14～2 * 10
15/ cm
2
In described deep/source drain extensions ion implantation technology, employed ion is phosphonium ion or arsenic ion.
In described deep/source drain extensions ion implantation technology, the energy of ions of being injected is: 1～30Kev; The dosage of the ion that is injected is: 5 * 10
13～3 * 10
15/ cm
2
The thickness of described buffer oxide layer is: 10～1000 dusts.
Described heavily stressed nitride layer is by Si
3N
4Constitute;
The thickness of described heavily stressed nitride layer is: 100～10000 dusts.
When carrying out described rapid thermal anneal process, employed annealing temperature is: 900～1100 degrees centigrade.
As from the foregoing, the invention provides a kind of method that improves the performance of semiconductor components and devices, because in the method, before forming heavily stressed nitride layer, carried out pre-amorphous injection technology earlier, because above-mentioned pre-amorphous injection technology will make the decrystallized more remarkable of gate polysilicon layer, thereby through can more effectively keeping the stress of the heavily stressed nitride layer that is deposited after the follow-up high-temperature quick thermal annealing technology, in raceway groove, cause bigger deformation, more electron mobility has been improved on the highland, thereby has improved the electric property of semiconductor components and devices effectively.
Description of drawings
Figure 1A～1E is the schematic diagram of SMT technology of the prior art.
Fig. 2 is the flow chart of the method for the performance of raising semiconductor components and devices among the present invention.
Fig. 3 A～3F is the schematic diagram of the method for the performance of the raising semiconductor components and devices among the present invention.
Embodiment
In order to make the purpose, technical solutions and advantages of the present invention clearer, below lift specific embodiment and, the present invention is described in more detail with reference to accompanying drawing.
The invention provides a kind of method that improves the performance of semiconductor components and devices, in the method, because before forming heavily stressed nitride layer, use germanium ion to carry out pre-amorphous injection technology earlier, because above-mentioned pre-amorphous injection technology will make the decrystallized more remarkable of gate polysilicon layer, thereby through can more effectively keeping the stress of the heavily stressed nitride layer that is deposited after the follow-up high-temperature quick thermal annealing technology, in raceway groove, cause bigger deformation, more electron mobility has been improved on the highland, thereby has improved the electric property of semiconductor components and devices (particularly NMOS) effectively.
Fig. 2 is the flow chart of the method for the performance of raising semiconductor components and devices among the present invention.Fig. 3 A～3F is the schematic diagram of the method for the performance of the raising semiconductor components and devices among the present invention.In conjunction with Fig. 2, shown in Figure 3, the method for the performance of the raising semiconductor components and devices that is provided among the present invention comprises step as described below:
Step 201 forms gate oxide and polysilicon layer successively on substrate; Described gate oxide and polysilicon layer are carried out etching, form grid.
As shown in Figure 3A, in this step, at first deposition formation gate oxide 2 on substrate 1 deposits a polysilicon layer again on gate oxide 2.Wherein, gate oxide 2 generally is made of silicon dioxide and a spot of nitrogen element.
Then, will expose to above-mentioned polysilicon layer and gate oxide 2, technology such as etching, thereby form grid 3.
In this step, can use deposition process commonly used in this area to carry out the deposition of above-mentioned gate oxide and polysilicon layer, and technologies such as commonly used exposure in use this area, etching form required grid 3, and the concrete deposition gate oxide and the method for polysilicon layer and the specific implementation that forms grid do not repeat them here.
Step 202 forms first side wall in the both sides of described grid; Carry out the shallow ion injection technology, to form shallow doped source and drain (LDD, Lightly Doped Drain) district.
Shown in Fig. 3 B, in this step, first side wall 4 will be formed in the both sides of grid 3 at first.The purpose of this first side wall 4 that forms is to reserve certain distance into the shallow ion injection region horizontal proliferation in follow-up rapid thermal annealing (RTA) technology, thereby the raceway groove of guaranteeing grid 3 belows has certain width, with the short-channel effect of avoiding follow-up shallow ion injection technology to be brought, cause channel length to diminish and the situation that punch-through and leakage current increase occurs.Wherein, described first side wall 4 is generally by silicon dioxide (SiO
2) constitute, and the thickness of described first side wall 4 is generally 50～200 dusts
Then, will be mask with first side wall 4 and grid 3, carry out the shallow ion injection technology, thereby on substrate 1, form shallow doped source drain region 5.
In addition, can use the method for formation side wall commonly used in this area to form described first side wall 4, and can use ion injection method commonly used in this area to carry out above-mentioned shallow ion injection technology.Therefore, the specific implementation of the method for above-mentioned formation first side wall and shallow ion injection technology does not repeat them here.
Step 203 forms second side wall in the outside of above-mentioned first side wall.
Shown in Fig. 3 C, in this step, will form second side wall 6 in the outside of first side wall 4 by series of process flow processs such as deposition, photoetching, corrosion.Wherein, described second side wall 6 mainly by silicon dioxide (SiO
2)/silicon nitride (Si
3N
4) dielectric film combines; And the thickness of described second side wall 6 is generally
In addition, in this step, can use side wall formation method commonly used in this area to form the second above-mentioned side wall 6, therefore, concrete implementation does not repeat them here.
Step 204 is carried out pre-amorphous injection (Pre-amorphization Implantation) technology.
Shown in Fig. 3 C, in this step, to carry out pre-amorphous injection technology, so that the gate polysilicon layer is decrystallized more remarkable, thereby through can more effectively keeping the stress of the heavily stressed nitride layer that is deposited after the follow-up high-temperature quick thermal annealing technology, cause bigger deformation in raceway groove, more electron mobility is improved on the highland, thereby has improved the electric property of semiconductor components and devices effectively.
In an embodiment of the present invention, in above-mentioned pre-amorphous injection technology, employed ion is germanium (Ge) ion, and described Ge energy of ions is: 10～30Kev, the dosage of described Ge ion is: 3 * 10
14～2 * 10
15Individual/square centimeter (is abbreviated as "/cm with unit " individual/square centimeter " usually
2").Preferable, employed Ge energy of ions can be 10Kev, 15Kev, 20Kev, 25Kev or 30Kev etc., the dosage of employed Ge ion can for: 3 * 10
14/ cm
2, 5 * 10
14/ cm
2, 10
15/ cm
2, 1.5 * 10
15/ cm
2Or 2 * 10
15/ cm
2Deng.
Step 205 is carried out the deep/source drain extensions ion implantation technology.
Shown in Fig. 3 D, in this step, will be mask, and, carry out the deep/source drain extensions ion and inject, formation source on substrate 1/leakage (S/D) district 7 with second side wall, 6 defined windows with grid 3, first side wall 4 and second side wall 6.
In an embodiment of the present invention, in above-mentioned deep/source drain extensions ion implantation technology, employed ion is P (phosphorus) ion or arsenic (As) ion, and the energy of ions of being injected is: 1～30Kev, the dosage of the ion that is injected is: 5 * 10
13～3 * 10
15/ cm
2Preferable, the energy of ions of being injected can be 1Kev, 10Kev, 20Kev or 30Kev etc., the dosage of the ion that is injected can for: 5 * 10
13/ cm
2, 10
14/ cm
2, 5 * 10
14/ cm
2, 10
15/ cm
2Or 3 * 10
15/ cm
2Deng.
In this step, can use deep/source drain extensions ion injection method commonly used in this area to form above-mentioned formation source/leakage (S/D) district 7, therefore, concrete implementation does not repeat them here.
Step 206 forms buffer oxide layer and heavily stressed nitride layer successively on formed grid, source and drain region.
Shown in Fig. 3 E, in this step, at first will carry out the buffer oxide layer growth technique, promptly on formed grid, source and drain region, form buffer oxide layer, this buffer oxide layer is the barrier layer of removing the heavily stressed nitride layer that forms subsequently in the subsequent technique, can be used for also preventing that follow-up formed heavily stressed nitride layer from causing unnecessary destruction to above-mentioned formed grid simultaneously.Wherein, the thickness of formed buffer oxide layer is generally:
Then, carry out heavily stressed nitride layer growth technique again, promptly form heavily stressed nitride layer on formed buffer oxide layer, this heavily stressed nitride layer is generally by Si
3N
4Constitute, be used for bringing out the channel region of stress, thereby improve the electric property of semiconductor components and devices in substrate.Wherein, the thickness of formed heavily stressed nitride layer is generally:
And owing to the stress intensity that this heavily stressed nitride layer produced is generally: 0.5～1.5 gigapascal (GPa).
Step 207 is carried out rapid thermal anneal process.
After forming above-mentioned heavily stressed nitride layer, can (for example carry out rapid thermal anneal process, laser annealing technique etc.), thereby make the horizontal proliferation of shallow ion injection region, and repair lattice impaired when carrying out shallow ion injection technology and deep/source drain extensions ion implantation technology, and make the ion distribution of being injected more even.Simultaneously, above-mentioned rapid thermal anneal process can make the gate polysilicon layer after the pre-amorphous injection technology of above-mentioned process produce crystallization again.This crystallization again will retain effectively by the formed stress of above-mentioned formed heavily stressed nitride layer, after making that even above-mentioned heavily stressed nitride layer is removed, still can keep corresponding stress in the polysilicon layer, thereby in raceway groove, cause deformation, improve the electron mobility in the semiconductor components and devices, improve the electric property of semiconductor components and devices.
Wherein, when carrying out above-mentioned rapid thermal anneal process, employed annealing temperature is generally: 900～1100 degrees centigrade (℃).
In this step, can use rapid thermal annealing method commonly used in this area to carry out above-mentioned thermal anneal process, therefore, concrete implementation does not repeat them here.
Step 208 is removed above-mentioned heavily stressed nitride layer and buffering oxide layer.
Shown in Fig. 3 F, in this step, will at first remove above-mentioned heavily stressed nitride layer by removal technology (for example, dry method or wet-etching technology etc.) commonly used, and then use removal technology (for example, dry method or wet-etching technology etc.) commonly used to remove above-mentioned buffer oxide layer.Concrete implementation does not repeat them here.
By above-mentioned step 201～208, finally can form required semiconductor components and devices.In above-mentioned step, because before forming heavily stressed nitride layer, use the Ge ion to carry out pre-amorphous injection technology earlier, thereby the ion that has reduced in the follow-up ion implantation process injects the degree of depth, suppressed the generation of channeling effect effectively, improve electron mobility, thereby improved the performance of semiconductor components and devices (particularly NMOS) effectively.According to actual experiment as can be known, after the method for the performance of the raising semiconductor components and devices of stating in the use, electron mobility in the formed semiconductor components and devices has improved about 10%, therefore the electric property (for example, saturation current Idsat, cut-off leakage current IOFF etc.) of formed semiconductor components and devices has also improved about 4%.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a method that improves the performance of semiconductor components and devices is characterized in that, this method comprises:
On substrate, form gate oxide and polysilicon layer successively; Described gate oxide and polysilicon layer are carried out etching, form grid;
Form first side wall in the both sides of described grid; Carry out the shallow ion injection technology, to form shallow doped source drain region;
Form second side wall in the outside of above-mentioned first side wall;
Carry out pre-amorphous injection technology;
Carry out the deep/source drain extensions ion implantation technology;
On formed grid, source and drain region, form buffer oxide layer and heavily stressed nitride layer successively;
Carry out rapid thermal anneal process; Remove above-mentioned heavily stressed nitride layer and buffering oxide layer.
2. method according to claim 1 is characterized in that:
In described pre-amorphous injection technology, employed ion is a germanium ion.
3. method according to claim 2 is characterized in that:
The energy of described germanium ion is: 10～30Kev;
The dosage of described germanium ion is: 3 * 10
14～2 * 10
15/ cm
2
4. method according to claim 1 is characterized in that:
In described deep/source drain extensions ion implantation technology, employed ion is phosphonium ion or arsenic ion.
5. method according to claim 1 is characterized in that:
In described deep/source drain extensions ion implantation technology, the energy of ions of being injected is: 1～30Kev; The dosage of the ion that is injected is: 5 * 10
13～3 * 10
15/ cm
2
6. method according to claim 1 is characterized in that:
The thickness of described buffer oxide layer is: 10～1000 dusts.
7. method according to claim 1 is characterized in that:
Described heavily stressed nitride layer is by Si
3N
4Constitute;
The thickness of described heavily stressed nitride layer is: 100～10000 dusts.
8. method according to claim 1 is characterized in that:
When carrying out described rapid thermal anneal process, employed annealing temperature is: 900～1100 degrees centigrade.
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| CN103489781A (en) * | 2012-06-13 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device by utilizing stress memory technology |
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| CN106158657A (en) * | 2015-04-20 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The forming method of MOS transistor |
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