CN102054462A - Low power consumption display control method and relevant display controller - Google Patents

Abstract

The present invention is a display control method with low power consumption and a related display controller. The display control method with low power consumption is used for a display controller, including: detecting a sensing signal to generate a sensing result; generating a sensing result according to the sensing result The control signal is used to control a power conversion controller to operate in a power-saving mode with low power consumption; when a wake-up event occurs, the control signal is released and the relevant power-consuming circuits in the display controller are disabled; finally, the display controller is woken up Return to normal operating mode.

Description

Low power consumption display control method and related display controller

technical field

The present invention relates to a display control method and a related display controller, in particular to a low power consumption display control method and a related display controller.

Background technique

Fig. 1 shows the display circuit block diagram 100 inside the display of the prior art, including a power supply circuit 110, a scaling controller 120 and a backlight assembly 130, the power supply circuit 110 is converted into appropriate voltages 114, 116 by an AC power supply 112, and respectively supplies power to Operation of the backlight unit 130 and the zoom controller 120 . The display circuit block diagram 100 can be applied to a computer monitor, an analog TV or a digital TV. In the world trend of energy saving and carbon reduction, many manufacturers are committed to saving the power consumption of the display in the standby state. The prior art utilizes an AC/DC conversion power supply circuit 110 to save power.

Therefore, there is an urgent need to develop a set of low-power display controllers and related methods that can be realized at low cost.

Contents of the invention

The object of the present invention is to provide a low-power consumption display controller and a related method that can be realized at low cost.

The present invention proposes a display controller, including a voltage detection circuit, a low power consumption control circuit, a power management unit, a selector, a microcontroller, and a crystal input/output circuit; the voltage detection circuit detects a voltage level of a sensing signal; The power consumption control circuit is coupled to the voltage detection circuit to generate a first control signal according to the voltage level. The voltage detection circuit can be an analog-to-digital converter or a comparator; the power management unit is used to receive a wake-up event and generate a second control signal. The control signal is in response to the wake-up event; the selector is coupled to the low power consumption control circuit and the power management unit, and is used to alternatively output the first control signal and the second control signal to control a power conversion controller to perform low power consumption. The selector can be a multiplexer for power-saving power-saving mode operation or normal operation mode operation. When the selector outputs the second control signal, the power management unit disables the low power consumption control circuit, microcontroller, crystal input and output circuits and digital video interface (DVI (Digital Visual Interface)) / high-definition multimedia audio-visual interface (HDMI (High-Definition Multimedia Interface)) clock amplifier to reduce possible power consumption.

The present invention also proposes a low power consumption display control method for a display controller, including: detecting a sensing signal to generate a sensing result, for example, converting the sensing signal by analog to digital to generate a sensing result , or, by comparing the sensing signal with a predetermined voltage level to generate a sensing result; generating a control signal according to the sensing result, for example, using a general-purpose input and output pin to generate a control signal to control a power conversion control The device operates in a power-saving mode with low power consumption; when a wake-up event occurs, the control signal is asserted and the related power-consuming circuits in the display controller are disabled. For example, the microcontroller, crystal input and output circuits, and DVI/HDMI clock amplifier; finally, wakes up the display controller to return to normal operating mode.

Description of drawings

In order to enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the accompanying drawings are for reference and illustration only, and are not intended to limit the present invention, wherein:

FIG. 1 shows a block diagram of a display circuit inside a display in the prior art.

FIG. 2 shows an ultra-low power consumption display control circuit according to an embodiment of the present invention.

FIG. 3 shows the main waveforms related to the embodiment of FIG. 2 .

FIG. 4 shows an ultra-low power consumption display control circuit according to another embodiment of the present invention.

FIG. 5 shows an ultra-low power consumption display control circuit according to another embodiment of the present invention.

FIG. 6 shows an ultra-low power consumption display control circuit according to another embodiment of the present invention.

FIG. 7 shows a flow chart of a method for controlling an ultra-low power consumption display according to an embodiment of the present invention.

FIG. 8 shows a very low power consumption power conversion controller according to an embodiment of the present invention.

FIG. 9 shows the main signal waveform diagram of the ultra-low power consumption power conversion control operation in FIG. 8 .

FIG. 10 shows a flowchart of a power conversion method with extremely low power consumption according to an embodiment of the present invention.

FIG. 11 shows a display controller according to an embodiment of the present invention.

FIG. 12 shows a waveform diagram of the sensing signal VCC5Vsense according to an embodiment of the present invention.

FIG. 13 shows a flowchart of a method for controlling low power consumption display according to an embodiment of the present invention.

Detailed ways

2 shows an extremely low power consumption display control circuit 300 according to a specific embodiment of the present invention. An AC power supply 302 supplies an AC voltage to a rectifier 310, such as an AC voltage of 80 to 220 volts; the rectifier 310 rectifies and outputs a DC voltage to a bias circuit 320. With a transformer (transformer) 330, for example, a DC voltage of 120 to 375 volts, and a rectifier 310, for example, a full-bridge rectifier; biased by a bias circuit 320, the DC voltage signal VDDp is supplied to the power conversion controller 340 for operation, and the DC voltage signal VDDp For example, if the DC voltage is 20V, the power conversion controller 340 is an analog circuit chip, usually packaged with eight pins, and the number of pins is limited due to cost considerations. Transformer 330 uses coil induction to convert its primary high-voltage voltage into other appropriate voltages for secondary output, through diodes D4, D5 and capacitors C2, C3 for the operation of other circuits, such as output DC voltage signals VCC14V and VCC5V, respectively provide 14 DC voltage of 5V and 5V, and DC voltage of 14V can supply the operation of the backlight components, such as the operation of the backlight components of CCFLs or LEDs. The DC voltage signal VCC5V passes through the regulator 350 , such as a low drop-out regulator (LDO for short) 350 , and outputs the DC voltage signal VDD3V3 to supply power to the operation of the scaling controller 360 . The scaling controller 360 controls the operation of the power conversion controller 340 according to the voltage status of the DC voltage signal VCC5V output from the secondary side of the transformer 330. For example, the scaling controller 360 sends the voltage division signal VCC5Vsense of the DC voltage signal VCC5V through the resistors R5 and R6 to the scaling The successive approximation register analog-to-digital converter (successive approximation ADC, referred to as SAR ADC) of the controller 360 detects the voltage condition on the DC voltage signal VCC5V. Those who are familiar with this technology can understand that the progressive approximation register analog-to-digital converter is a low-speed low-cost achievable The analog-to-digital converter, or, sends the divided voltage signal VCC5Vsense to a comparator (not shown) of the scaling controller 360 and a reference voltage, such as 4 volts, to detect the voltage condition on the DC voltage signal VCC5V; then, the scaling control The controller 360 can use the general purpose I/O (GPIO for short) pin to control the compensation pin COMP of the power conversion controller 340 through the opto-coupler (or called photocoupler) 370, and feedback control power conversion control The opening and operating timing of the device 340 is controlled to achieve the purpose of extremely low power consumption. It should be noted that those skilled in the art can understand that the power conversion controller 340 is an analog circuit chip, usually packaged into eight pins, wherein the compensation pin COMP provides a current source 342 inside the power conversion controller 340, for example, a 200 micron Current source in amperes (µA). The bias circuit 320 includes resistors R11, R12, R13, diodes D21, D22, transistors Q1, Q2, Q3. The bias circuit 320 utilizes the path of the resistors R11, R12 and the transistor Q1 to bias the high-voltage DC voltage into a DC voltage signal VDDP to supply power to the power conversion controller 340 for operation.

The power conversion controller 340 utilizes the charge stored in the capacitor C1 to temporarily supply the operation of the power conversion controller 340 when the transistor Q1 is turned off and the power supply stops. It takes time to actually start supplying normal DC voltage, so the capacitor C1 should not be too large, for example, 22 microfarads (μF). The scaling controller 360 can use the capacitor C2 to temporarily supply the operation of the scaling controller 360 when the power is cut off. Typically, the capacitor C2 is quite large, such as 2000 microfarads (μF). It should be noted that the capacitor C2 can provide The stored power is much larger than that of the capacitor C1.

The ultra-low power consumption display control circuit 300 shown in FIG. 2 uses the capacitor C2 to temporarily supply power to the operation of the zoom controller 360 after the system power is turned off, and outputs a DC voltage signal VDD3V3 through the regulator 350 to supply power to the zoom controller. The operation of the controller 360, as long as the DC voltage signal VCC5V is stabilized by the voltage regulator 350 and the output DC voltage signal VDD3V3 is higher than the working voltage of the scaling controller 360, the scaling controller 360 can be operated, and the power consumption of the voltage regulator 350 The power is extremely low, and the voltage drop LDODrop between the DC voltage signal VCC5V and the DC voltage signal VDD3V3 is extremely small. Assuming that the working voltage of the scaling controller 360 is 3.3V, through the gradual discharge of the capacitor C2, as long as the DC voltage signal VCC5V exceeds (3.3V+LDODrop), the scaling controller 360 can operate.

After the system power is turned off, the scaling controller 360 uses the GPIO pin to send the signal AC OFF to reflect the voltage state of the scaling controller 360 to the power conversion controller 340 through the resistor R4 and the optical coupling component 370 to draw current, and the power conversion control The device 340 uses the compensation pin COMP to make the current source 342 supply the current through the resistor R13, the diodes D21, D22 and the transistor Q3. For example, the current transfer ratio (CTR) of the optical coupling device 370 is 1: 1, the current drawn by both sides of the optical coupling component 370 is 1:1, and the assertion period of the signal AC_OFF is related to the level of the DC voltage signal VCC5V. When the power conversion controller 340 senses that the voltage of the scaling controller 360 at the compensation pin COMP is lower than a predetermined level, it briefly drives the signal DRV to turn on the transistor Q4, and briefly starts the primary side of the transformer 330 to draw external power to the capacitor C1. charging and charging the secondary bulk capacitor C2 of the transformer 330 for the operation of the scaling controller 360 during the next cycle. The directions of the arrows in FIG. 2 indicate the main current flows in several circuit analyzes so that those skilled in the art can better understand the operation of this embodiment.

For the power conversion controller 340, when the signal AC_OFF is asserted, for example, at a high level, the optical coupling component 370 generates a coupling current, and draws the required coupling current through the node A, diodes D21, D22 and the optical coupling component 370, so that the transistor Q3 The base voltage of the transistor Q3 drops, and the transistor Q3 and the diodes D21 and D22 are turned on, so that the voltage on the compensation pin COMP drops, and the transistor Q2 is turned off, so that the base potential of the transistor Q1 drops and the transistor Q1 is turned off; the transistor Q3 has the function of current amplification, The discharge speed of the current source 342 can be accelerated. If the current capability of the current source 342 in the power conversion controller 340 is low, the transistor Q3 can be omitted and the diode D22 can be directly used for discharging. On the other hand, when the signal AC_OFF is released, for example, it is at a low level, no induction current is generated, the transistor Q1 is turned on to charge the capacitor C1, and then the voltage on the compensation pin COMP gradually rises, and the transistor Q2 is turned on, so that the transistor Q1 The base of the transistor Q1 is grounded and the transistor Q1 is turned off, so that the power conversion controller 340 uses the power stored in the capacitor C1 to discharge the capacitor C1; Capacitor C1 charges and discharges cycle operation.

FIG. 3 shows the main waveforms of the ultra-low power consumption display control circuit 300 shown in FIG. 2 , including the relationship between the waveforms of the signal AC_OFF, the voltage signal VDDp, the signal DRV, the voltage signal VCC5V, and the sensing signal VCC5Vsense. In this embodiment, after the signal AC_OFF is pulled high, the current source 342 in the power conversion controller 340 is quickly forced through the diodes D21, D22 and the optical coupling component 370. Discharging pulls down the potential and turns off the transistor Q1, forcibly cutting off the power supply from the external power supply to the power conversion controller 340, and the voltage signal VDDp is quickly pulled down and kept at 0 volts for a long time to achieve the purpose of power saving. After the signal AC_OFF is pulled low, the transistor Q1 is turned on to charge the capacitor C1, so that the voltage signal VDDp rises rapidly. After reaching the highest voltage, such as 20 volts, the voltage on the compensation pin COMP rises to a predetermined level, and the power conversion controller 340 briefly The signal DRV is asserted, for example, the pulse width modulation (Pulse Width Modulation, PWM) controller in the power conversion controller 340 briefly generates the signal DRV with high and low level width modulation, or the pulse frequency modulation (pulse frequency modulation, The PFM for short) controller generates signals DRV with different frequencies, and briefly turns on the transistor Q4, so that the primary of the transformer 330 is temporarily turned on to charge the capacitor C1 and the secondary large capacitor C2, for example, the voltage signal VCC5V is quickly pulled up To 5 volts, it can be achieved by comparing with a comparator and a reference voltage, or, for example, charging the secondary large capacitor C2 for a predetermined period; as long as the voltage signal VCC5V is discharged to the predetermined voltage, the scaling controller 360 can be normal The operation monitors the change of the sensing signal VCC5Vsense, so as to continuously operate in a cycle. For example, as long as the voltage signal VCC5V is greater than (3.3 volts + voltage drop LDODrop) during the whole process, it can operate normally. The sensing signal VCC5Vsense displays the charging and discharging changes of the corresponding voltage signal VCC5V. It should be noted that the voltage signal VDDp is maintained at 0 volts for a long period of time, so that the driving period of the signal DRV is far apart, which can completely isolate the consumption of the external power supply and achieve the purpose of extremely low power consumption. After circuit simulation, the total power The power consumption can be less than 150 milliwatts (mW), and the actual additional cost is very low, taking into account both cost and performance. Operations of other auxiliary components in this embodiment, such as the fuse F1, the negative temperature coefficient resistor NTC, the resistor R2, the capacitor C4, etc., can be understood by those skilled in the art and will not be repeated here.

FIG. 4 shows an extremely low power consumption display control circuit 400 according to another specific embodiment of the present invention. Compared with the embodiment in FIG. 2 , the difference is that the bias voltage circuit 420 uses the resistor R18 to provide bias voltage control, and the transistor Q3 is omitted. , and the far right shows that the 5-volt signal PC5V from the personal computer can be coupled to the voltage signal VCC5V through the diode D6 to charge the capacitor C2; For analog TV and digital TV, it does not escape the scope of the present invention.

FIG. 5 shows an ultra-low power consumption display control circuit 500 according to another embodiment of the present invention, which is mainly derived from the concept of the embodiment in FIG. 2 . Similar signals also use the labels of the previous signals, which is helpful for understanding the operation of this embodiment. The main difference is that the power conversion controller 540 integrates similar elements of the bias circuit 320 in FIG. The controller 560 can detect the change of the voltage signal VCC5V. For example, before the voltage signal VCC5V is higher than 3.3 volts, the display controller 560 can use the GPIO pin to assert the signal AC_OFF to stop the power conversion controller 540 from drawing external power through the optical coupling component 570 and the compensation pin COMP; Before the signal VDD3V3 drops to 3.3 volts, the display controller 560 asserts the signal AC_OFF, and the power conversion controller 540 briefly draws the external power from the node B through the high-voltage power supply pin HV by turning on the internal switch (not shown), so that the power The controlled current source 542 inside the conversion controller 540 charges the capacitor C1 through the voltage signal VDDp', and briefly drives the signal DRV to start the primary of the transformer 530, so that the transformer 530 charges the capacitor C1 through the diode D5 and the secondary large The capacitor C2 is charged to a predetermined voltage or charged for a predetermined period, that is, the voltage conversion device 531 includes a transformer 530 and diodes D4 and D5 to provide a DC voltage output. The power conversion controller 540 cuts off the external power supply for a long time, which can greatly reduce the power consumption. The directions of the arrows indicate the main current flow directions in several circuit analysis, so that those skilled in the art can better understand the operation of this embodiment.

According to the above disclosure of many embodiments, those skilled in the art can make many possible changes without departing from the scope of the present invention. For example, the display controller 560 utilizes the GPIO pin control signal AC_OFF to feedback control the compensation pin COMP through the resistor R4 and the optical coupling component 570 to control whether the power conversion controller 540 draws external power, and there may be other changes. For example, the circuit near the optical coupling component 570 can be modified so that the high and low levels of the signal AC_OFF are opposite to the operation of the power conversion controller 540; or, with an auxiliary circuit, the GPIO pin can indirectly control the current drawn by the optical coupling component 570 Or, in many of the above embodiments, the level of the control signal AC_OFF is output by the GPIO pin. By modifying the circuit near the optical coupling component 570, the GPIO pin can be operated as an input mode. As shown in Figure 6, the optical coupling The component 570 is coupled to the GPIO pin of the display controller 560 through the resistor R72, and controls whether the discharge is turned on through the transistor Q8. When the control signal CTRL is asserted, the transistor Q8 is turned on, and the signal COMP triggers the power conversion controller 540 to implement similarly to the above. example operation.

FIG. 7 shows a flow chart of a method for controlling an ultra-low power consumption display according to an embodiment of the present invention. In step 702, the DC voltage level of the transformer secondary is sensed. For example, the change of the signal VCC5V in FIG. 2 can be sensed, or the change of the signal VDD3V3 can be directly sensed. In step 704, the display controller turns on the optocoupler through the GPIO pin, controls the compensation pin of the power conversion controller, and turns off the operation of the power conversion controller. For example, as shown in Figure 5, the display control The device 560 can increase the magnitude of the coupling current of the optical coupling component 570 through the GPIO pin assertion signal AC_OFF, and shut down the operation of the power conversion controller 540, or, as shown in FIG. 6 , the optical coupling component 570 is coupled to the display controller 560 GPIO pins, forming a discharge path through the transistor Q8, and shutting down the operation of the power conversion controller 540; in step 706, when the DC voltage level drops to a predetermined level, reduce the coupling current of the optical coupling component through the GPIO pins size, control the compensation pin of the power conversion controller, and start the operation of the power conversion controller; in step 708, briefly turn on the primary of the transformer, and briefly charge the first capacitor and the second capacitor, for example, as shown in Figure 5 As shown, the gate of the transistor Q4 is controlled by pulse width modulation or pulse frequency modulation, so that the transformer 530 charges the first capacitor C1 and the secondary second capacitor C2.

FIG. 8 shows a very low power consumption power conversion controller 800 according to a specific embodiment of the present invention, which has pins such as HV, VDDp, DRV, CS, COMP, and GND. When applied to the operation of the embodiment in FIG. 5, FIG. 8 The operation of the external circuit of each pin is as described in the foregoing embodiments. Very low power consumption power conversion controller 800 includes comparators 810, 820, hysteresis comparator 830, oscillator 840, current source 842, voltage regulator 850, flip-flop 860, AND gates 870, 872, buffer 880, control circuit 890, resistors R80, R82, all-sodium diode D80.

FIG. 9 shows the main signal waveform diagram of the operation of the ultra-low power consumption power conversion controller 800 in FIG. Represents the voltage signal of the VDDp pin, the voltage signal of the COMP pin, the current magnitude of the HV pin, the current magnitude of the VDDp pin, the voltage signal of the DRV pin, and the 5V voltage signal. When the power conversion controller 800 is first started, the HV pin charges the capacitor (not shown) outside the VDDp pin through the current source 842. When the potential gradually rises to the point where the input voltage of the positive terminal of the hysteresis comparator 830 is higher than the first hysteresis The reference voltage VDDH, the output level of the hysteresis comparator 830 is high, so that the output of the AND gate 870 is high, enabling the voltage regulator 850 to output the operating voltage in the signal 852 to supply the internal operation of the power conversion controller 800; and, the hysteresis comparator The output high level of the device 830 passes through the OR gate 892 and the inverter 894, the current source 842 is turned off, and the HV pin stops drawing current from the outside. A high level will turn off the current source 842 to block external power consumption. The oscillator 840 generates a square wave signal and outputs it to the S input terminal of the SR flip-flop 860, while the R input terminal of the SR flip-flop 860 is at a low level at first, and the Q output terminal turns to a high level, when the DRV pin is pulled High level, the externally connected transistor (not shown) will be turned on, and the current sense (CS) pin will be pulled high accordingly. After the comparator 810, the R input terminal of the SR flip-flop 860 will be When the SR flip-flop 860 receives a trigger next time, the S input terminal and the R input terminal of the R flip-flop 860 are respectively low level and high level. After the trigger, the Q output terminal turns to low level , That is to say, the operation of this circuit, the input of the S input terminal and the R input terminal are both inverting when triggered, so as to generate a pulse width modulation signal on the DRV pin. For example, the square wave signal is a 1MHz square wave signal to reduce the power consumption of the ultra-low power consumption power conversion controller 800 in standby mode, and the square wave signal is output on the DRV pin through the AND gate 872 and the buffer 880 . Then, the capacitor (not shown) outside the VDDp pin slowly releases the stored power until the positive terminal input voltage of the hysteresis comparator 830 reaches the second hysteresis reference voltage VDDL, so that the output level of the hysteresis comparator 830 is changed by High to low, so that the output of the AND gate 870 is low, the output of the AND gate 872 is low, the output of the DRV pin is low, and the external transistor (not shown) connected to it is turned off and the external transformer (not shown) is turned off. ) primary, as shown in Figure 9, the I(HV) signal draws the charging current Icharge at the beginning, and when V(VDDP) changes from the voltage VDDH to the voltage VDDL, the I(HV) signal (from the external power supply) consumes a current that suddenly drops to Ihv_off . The current released by I(VDDp) is Istartup and Iop, and the current Iop supplies the power conversion controller 800 to drive the square wave signal on the DRV pin.

Then, after the primary of the external transformer is turned on, the secondary display controller (not shown) can obtain power to operate, and can control the V(COMP) signal. Through the control of the COMP pin disclosed in the above-mentioned embodiments, by controlling the compensation signal on the COMP pin, the time interval for generating the pulse width modulation signal can be lengthened, and the actual time length of the generation can be shortened, but the power conversion controller is still The 800 operates in a fully monitored manner, so that the entire system will not be out of control and unable to wake up.

When the voltage of the V(COMP) signal is pulled low, the operation of the oscillator 840 is forcibly turned off, or the output frequency of the oscillator 840 is adjusted in response to the potential level of the V(COMP) signal. For example, V(COMP ) signal, the output frequency becomes higher when the potential of the V(COMP) signal is lower, or the reverse operation, so the potential of the V(COMP) signal can affect the power consumption of the power conversion controller 800 and the control comparator 820 compares the positive terminal voltage with the feedback reference voltage Voff, and outputs a low level to the feedback control signal 822, so that the output of the AND gate 870 is at a low level, disabling the operation of the voltage regulator 850, and turning off The internal power supply of the power conversion controller 800 makes the power conversion controller 800 enter the extremely low power consumption mode, and the current I(VDDp) is instantly reduced to Ioff, preferably the current Ioff is less than the current 0.1*Iop, or lower, V( The falling speed of VDDP) potential becomes very slow, that is, the falling slope of V(VDDP) potential becomes smaller, and by controlling the V(COMP) signal, the time to start charging the external capacitor next time can be greatly lengthened and the power consumption of the entire system can be reduced. It should be noted that pulling down the V(COMP) signal can make the low level output in the feedback control signal 822 pass through the inverter 896 and the OR gate 892 to forcibly turn off the current source 842, and stop the HV pin from drawing current from the outside, because this The output of the hysteresis comparator 830 is at a high level, which has shut down the operation of the current source 842 . That is to say, the simple control circuit 890 including the OR gate 892 and the inverters 894 and 896 can timely control the timing of turning on and off the current source 842 .

Returning to Figure 8, when the action of pulling down the V(COMP) signal is stopped, that is, when the voltage on the COMP pin is controlled to be higher than the feedback reference voltage Voff, the level of the feedback control signal 822 is high, and the current I(VDDp ) is restored to Iop, the external large capacitor (not shown) restores the operating power of the power conversion controller 800 again, and the power conversion controller 800 operates normally until the V(VDDP) voltage is VDDL, at this time, the positive voltage of the hysteresis comparator 830 When the input voltage at terminal reaches the second hysteresis reference voltage VDDL, the output level of the hysteresis comparator 830 changes from high to low, so that the output of the AND gate 870 is low, the output of the AND gate 872 is low, and the output of the DRV pin turns to low level.

Then, after the HV pin temporarily charges the capacitor (not shown) outside the pin VDDp through the current source 842 , the potential of V(VDDp) is charged from VDDL to VDDH, and the current I(VDDp) starts to discharge so that the loop operates. The COMP pin can first pass through the gain amplifier 811, such as a gain adjustment of 1/2. This gain adjustment can be adjusted according to the actual circuit design. After entering the comparison of the comparator 810, it controls the R input terminal of the SR flip-flop 860, 1 Volts (V) are just an example of the range in which the comparator 810 compares voltages. In this embodiment, the comparator 810 compares the CS pin voltage with the COMP voltage and the 1V voltage. Possible circuit changes may be made.

FIG. 10 shows a flow chart of a power conversion method with extremely low power consumption according to an embodiment of the present invention. In step 1020, a current source is turned on for a first predetermined period, for example, the charging reaches the voltage VDDH; in step 1030, enabling A voltage regulator in the power conversion controller reaches a second predetermined period, and generates a driving signal, such as a pulse width modulation signal or a pulse frequency modulation signal, during the second predetermined period; at step 1040, a feedback control signal is asserted, For example, the feedback control signal 822 in FIG. 8 disables the voltage regulator so that the power conversion controller enters a very low power consumption mode. Preferably, the current consumed in the very low power consumption mode is lower than the normal operating current One-tenth of the magnitude, or lower, preferably, asserting the feedback control signal can also forcibly turn off the current source; in step 1060, then releasing the asserting feedback control signal allows the power conversion controller to resume normal operation until the external capacitor is discharged to the voltage VDDL, that is, operates for a third predetermined period, controls the external capacitor to charge from the voltage VDDL to the voltage VDDH.

Please refer to the operation of the ultra-low power consumption display control circuit 400 in FIG. 4 again. Before the voltage signal VCC5V drops to 3.3V, the zoom controller 360 deasserts the signal AC_OFF, and the zoom controller 360 draws the external power for a short time. When the zoom controller 360 detects a wake-up event, the zoom controller 360 will return to the normal operation mode from the very low power consumption mode. Increase power consumption, resulting in a short power surge (power surge), if the voltage signal VCC5V just falls to 3.3 volts at this time, it may cause the malfunction of the entire circuit.

11 shows a display controller 1100 according to a specific embodiment of the present invention, mainly including a power management unit 1120, a low power consumption control circuit 1130, a microcontroller 1150, a crystal I/O circuit 1160, and a multi-channel The multiplexer 1170 and other related power consumption circuits 1140 inside the display controller 1100 . The low power consumption control circuit 1130 can detect the sensing signal VCC5Vsense through the voltage detection circuit 1132, so as to implement the power conversion controller 1102 in the power saving mode with low power consumption in the foregoing embodiment, for example, generate the signal AC_OFF through the GPIO pin , so that the power conversion controller 1102 operates in a power-saving mode with low power consumption, and the voltage detection circuit 1132 can be a progressive approximation register analog-to-digital converter (successive approximation ADC, SAR ADC for short) or a comparator. In this embodiment, when the power management unit 1120 detects a wake-up event, it first controls the multiplexer 1170 through the signal 1122, and selects the output signal from the power management unit 1120 at its two input terminals. At this time, the power management unit 1120 deasserts the signal AC_OFF, so that the power conversion controller 1102 first returns to the normal operation mode; then, the power management unit 1120 disables the low power consumption control circuit 1130 through the signal 1124, and turns off the related power consumption circuit 1140 through the signal 1126, For example, related circuits such as a Digital Visual Interface (DVI) clock amplifier or a High-Definition Multimedia Interface (HDMI) clock amplifier may be turned off. Since the power conversion controller 1102 enters the normal operation mode, the sensing signal VCC5Vsense will gradually oscillate and rise, and the display controller 1100 detects that the sensing signal VCC5Vsense reaches a predetermined level, or after charging for a predetermined period, the power conversion controller 1102 passes the signal 1128 and 1126 to wake up the microcontroller 1150, the crystal I/O circuit 1160 and other related internal power consumption circuits 1140 for operation, the crystal I/O circuit 1160 can be coupled to an external quartz oscillator, and the crystal I/O circuit 1160 can be started officially The oscillating operation of the quartz oscillator makes the display controller 1100 return to the normal operation mode. According to the disclosure of this embodiment, the display controller 1100 can be applied to the zoom controller 360 of FIG. 4 .

FIG. 12 shows a waveform diagram of the sensing signal VCC5Vsense according to a specific embodiment of the present invention. FIG. 11 shows that after the controller 1100 detects that the sensing signal VCC5Vsense reaches a predetermined level VPD, the power conversion controller 1102 uses signals 1128 and 1126 to convert micro The controller 1150 , the crystal I/O circuit 1160 , the multiplexer 1170 and other related internal power consumption circuits 1140 wake up and operate, so that the display controller 1100 returns to the normal operation mode.

FIG. 13 shows a flow chart of a low power consumption display control method according to a specific embodiment of the present invention, which is applied in a display controller. In step 1320, the sensing signal VCC5Vsense is detected to generate a sensing result, and a sensing result is generated according to the sensing result. The control signal AC_OFF is used to control the power conversion controller to operate in a power-saving mode with low power consumption. For example, the control signal AC_OFF is generated through the GPIO pin to enable the power conversion controller to operate in a power-saving mode with low power consumption. For example, In other words, the sensing signal can be converted by analog to digital to generate the sensing result, or the sensing signal VCC5Vsense can be compared with a predetermined voltage level to generate the sensing result; in step 1340, when a wake-up event occurs, assert the control signal AC_OFF, so that the power conversion controller first returns to the normal operation mode; in step 1360, turn off the circuit related to power consumption in the display controller; in step 1380, detect whether the sensing signal VCC5Vsense reaches a predetermined level, or the charging reaches a predetermined level After the period, the microcontroller in the display controller, the crystal input/output circuit and other related internal power consumption circuits are woken up for operation, so that the display controller returns to the normal operation mode.

In summary, the present invention discloses a display controller, including a voltage detection circuit, a low power consumption control circuit, a power management unit, a selector, a microcontroller, and a crystal input/output circuit; the voltage detection circuit detects a sensing signal Voltage level; the low power consumption control circuit is coupled to the voltage detection circuit to generate a first control signal according to the voltage level, and the voltage detection circuit can be an analog-to-digital converter or a comparator; the power management unit is used to receive a wake-up event and used to generate a second control signal in response to a wake-up event; the selector is coupled to the low power consumption control circuit and the power management unit, and is used to alternatively output the first control signal and the second control signal to control a power supply The switching controller operates in a power-saving mode with low power consumption or in a normal operation mode, and the selector can be a multiplexer. When the selector outputs the second control signal, the power management unit disables the low power consumption control circuit, microcontroller, crystal I/O circuit and DVI/HDMI clock amplifier to reduce possible power consumption.

The present invention further discloses a low power consumption display control method for a display controller, including: detecting a sensing signal to generate a sensing result, for example, converting the sensing signal by analog to digital to generate a sensing result , or, by comparing the sensing signal with a predetermined voltage level to generate a sensing result; generating a control signal according to the sensing result, for example, using a general-purpose input and output pin to generate a control signal to control a power conversion control The device operates in a power-saving mode with low power consumption; when a wake-up event occurs, the control signal is asserted and the related power-consuming circuits in the display controller are disabled. For example, the microcontroller, crystal input and output circuits, and DVI/HDMI clock amplifier; finally, wakes up the display controller to return to normal operating mode.

To sum up, although the present invention has been disclosed above with preferred embodiments, they are not intended to limit the present invention. Any person familiar with this technology may make various equivalent changes or substitutions without departing from the spirit and scope of the present invention, and the protection scope of the present invention shall be defined by the appended claims of the present application.

Claims (18)

1. display controller comprises:

One voltage detecting circuit is in order to detect the voltage level of a sensing signal;

One low power consumption control circuit is coupled to this voltage detecting circuit, in order to produce one first control signal according to this voltage level;

One Power Management Unit is in order to receive a wake events and in order to produce one second control signal with in response to this wake events; And

One selector switch is coupled to this low power consumption control circuit and this Power Management Unit, in order to export this first control signal and this second control signal alternatively.

2. display controller according to claim 1 is characterized in that, also comprises a microcontroller and a crystal output/input circuit.

3. display controller according to claim 2 is characterized in that, when this selector switch is exported this second control signal, and this low power consumption control circuit of this Power Management Unit forbidden energy, this microcontroller and this crystal output/input circuit.

4. display controller according to claim 1 is characterized in that, also comprises a digital video interface clock pulse amplifier.

5. display controller according to claim 4 is characterized in that, when this selector switch is exported this second control signal, and this digital video interface clock pulse amplifier of this Power Management Unit forbidden energy.

6. display controller according to claim 1 is characterized in that, also comprises a high-definition multimedia audio/video interface clock pulse amplifier.

7. display controller according to claim 6 is characterized in that, when this selector switch is exported this second control signal, and this high-definition multimedia audio/video interface clock pulse amplifier of this Power Management Unit forbidden energy.

8. display controller according to claim 1 is characterized in that, this selector switch is a multiplexer.

9. display controller according to claim 1, it is characterized in that, this selector switch is exported this first control signal and this second control signal alternatively, to control the running that a switch controller of power supply carries out the battery saving mode or a normal manipulation mode of a low power consumption.

10. display controller according to claim 9 is characterized in that, this voltage detecting circuit is an analog-digital converter or a comparer.

11. a low power consumption display control method is used for a display controller, comprising:

Detect a sensing signal to produce a sensing result;

Produce a control signal according to this sensing result, to control the battery saving mode running that a switch controller of power supply carries out a low power consumption;

When a wake events occurring, separate the circuit of advocating power consumption relevant in this control signal and this display controller of forbidden energy; And

Wake this display controller up and be returned to a normal manipulation mode.

12. control method according to claim 11 is characterized in that, this produces this control signal step is to utilize a universal input and output pin position to produce this control signal.

13. control method according to claim 11 is characterized in that, this detection step is that analog digital is changed this sensing signal to produce this sensing result.

14. control method according to claim 11 is characterized in that, this detection step be relatively this sensing signal and a predetermined voltage level to produce this sensing result.

15. control method according to claim 11 is characterized in that, this wake-up step is when this sensing signal arrives a predetermined voltage level, wakes this display controller up and is returned to this normal manipulation mode.

16. control method according to claim 11 is characterized in that, this is separated and advocates a microcontroller and a crystal output/input circuit in this display controller of step forbidden energy.

17. control method according to claim 11 is characterized in that, this is separated and advocates a digital video interface clock pulse amplifier in this display controller of step forbidden energy.

18. control method according to claim 11 is characterized in that, this is separated and advocates step forbidden energy one high-definition multimedia audio/video interface clock pulse amplifier.

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