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CN102053395B - Bump structure, chip packaging structure and method for preparing the bump structure - Google Patents

Bump structure, chip packaging structure and method for preparing the bump structure Download PDF

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CN102053395B
CN102053395B CN 200910181090 CN200910181090A CN102053395B CN 102053395 B CN102053395 B CN 102053395B CN 200910181090 CN200910181090 CN 200910181090 CN 200910181090 A CN200910181090 A CN 200910181090A CN 102053395 B CN102053395 B CN 102053395B
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bump
insulating
substrate
structure according
electrodes
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CN102053395A (en
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陆苏财
黄昱玮
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Abstract

The invention discloses a bump structure, a chip packaging structure and a preparation method of the bump structure. The bump structure comprises a first substrate, a plurality of first electrodes, a plurality of insulating bumps, a plurality of metal extension layers and a plurality of metal layers. A plurality of first electrodes are arranged at intervals on the first substrate. The plurality of insulation bumps are arranged corresponding to the first electrodes and isolate the first electrodes from each other. Each metal extending layer is formed between the corresponding first electrode and the corresponding insulating bump, extends out of one side face of the insulating bump, and forms an extending part between the corresponding two adjacent insulating bumps, wherein the length of each extending part in the extending direction is smaller than the distance between the corresponding two adjacent insulating bumps. Each metal layer is formed on the side surface of the corresponding insulation bump and the corresponding extension part.

Description

The preparation method of projection cube structure, chip-packaging structure and this projection cube structure
Technical field
The present invention relates to the preparation method of a kind of thin space chip-packaging structure and projection cube structure thereof.
Background technology
When display panel during towards the future development of high-res, high image quality, the number of electrodes that is used for the driving pixel also also will increase inevitably thereupon, yet when increasing electrode number at set driving chip size or under less driving chip size, at present at Liquid Crystal Module (Liquid Crystal Module, LCM) in the driving chip packaging, no matter be ambetti (Chip On Glass, COG) also or crystal grain mantle (Chip On Flex, COF) all towards the research direction of thin space (fine pitch) structure dress.
Usually, in Liquid Crystal Module, drive chip and be use the joint glue material as the middle layer will drive chip join on display panel, wherein the joint glue material can be divided into anisotropic conductive (Anisotropic Conductive Adhesive, ACA) and non-conductive adhesive (Non-Conductive Adhesive, NCA).Yet, when driving chip employing thin space structure packing technique and use anisotropic conductive for joint framework middle layer, because the spacing between projection is less than 10 μ m, so conductive particle is easily assembled and the problem (bridging issue) of generation bridge joint between projection, thereby causes electric pole short circuit.For solving the bridge joint problem, different technology are developed.
U.S. Patent Application No. US 2007/0,063, and 347 disclose a kind of conductive particle, and this conductive particle outer cladding one layer insulating makes thus that to be positioned between projection the conductive particle of clustering electrically isolated from one.Yet therefore, because the insulation course on the conductive particle is quite thin, in hot-pressing making process, easily because the glue material flows conductive particle is rubbed, and insulation course is broken and causes losing efficacy.
U.S. Patent Application No. US 2005/0,227, and 475 disclose a kind of method of utilizing the distribution of impressed voltage control conductive particle on chip electrode.Though the bridge joint problem when the method can solve the thin space joint is dressed up this but can significantly improve structure.
United States Patent (USP) notification number US 7,109,058 discloses semiconductor device of a kind of bumpless and preparation method thereof, and the method is that the mode of conducting particles with the ultrasonic welding is fixed on the electrode.Though the method can be avoided producing the bridge joint problem, but manufacturing process steps is complicated, and when interelectrode gap dwindles, because being removed the fiduciary level that may cause electrode, reduces projection.
Except aforesaid bridge joint problem, when electrode density is more and more higher, also can do less and less with the projection that electrode joins.When projection becomes more and more hour, the conductive particle quantity that it can catch also decreases, and engages quality and may have influence between projection and electrode.
In sum, existing structure packing technique when the challenge that faces thin space structure dress, a kind of structure and method that overcomes the electrode engagement of above-mentioned all deficiencies to be developed still.
Summary of the invention
The object of the present invention is to provide the preparation method of projection cube structure, chip-packaging structure and this projection cube structure, to address the above problem.
The object of the present invention is achieved like this, and a kind of projection cube structure namely is provided, and it comprises a first substrate, a plurality of the first electrode, a plurality of insulation projection, a plurality of metal extended layer and a plurality of metal level.A plurality of the first electrodes are disposed at this first substrate.A plurality of insulation projections correspond to those the first electrode settings, and wherein those insulation projections are isolated those first electrodes mutually.Each metal extended layer is formed between corresponding this first electrode and this insulation projection, and extend a side of this insulation projection, and between corresponding two adjacent those insulation projections, form extensions, wherein respectively the length of this extension on its bearing of trend less than the spacing of corresponding two adjacent these insulation projections.The top of this side that each metal level is formed at this corresponding insulation projection and this corresponding extension.
Another enforcement example of the present invention discloses a kind of projection cube structure, and it comprises a first substrate, a plurality of insulation projection, a plurality of the first electrode and a plurality of metal level.A plurality of insulation projections compartment of terrain is arranged in this first substrate, and respectively this insulation projection comprises two relative sides, and wherein at least one this side is in the face of this adjacent insulation projection.Each first electrode is arranged between those adjacent projections accordingly.Respectively this metal level be formed at this corresponding first electrode and adjacent to this first electrode those the insulation projections those sides on.
The present invention one implements example and discloses a kind of chip-packaging structure, and it comprises a first substrate, a plurality of the first electrode, a plurality of insulation projection, a plurality of metal extended layer, a plurality of metal level, a second substrate, a plurality of the second electrode, reaches a conducting resinl.A plurality of the first electrodes are configured on the first substrate.A plurality of insulation projections correspond to those the first electrode settings, and those first electrodes are isolated mutually.Each metal extended layer is formed between corresponding this first electrode and this insulation projection, and extend a side of this insulation projection, and between corresponding two adjacent those insulation projections, form extensions, wherein respectively the length of this extension on its bearing of trend less than the spacing of corresponding two adjacent these insulation projections.Each metal level is formed at this side of this corresponding insulation projection and this corresponding extension.A plurality of the second electrodes are arranged at this second substrate, and wherein respectively this second electrode convexedly stretches between two adjacent these insulation projections accordingly.Conducting resinl comprises a plurality of conductive particles, and this conducting resinl is located between this first substrate and this second substrate, and some of those conductive particles catch between this second electrode respectively and corresponding this metal level.
Another enforcement example of the present invention discloses a kind of chip-packaging structure, and it comprises a first substrate, a plurality of insulation projection, a plurality of the first electrode, a plurality of metal level, a second substrate, a plurality of the second electrode, reaches a conducting resinl.A plurality of insulation projections compartment of terrain is arranged in this first substrate, and respectively this insulation projection comprises two relative sides, and wherein at least one this side is in the face of this adjacent insulation projection.Each first electrode is arranged between those adjacent insulation projections accordingly.Each metal level be formed at this corresponding first electrode and adjacent to this first electrode those the insulation projections those sides on.A plurality of the second electrodes and those the first electrodes are arranged at this second substrate accordingly, and wherein respectively this second electrode convexedly stretches between two adjacent these insulation projections accordingly.Conducting resinl comprises a plurality of conductive particles, and this conducting resinl is located between this first substrate and this second substrate, and some of those conductive particles catch between this second electrode respectively and corresponding this metal level.
The present invention one implements the preparation method that example discloses a kind of projection cube structure, and it comprises the following step: a first substrate is provided; Form a plurality of the first electrodes that are disposed on this first substrate; Form a metal extended layer on this first substrate; Correspond to those the first electrodes, form a plurality of insulation projections on this metal extended layer; Form a metal level on this metal extended layer and those insulation projections; Form accordingly a plurality of mask layers between those adjacent insulation projections, wherein respectively this mask layer cover one on should a side of insulation projection this metal level and this metal level of the part between adjacent this insulation projection, wherein this metal level of this part in the length on this first electrode spread direction less than the spacing between this adjacent insulation projection; And remove not this metal level and this metal extended layer of shade.
Another implements the preparation method that example discloses a kind of projection cube structure the present invention, and it comprises the following step: a first substrate is provided; Form a plurality of the first electrodes that are disposed on this first substrate; Form accordingly a plurality of metal extended layers on those first electrodes, wherein those metal extended layers electrical isolation each other; Form accordingly a plurality of insulation projections on those metal extended layers, some of respectively these metal extended layers are positioned between this adjacent insulation projection; Form a metal level in respectively this metal extended layer of those insulation projections and those parts; And this metal level that removes those insulation projection tops.
The another enforcement example of the present invention discloses a kind of preparation method of projection cube structure, and it comprises the following step: a first substrate is provided; Form a plurality of the first electrodes that are disposed on this first substrate; Form a plurality of insulation projections in this first substrate, wherein those first electrodes are accordingly between those insulation projections; Form a metal level on those insulation projections and those the first electrodes; And this metal level that removes those insulation projection tops.
Description of drawings
Fig. 1 shows that the present invention first implements the diagrammatic cross-section of the chip-packaging structure of example;
Fig. 2 shows that the present invention second implements the diagrammatic cross-section of the chip-packaging structure of example;
Fig. 3 shows that the present invention the 3rd implements the diagrammatic cross-section of the chip-packaging structure of example;
Fig. 4 shows that the present invention the 4th implements the diagrammatic cross-section of the chip-packaging structure of example;
Fig. 5 to Fig. 8 shows the present invention, and other implement the diagrammatic cross-section of the chip-packaging structure of example;
Fig. 9 to Figure 14 shows that the present invention one implements the fabrication processing schematic diagram of the projection cube structure of example;
Figure 15 to Figure 18 shows the present invention, and another implements the fabrication processing schematic diagram of the projection cube structure of example;
Figure 19 to Figure 21 shows the fabrication processing schematic diagram of the projection cube structure of the another enforcement example of the present invention;
Figure 22 shows that the present invention one implements the diagrammatic cross-section of the insulation projection of example; And
Figure 23 and Figure 24 be Figure 22 the insulation projection engage schematic diagram.
The main element symbol description
1a~1h projection cube structure
2 second electrodes
3 second substrates
4 anisotropic conductives
5 conductive particles
10a~10h chip-packaging structure
11 first substrates
12 first electrodes
13 protective seams
14a~14c metal extended layer
15a~15c projection that insulate
16a, 16b metal level
17 metal extended layers
18 metal levels
19 mask layers
20 macromolecule layers
121 electrode sides
141a~141c extension
142,143 extended layer sides
151 sides
Embodiment
Fig. 1 shows that the present invention first implements the diagrammatic cross-section of the chip-packaging structure 10a of example.This enforcement example discloses a kind of chip-packaging structure 10a; it comprises second substrate 3 and the projection cube structure 1a with second electrode 2 of a plurality of protrusions, and projection cube structure 1a comprises a first substrate 11, a plurality of the first electrode 12, a protective seam (passive layer) 13, a plurality of metal extended layer 14a, a plurality of insulation projection 15a and a plurality of metal level 16a.A plurality of the first electrodes 12 are disposed at first substrate 11, and in this enforcement example, the first electrode 12 can be arranged with ultra fine-pitch.Protective seam 13 be formed at the first electrode 12 around.A plurality of metal extended layer 14a are formed on those first electrodes 12 accordingly, and wherein each metal extended layer 14a extends on the direction of an electrode side 121 that is in reverse to the first corresponding electrode 12.
A plurality of insulation projection 15a are formed at the top of those the first electrodes 12 accordingly, each projection 15a that insulate covers the electrode side 121 of corresponding the first electrode 12, and each corresponding metal extended layer 14a extend through insulation projection 15a one slightly towards the side 151 that tilts, and between corresponding two adjacent insulation projection 15a, form an extension 141a, wherein the length L of each extension 141a on bearing of trend is less than the space D of corresponding two adjacent insulation projection 15a.Relatively, on metal extended layer 14a, can be insulation projection 15a in 142 relative of extended layer sides of extension 141a and cover.Because extension 141a does not extend to the insulation projection 15a of next adjacency, so electrical isolation each other between metal extended layer 14a.
Two relative sides 151 are arranged on each projection 15a that insulate, and side 151 is all slightly towards tilting.A plurality of metal level 16a and the corresponding setting of insulation projection 15a, each metal level 16a is arranged on the side 151 that insulation projection 15a is upper, metal extended layer 14a passes, and is positioned on the corresponding extension 141a that insulate between projection 15a.
Projection cube structure 1a of the present invention can be used for engaging a second substrate 3, the second electrodes 2 tools one cross-sectional shape of the second electrode 2 of tool projection form, this cross-sectional shape can and two insulation projection 15a between the depression match profiles close.Therefore when the second electrode 2 is inserted between two insulation projection 15a accordingly, the end face that the conductive particle 5 of anisotropic conductive 4 can be pressed and be bonded to side 151, the second electrodes 2 of insulation projection 15a in the side of the second electrode 2 then can press conductive particle on extension 141a.Insulation projection 15a has enough height, and therefore when second substrate 3 engaged with first substrate 11, insulation projection 15a can intercept the phenomenon of conductive particle clustering between two adjacent the second electrode 2 joints, therefore can avoid producing the problem of bridge joint.Again, in the side 151 of insulation projection 15a and the surface between insulation projection 15a the metal level 16a that is electrically connected at the first electrode 12 is set, can captures more conducting particles because of the larger area of metal level 16a tool, thereby reduce the resistance value of contact.
Fig. 2 shows that the present invention second implements the diagrammatic cross-section of the chip-packaging structure 10b of example.The chip-packaging structure 10b of this enforcement example; its second substrate 3 and one that comprises the second electrode 2 of a plurality of protrusions of a tool is used for the projection cube structure 1b of clamping connection the second electrode 2, and projection cube structure 1b comprises protective seam 13, a plurality of metal extended layer 14b, a plurality of insulation projection 15a and a plurality of metal level 16b that a first substrate 11, a plurality of the first electrode 12, that is disposed at first substrate 11 are arranged at the first electrode 12 peripheries.Each projection 15a that insulate covers an electrode side 121 of the first corresponding electrode 12, makes 12 at each first electrode form electrical isolation.Metal extended layer 14b is formed between the first corresponding electrode 12 and the corresponding insulation projection 15a, and metal extended layer 14b extends towards the reverse direction of the electrode side 121 of the first electrode 12.Metal extended layer 14b extends the side 151 of insulation projection 15a, and forms an extension 141b accordingly between two adjacent insulation projection 15a.In this enforcement example, because each insulation projection 15a is offset on the first corresponding electrode 12, makes extension 141b may extend to the insulation projection 15a of next vicinity and the situation of 12 conductings of adjacent the first electrode can not occur.Each metal level 16b is arranged at accordingly then that adjacent insulation projection 15a is upper, on opposed facing side 151 and the extension 141b, so can effectively improve the catch rate of conductive particle.
Fig. 3 shows that the present invention the 3rd implements the diagrammatic cross-section of the chip-packaging structure 10c of example.The chip-packaging structure 10c of this enforcement example; it comprises the projection cube structure 1c that a second substrate 3 and with second electrode 2 of a plurality of protrusions is used for clamping connection the second electrode 2, and projection cube structure 1c comprises protective seam 13, a plurality of metal extended layer 14c, a plurality of insulation projection 15a and a plurality of metal level 16b that a first substrate 11, a plurality of the first electrode 12, that is disposed at first substrate 11 are arranged at the first electrode 12 peripheries.Each projection 15a that insulate covers an electrode side 121 of the first corresponding electrode 12, makes 12 at each first electrode form electrical isolation.Metal extended layer 14c is formed between the first corresponding electrode 12 and the corresponding insulation projection 15a, and metal extended layer 14c extends towards the reverse direction of the electrode side 121 of the first electrode 12.Metal extended layer 14c extends the side 151 of insulation projection 15a, and forms an extension 141c accordingly between two adjacent insulation projection 15a.In this enforcement example, the upper side 143 with respect to extension 141c of each metal extended layer 14c is positioned at corresponding insulation projection 15a below, so each extension 141c may extend to the insulation projection 15a of next vicinity and the situation of conducting between adjacent metal extended layer 14c can not occur.Each metal level 16b is arranged at accordingly then that adjacent insulation projection 15a is upper, on opposed facing side 151 and the extension 141c, so can effectively improve the catch rate of conductive particle.
Fig. 4 shows that the present invention the 4th implements the diagrammatic cross-section of the chip-packaging structure 10d of example.The chip-packaging structure 10d of this enforcement example; its second substrate 3 and one that comprises the second electrode 2 of a plurality of protrusions of a tool is used for the projection cube structure 1d of clamping connection the second electrode 2, and projection cube structure 1d comprises a first substrate 11, a plurality of the first electrode 12, that is disposed at first substrate 11 is arranged at the protective seam 13 of the first electrode 12 peripheries, a plurality of insulation projection 15a and a plurality of metal level 16b.A plurality of insulation projection 15a are disposed on the first substrate 11, and each projection 15a that insulate has two relatively and be surperficial slightly towards the side 151 that tilts, and each side 151 can be in the face of an adjacent insulation projection 15a.A plurality of the first electrodes 12 are arranged between the adjacent insulation projection 15a accordingly, and a plurality of metal level 16b then are arranged between adjacent insulation projection 15a accordingly, on opposed facing side 151 and corresponding the first electrode 12.
Fig. 5 to Fig. 8 shows the present invention, and other implement the diagrammatic cross-section of the chip-packaging structure 10e to 10h of example.The enforcement example that Fig. 5 to Fig. 8 shows and aforesaid first to fourth implements to have accordingly similar structure between example.Only the aforementioned first to fourth insulation projection 15a that implements in the example has flat top, and in the enforcement example of Fig. 5 to Fig. 8, the top cross-section of insulation projection 15b is shaped as circle.When insulation projection 15a tool flat-top, joint rear section conducting particles may be pressed between the flat-top and second substrate 3 of insulation projection 15a; And the insulation projection 15b of dome then can fully push conductive particle to both sides, and effectively separates conducting particles when engaging.
Fig. 9 to Figure 14 shows that the present invention one implements the fabrication processing schematic diagram of the projection cube structure 1a of example.As shown in Figure 9, at first provide a first substrate 11, then form a plurality of spaced the first electrodes 12 at first substrate 11, then around each the first electrode 12, form protective seam 13.With reference to shown in Figure 10, then form the metal extended layer 17 that one deck covers the first electrode 12 and protective seam 13 at first substrate 11.With reference to Figure 11 and shown in Figure 12, then at metal extended layer 17 coatings one macromolecule layer 20, follow patterning macromolecule layer 20, to form a plurality of insulation projection 15a.With reference to shown in Figure 13, form afterwards a metal level 18 on the surface and the metal extended layer 17 between insulation projection 15a of insulation projection 15a.Then, form a plurality of mask layers 19 between adjacent insulation projection 15a, wherein each mask layer 19 covers a side and the metal level 18 of part between between insulation projection 15a of corresponding insulation projection 15a.Between insulation projection 15a, the metal level 18 of crested in the length in 12 orientations of the first electrode less than the spacing between insulation projection 15a.With reference to shown in Figure 14, will do not removed with metal extended layer 17 by the metal level 18 of mask layer 19 shades at last.
Figure 15 to Figure 18 shows the present invention, and another implements the fabrication processing schematic diagram of the projection cube structure 1c of example.As shown in figure 15, at first provide a first substrate 11, then form a plurality of spaced the first electrodes 12 at first substrate 11, then around each the first electrode 12, form protective seam 13.With reference to shown in Figure 16, then correspond to the first electrode 12 and form a plurality of metal extended layer 14c, wherein metal extended layer 14c electrical isolation each other.With reference to shown in Figure 17, form accordingly afterwards a plurality of insulation projection 15a on those metal extended layers 14c, some of metal extended layer 14c are between insulation projection 15a, and the metal extended layer 14c of another part is then covered by corresponding insulation projection 15a.With reference to shown in Figure 180, then form a metal level on insulation projection 15a and metal extended layer 14c, the metal level at the projection 15a top of then will insulating removes, to form last metal level 16b.
Figure 19 to Figure 21 shows the fabrication processing schematic diagram of the projection cube structure 1d of the another enforcement example of the present invention.As shown in figure 19, at first provide a first substrate 11, then form a plurality of spaced the first electrodes 12 at first substrate 11, then around each the first electrode 12, form protective seam 13.With reference to shown in Figure 20, then form a plurality of insulation projection 15a on first substrate 11, wherein those first electrodes 12 are accordingly between adjacent insulation projection 15a.With reference to shown in Figure 21, then form a metal level on insulation projection 15a and the first electrode 12, the metal level at the projection 15a top of then will insulating removes, to form last metal level 16b.
Figure 22 shows that the present invention one implements the diagrammatic cross-section of the insulation projection 15c of example; Figure 23 and Figure 24 be Figure 23 insulation projection 15c engage schematic diagram.With reference to Figure 22 to Figure 24, insulation projection 15c may be partitioned into two parts, makes insulation projection 15c be easier to distortion, so when the second electrode 2 engages, more can closely engage between the second electrode 2 and metal level 16b.Each projection 15c that insulate is divided into two parts along on the direction perpendicular to 12 orientations of the first electrode, and its mode of cutting apart comprises engraving method.Insulation projection 15c tool elasticity after cutting apart can be used in the joint that uses anisotropic conductive, as shown in figure 23; Perhaps be used in the joint of non-conductive adhesive, as shown in figure 24.
In aforementioned all enforcement examples, insulation projection 15a, 15b can be a macromolecular convex, for example polyimide (Polyimide) projection.The shape of insulation projection 15a, 15b can comprise hexahedron, right cylinder and polygonal cylinder.First substrate 11 can be silicon substrate.The second electrode 2 and 12 material are gold, copper or aluminium.Metal level 16a, 16b and 18 material are gold.The material of second substrate 3 can comprise glass substrate, polymeric substrate, silicon substrate and ceramic substrate.
Technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with the technology still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to implement the example those disclosed herein, and should comprise various do not deviate from replacement of the present invention and modifications, and by being contained with the claim of enclosing.

Claims (46)

1.一种芯片封装结构中的凸块结构,包含:1. A bump structure in a chip packaging structure, comprising: 第一基板;first substrate; 多个第一电极,配置于该第一基板上;a plurality of first electrodes configured on the first substrate; 多个绝缘凸块,相对应于该些第一电极设置,其中该些绝缘凸块位于第一电极的上方;A plurality of insulating bumps are arranged corresponding to the first electrodes, wherein the insulating bumps are located above the first electrodes; 多个金属延伸层,各该金属延伸层形成于相对应的该第一电极与该绝缘凸块之间,且延伸出该绝缘凸块的一侧面,并在相对应的两相邻的该些绝缘凸块间形成一延伸部,其中各该延伸部在其延伸方向上的长度小于相对应的两相邻的该绝缘凸块的间距;以及A plurality of metal extension layers, each metal extension layer is formed between the corresponding first electrode and the insulating bump, and extends out of one side of the insulating bump, and on the corresponding two adjacent ones An extension portion is formed between the insulation bumps, wherein the length of each extension portion in its extending direction is smaller than the distance between two corresponding adjacent insulation bumps; and 多个金属层,各该金属层形成于相对应的该绝缘凸块的该侧面与相对应的该延伸部的上方。A plurality of metal layers, each metal layer is formed on the side of the corresponding insulating bump and above the corresponding extension. 2.根据权利要求1所述的凸块结构,其中各该绝缘凸块包含相对于该侧面的另一侧面,其中各该金属层形成于相邻的该些绝缘凸块间相互面对的两该侧面上。2. The bump structure according to claim 1, wherein each of the insulating bumps comprises another side opposite to the side, wherein each of the metal layers is formed on two sides facing each other between adjacent insulating bumps. on this side. 3.根据权利要求1所述的凸块结构,其中各该绝缘凸块位于相对应的该第一电极的正上方。3. The bump structure according to claim 1, wherein each insulating bump is located directly above the corresponding first electrode. 4.根据权利要求1所述的凸块结构,其中该绝缘凸块是一高分子凸块。4. The bump structure according to claim 1, wherein the insulating bump is a polymer bump. 5.根据权利要求4所述的凸块结构,其中各该绝缘凸块沿垂直于该些第一电极排列方向上分割成两部分。5. The bump structure according to claim 4, wherein each insulating bump is divided into two parts along a direction perpendicular to the arrangement of the first electrodes. 6.根据权利要求1所述的凸块结构,其中该绝缘凸块的形状包含六面体、圆柱体及多角柱体。6. The bump structure according to claim 1, wherein the shape of the insulating bump comprises a hexahedron, a cylinder and a polygonal prism. 7.根据权利要求1所述的凸块结构,其中该绝缘凸块的顶部截面形状为一圆弧。7. The bump structure according to claim 1, wherein a top cross-sectional shape of the insulating bump is an arc. 8.根据权利要求1所述的凸块结构,其中该第一基板为一硅基板。8. The bump structure according to claim 1, wherein the first substrate is a silicon substrate. 9.根据权利要求1所述的凸块结构,其中该第一电极的材料是金、铜或铝。9. The bump structure according to claim 1, wherein the material of the first electrode is gold, copper or aluminum. 10.根据权利要求1所述的凸块结构,其中该金属层的材质是金。10. The bump structure according to claim 1, wherein the material of the metal layer is gold. 11.一种芯片封装结构中的凸块结构,包含:11. A bump structure in a chip packaging structure, comprising: 第一基板;first substrate; 多个绝缘凸块,配置于该第一基板,各该绝缘凸块包含两相对的侧面,其中至少一该侧面面对一相邻的该绝缘凸块;a plurality of insulating bumps disposed on the first substrate, each of the insulating bumps includes two opposite sides, wherein at least one of the side faces faces an adjacent insulating bump; 多个第一电极,各该第一电极相对应地设置于相邻的该些绝缘凸块之间;以及a plurality of first electrodes, each of which is correspondingly disposed between adjacent insulating bumps; and 多个金属层,各该金属层形成于相对应的该第一电极和相邻于该第一电极的该些绝缘凸块的该些侧面上。A plurality of metal layers, each metal layer is formed on the corresponding first electrode and the side surfaces of the insulating bumps adjacent to the first electrode. 12.根据权利要求11所述的凸块结构,其中该绝缘凸块是一高分子凸块。12. The bump structure according to claim 11, wherein the insulating bump is a polymer bump. 13.根据权利要求11所述的凸块结构,其中各该绝缘凸块沿垂直于该些第一电极排列方向上分割成两部分。13. The bump structure according to claim 11, wherein each of the insulating bumps is divided into two parts along a direction perpendicular to the arrangement of the first electrodes. 14.根据权利要求11所述的凸块结构,其中该绝缘凸块的形状包含六面体、圆柱体及多角柱体。14. The bump structure according to claim 11, wherein the shape of the insulating bump comprises a hexahedron, a cylinder and a polygonal prism. 15.根据权利要求11所述的凸块结构,其中该绝缘凸块的顶部截面形状为一圆弧。15. The bump structure according to claim 11, wherein a top cross-sectional shape of the insulating bump is an arc. 16.根据权利要求11所述的凸块结构,其中该第一基板为一硅基板。16. The bump structure according to claim 11, wherein the first substrate is a silicon substrate. 17.根据权利要求11所述的凸块结构,其中该第一电极的材料是金、铜或铝。17. The bump structure according to claim 11, wherein the material of the first electrode is gold, copper or aluminum. 18.根据权利要求11所述的凸块结构,其中该金属层的材质是金。18. The bump structure according to claim 11, wherein a material of the metal layer is gold. 19.一种芯片封装结构,包含:19. A chip packaging structure, comprising: 第一基板;first substrate; 多个第一电极,配置于该第一基板上;a plurality of first electrodes configured on the first substrate; 多个绝缘凸块,相对应于该些第一电极设置,其中该些绝缘凸块位于第一电极的上方;A plurality of insulating bumps are arranged corresponding to the first electrodes, wherein the insulating bumps are located above the first electrodes; 多个金属延伸层,各该金属延伸层形成于相对应的该第一电极与该绝缘凸块之间,且延伸出该绝缘凸块的一侧面,并于相对应的两相邻的该些绝缘凸块间形成一延伸部,其中各该延伸部在其延伸方向上的长度小于相对应的两相邻的该绝缘凸块的间距;A plurality of metal extension layers, each metal extension layer is formed between the corresponding first electrode and the insulating bump, and extends out of one side of the insulating bump, and is formed on the corresponding two adjacent ones An extension portion is formed between the insulation bumps, wherein the length of each extension portion in its extending direction is smaller than the distance between two corresponding adjacent insulation bumps; 多个金属层,各该金属层形成于相对应的该绝缘凸块的该侧面与相对应的该延伸部的上方;a plurality of metal layers, each of the metal layers is formed on the side surface of the corresponding insulating bump and above the corresponding extension; 第二基板;second substrate; 多个第二电极,设置于该第二基板,其中各该第二电极相对应地凸伸于两相邻的该绝缘凸块之间;以及a plurality of second electrodes disposed on the second substrate, wherein each second electrode correspondingly protrudes between two adjacent insulating bumps; and 导电胶,包含多个导电颗粒,该导电胶设于该第一基板与该第二基板之间,其中部分的该些导电颗粒捕捉于各该第二电极与相对应的该金属层之间。The conductive glue includes a plurality of conductive particles, the conductive glue is disposed between the first substrate and the second substrate, and some of the conductive particles are trapped between each second electrode and the corresponding metal layer. 20.根据权利要求19所述的芯片封装结构,其中各该绝缘凸块包含相对于该侧面的另一侧面,其中各该金属层形成于相邻的该些绝缘凸块间相互面对的两该侧面上。20. The chip packaging structure according to claim 19, wherein each of the insulating bumps comprises another side opposite to the side, wherein each of the metal layers is formed on two sides facing each other between adjacent insulating bumps. on this side. 21.根据权利要求19所述的芯片封装结构,其中各该绝缘凸块位于相对应的该第一电极的正上方。21. The chip packaging structure according to claim 19, wherein each insulating bump is located directly above the corresponding first electrode. 22.根据权利要求19所述的芯片封装结构,其中该绝缘凸块是一高分子凸块。22. The chip packaging structure according to claim 19, wherein the insulating bump is a polymer bump. 23.根据权利要求22所述的芯片封装结构,其中各该绝缘凸块沿垂直于该些第一电极排列方向上分割成两部分。23. The chip packaging structure according to claim 22, wherein each insulating bump is divided into two parts along a direction perpendicular to the arrangement of the first electrodes. 24.根据权利要求19的芯片封装结构,其中该绝缘凸块的形状包含六面体、圆柱体及多角柱体。24. The chip package structure according to claim 19, wherein the shape of the insulating bump comprises a hexahedron, a cylinder and a polygonal prism. 25.根据权利要求19所述的芯片封装结构,其中该绝缘凸块的顶部截面形状为一圆弧。25. The chip package structure according to claim 19, wherein a top cross-sectional shape of the insulating bump is an arc. 26.根据权利要求19所述的芯片封装结构,其中该第一基板为一硅基板。26. The chip package structure according to claim 19, wherein the first substrate is a silicon substrate. 27.根据权利要求19所述的芯片封装结构,其中该第一电极的材料是金、铜或铝。27. The chip package structure according to claim 19, wherein the material of the first electrode is gold, copper or aluminum. 28.根据权利要求19所述的芯片封装结构,其中该金属层的材质是金。28. The chip package structure according to claim 19, wherein the material of the metal layer is gold. 29.一种芯片封装结构,包含:29. A chip packaging structure, comprising: 第一基板;first substrate; 多个绝缘凸块,配置于该第一基板,各该绝缘凸块包含两相对的侧面,其中至少一该侧面面对一相邻的该绝缘凸块;a plurality of insulating bumps disposed on the first substrate, each of the insulating bumps includes two opposite sides, wherein at least one of the side faces faces an adjacent insulating bump; 多个第一电极,各该第一电极相对应地设置于相邻的该些绝缘凸块之间;A plurality of first electrodes, each of which is correspondingly arranged between adjacent insulating bumps; 多个金属层,各该金属层形成于相对应的该第一电极和相邻于该第一电极的该些绝缘凸块的该些侧面上;a plurality of metal layers, each of the metal layers is formed on the corresponding first electrode and the side surfaces of the insulating bumps adjacent to the first electrode; 第二基板;second substrate; 多个第二电极,与该些第一电极相对应设置于该第二基板,其中各该第二电极相对应地凸伸于两相邻的该绝缘凸块之间;以及A plurality of second electrodes are disposed on the second substrate corresponding to the first electrodes, wherein each second electrode protrudes correspondingly between two adjacent insulating bumps; and 导电胶,包含多个导电颗粒,该导电胶设于该第一基板与该第二基板之间,其中部分的该些导电颗粒捕捉于各该第二电极与相对应的该金属层之间。The conductive glue includes a plurality of conductive particles, the conductive glue is disposed between the first substrate and the second substrate, and some of the conductive particles are trapped between each second electrode and the corresponding metal layer. 30.根据权利要求29所述的芯片封装结构,其中该绝缘凸块是一高分子凸块。30. The chip package structure according to claim 29, wherein the insulating bump is a polymer bump. 31.根据权利要求29所述的芯片封装结构,其中各该绝缘凸块沿垂直于该些第一电极排列方向上分割成两部分。31. The chip packaging structure according to claim 29, wherein each insulating bump is divided into two parts along a direction perpendicular to the arrangement of the first electrodes. 32.根据权利要求29所述的芯片封装结构,其中该绝缘凸块的形状包含六面体、圆柱体及多角柱体。32. The chip packaging structure according to claim 29, wherein the shape of the insulating bump comprises a hexahedron, a cylinder and a polygonal prism. 33.根据权利要求29所述的芯片封装结构,其中该绝缘凸块的顶部截面形状为一圆弧。33. The chip package structure according to claim 29, wherein a top cross-sectional shape of the insulating bump is an arc. 34.根据权利要求29所述的芯片封装结构,其中该第一基板为一硅基板。34. The chip package structure according to claim 29, wherein the first substrate is a silicon substrate. 35.根据权利要求29所述的芯片封装结构,其中该第一电极的材料是金、铜或铝。35. The chip package structure according to claim 29, wherein the material of the first electrode is gold, copper or aluminum. 36.根据权利要求29所述的芯片封装结构,其中该金属层的材质是金。36. The chip packaging structure according to claim 29, wherein the metal layer is made of gold. 37.一种芯片封装结构中的凸块结构的制备方法,包含下列步骤:37. A method for preparing a bump structure in a chip packaging structure, comprising the following steps: 提供一第一基板;providing a first substrate; 形成多个在该第一基板上的第一电极;forming a plurality of first electrodes on the first substrate; 形成一金属延伸层于该第一基板上;forming a metal extension layer on the first substrate; 相对应于该些第一电极,形成多个绝缘凸块在该金属延伸层上;Corresponding to the first electrodes, forming a plurality of insulating bumps on the metal extension layer; 形成一金属层在该金属延伸层与该些绝缘凸块上;forming a metal layer on the metal extension layer and the insulating bumps; 相对应地形成多个遮罩层在相邻的该些绝缘凸块之间,其中各该遮罩层覆盖该绝缘凸块的一侧面上的该金属层及相邻的该绝缘凸块间部分的该金属层,其中部分的该金属层在该第一电极排列方向上的长度小于相邻的该绝缘凸块间的间距;以及Correspondingly forming a plurality of masking layers between the adjacent insulating bumps, wherein each masking layer covers the metal layer on one side of the insulating bump and the portion between the adjacent insulating bumps the metal layer, wherein the length of part of the metal layer in the first electrode arrangement direction is smaller than the distance between adjacent insulating bumps; and 移除未遮罩的该金属层与该金属延伸层。The unmasked metal layer and the metal extension layer are removed. 38.一种芯片封装结构中的凸块结构的制备方法,包含下列步骤:38. A method for preparing a bump structure in a chip packaging structure, comprising the following steps: 提供一第一基板;providing a first substrate; 形成多个配置于该第一基板上的第一电极;forming a plurality of first electrodes disposed on the first substrate; 相对应地形成多个金属延伸层在该些第一电极上,其中该些金属延伸层彼此电性隔离;correspondingly forming a plurality of metal extension layers on the first electrodes, wherein the metal extension layers are electrically isolated from each other; 相对应地形成多个绝缘凸块在该些金属延伸层上,其中部分的各该金属延伸层位于相邻的该绝缘凸块间;Correspondingly forming a plurality of insulating bumps on the metal extension layers, wherein part of each metal extension layer is located between the adjacent insulating bumps; 形成一金属层于该些绝缘凸块与该些部分的各该金属延伸层;以及forming a metal layer on each of the insulating bumps and the portions of the metal extension layer; and 移除该些绝缘凸块顶部的该金属层。The metal layer on top of the insulating bumps is removed. 39.一种芯片封装结构中的凸块结构的制备方法,包含下列步骤:39. A method for preparing a bump structure in a chip packaging structure, comprising the following steps: 提供一第一基板;providing a first substrate; 形成多个配置于该第一基板上的第一电极;forming a plurality of first electrodes disposed on the first substrate; 形成多个绝缘凸块于该第一基板,其中该些第一电极相对应地位于该些绝缘凸块之间;forming a plurality of insulating bumps on the first substrate, wherein the first electrodes are correspondingly located between the insulating bumps; 形成一金属层在该些绝缘凸块与该些第一电极之上;以及forming a metal layer on the insulating bumps and the first electrodes; and 移除该些绝缘凸块顶部的该金属层。The metal layer on top of the insulating bumps is removed. 40.根据权利要求37至39的任一项所述的凸块结构的制备方法,其还包含形成一保护层于该些第一电极的周围的步骤,其中形成一保护层在该些第一电极之间的步骤早于形成一金属延伸层在该第一基板上的步骤。40. The method for manufacturing a bump structure according to any one of claims 37 to 39, further comprising a step of forming a protective layer around the first electrodes, wherein a protective layer is formed on the first electrodes The step between electrodes is earlier than the step of forming a metal extension layer on the first substrate. 41.根据权利要求37至39的任一项所述的凸块结构的制备方法,其中该绝缘凸块是一高分子凸块。41. The method for manufacturing a bump structure according to any one of claims 37-39, wherein the insulating bump is a polymer bump. 42.根据权利要求37至39的任一项所述的凸块结构的制备方法,其还包含将各该绝缘凸块沿垂直于该些第一电极排列方向上蚀刻成两部分的步骤。42. The method for manufacturing a bump structure according to any one of claims 37-39, further comprising a step of etching each insulating bump into two parts along a direction perpendicular to the arrangement of the first electrodes. 43.根据权利要求37至39的任一项所述的凸块结构的制备方法,其中该绝缘凸块的形状包含六面体、圆柱体及多角柱体。43. The method for manufacturing a bump structure according to any one of claims 37-39, wherein the shape of the insulating bump includes a hexahedron, a cylinder, and a polygonal prism. 44.根据权利要求37至39的任一项所述的凸块结构的制备方法,其中该第一基板为硅基板。44. The method for manufacturing a bump structure according to any one of claims 37-39, wherein the first substrate is a silicon substrate. 45.根据权利要求37至39的任一项所述的凸块结构的制备方法,其中该第一电极的材料是金、铜或铝。45. The method for manufacturing a bump structure according to any one of claims 37-39, wherein the material of the first electrode is gold, copper or aluminum. 46.根据权利要求37至39的任一项所述的凸块结构的制备方法,其中该金属层的材质是金。46. The method for manufacturing a bump structure according to any one of claims 37-39, wherein the metal layer is made of gold.
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