CN102053222A - Method for reading chip information by using semiconductor tester - Google Patents
Method for reading chip information by using semiconductor tester Download PDFInfo
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- CN102053222A CN102053222A CN2009102017646A CN200910201764A CN102053222A CN 102053222 A CN102053222 A CN 102053222A CN 2009102017646 A CN2009102017646 A CN 2009102017646A CN 200910201764 A CN200910201764 A CN 200910201764A CN 102053222 A CN102053222 A CN 102053222A
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Abstract
The invention discloses a method for reading chip information by using a semiconductor tester. The method comprises the following steps: a serial graphic generator generates a graphic value and writes the graphic value into a graphic true value table, and a data comparator outputs an X result to a data invalid memory according to the graphic value and outputs a Y result to the data invalid memory; a test program is used for setting a data selector, and setting the link between the bits of a digital acquisition unit and a chip test channel; the X result value and Y result value in the data invalid memory are converted into an acquisition enabling signal of the digital acquisition unit through an exclusive or logic gate in the digital acquisition unit, thereby controlling a storage interval corresponding to the chip test channel in the memory which transmits an H result or L result value into the digital acquisition unit; and finally, the data in the memory of the digital acquisition unit is transmitted into a designated array variable through background processing. The method provided by the invention can be used for simultaneously reading the information in multiple chips by utilizing the semiconductor tester, thereby saving the testing time.
Description
Technical field
The present invention relates to the semiconductor test technology, particularly a kind of method of utilizing semi-conductor test instrument to read chip information.
Background technology
Common semi-conductor test instrument, for example ADVANTEST T6573 as shown in Figure 1, comprises main frame (Main Frame), measuring head (Test Head), digital collection device (DCAP);
Unit of testing and controlling (Tester Controller), power supply unit (DPS) (being used to chip under test that power supply is provided), dc parameter measuring unit (be used for the measurement of chip under test dc parameter or provide chip exterior to apply electric current and voltage) are provided described main frame;
Described measuring head comprises channel electron loop (Pin Electronics), framework processor (FP, Frame Processor), frequency generator (Rate Generator), data failure storer (DFM), sequence pattern generator (SQPG), algorithm pattern generator (ALPG), scanning patter generator (SCPG), data selector (PDS);
Described channel electron loop comprises two comparers (CP) and datum generator (VO), described two comparers (CP) are used for the comparison of logic high and logic low, the data-signal of chip under test output connects described two comparers (CP), reference high level (VOH) and reference low level (VOL) with datum generator (VO) output compares respectively, its detection (STROBE) point that compares the data signal waveforms of chip under test output is the time edge by the clock signal (STBL) of the timing sequencer generation of framework processor (FP), described datum generator (VO) is used to produce the datum of a logical one and a logical zero, if the data signal levels of chip under test output is smaller or equal to reference low level (VOL), low datum comparer output 0, otherwise export 1, if the data signal levels of chip under test output is more than or equal to reference high level (VOH), high with reference to level comparator output 0, otherwise export 1, thus the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor (FP).
Described framework processor (FP, Framr Processor) comprises data comparator (DigitalCompare), timing sequencer (Timing Generator), reshaper (Formatter), sequential memory (Timing Memory), wave memorizer (Waveform Memory), described sequential memory is used to produce different time edges, and the data-signal that is used for the generation of chip under test excitation waveform, I/O switching controls, chip under test output relatively waits; Described data comparator moves according to the pattern values in the figure truth table (TTB) (PATTERN value), and is as shown in table 1, and when the PATTERN value was 0, described data comparator was not worked; When the PATTERN value was 1, described data comparator was not worked; When the PATTERN value is L, if low datum comparer output 0 (data signal levels of chip under test output is smaller or equal to reference low level), then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if low datum comparer output 1 (data signal levels of chip under test output is greater than reference low level), then the data test of chip output lost efficacy, described data comparator will hang down the output of datum comparer to be done to export data failure storer DFM to as X result after negate is handled, and directly exports height to data failure storer DFM as Y result with reference to level comparator output; When the PATTERN value is H, if it is high with reference to level comparator output 0 (data signal levels of chip under test output is more than or equal to the reference high level), then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if it is high with reference to level comparator output 1 (data signal levels of chip under test output is less than the reference high level), then the data test of chip output lost efficacy, described data comparator is done height to export data failure storer DFM to as Y result after negate is handled with reference to level comparator output, will hang down the output of datum comparer and directly export data failure storer DFM to as X result; When the PATTERN value is Z, data comparator can be done following processing: height is done negate with reference to level comparator output handle and export data failure storer DFM to as Y result, will hang down the output of datum comparer and do negate and handle and export data failure storer DFM to as X result; When the PATTERN value was X, described data comparator was not worked;
Table 1
| The PATTERN value | The comparer action |
| 0 | Do not compare |
| 1 | Do not compare |
| L | Compare VOL |
| H | Compare VOH |
| Z | Compare Z |
| X | Do not compare |
Described reshaper, time edge and sample data according to timing sequencer produces generate the waveform that is applied on the chip under test); The described sequential memory rise time continues to use in each sequential configuration; Described wave memorizer is used for the sample data of storage sequence pattern generator.
Described sequence pattern generator (SQPG, Sequential Pattern Generator) generates the resolution chart that the chip under test functional evaluation is used, comprising figure truth table (TTB), figure (PATTERN) value that the sequence pattern generator produces is write in this figure truth table (TTB), and figure (PATTERN) value that the sequence pattern generator is written in the described figure truth table (TTB) comprises 0,1, L, H, Z, X;
Comprise register in the described algorithm pattern generator (ALPG), the graph data that the algorithm pattern generator produces writes in the described register, is used for producing the write operation figure and the comparison figure (PATTERN) of chip.When using the figure (PATTERN) of algorithm pattern generator, figure in the described register (PATTERN) data are written to the figure truth table (TTB) in the described sequence pattern generator (SQPG), figure (PATTERN) value that algorithm pattern generator (ALPG) is written in the described figure truth table (TTB) is corresponding with the every value in the register, and two kinds of L, H are arranged;
Described data selector (PDS) is generally used for select distributing the graph data that generated by ALPG, SCPG (scanning patter generator) the figure truth table (TTB) in the described sequence pattern generator (SQPG);
Described frequency generator generates main clock pulse and is used to determine test frequency;
Described digital collection device is used for ADC (analog to digital converter) test, comprising storer and exclusive or logic gate.
When wafer (wafer) tests, generally can in each chip, write different data messages, when test, these information need be read out, be used for follow-up test.When reading chip information, present method, be to utilize semi-conductor test instrument with algorithm pattern generator (ALPG), by calling the value execution reading chip information operating that the algorithm pattern generator constantly changes register, value until register is identical with a string data of chip under test output, promptly by data selector (PDS), select to distribute the graph data that generates by the ALPG figure truth table (TTB) in the described sequence pattern generator (SQPG), by calling the value that the algorithm pattern generator constantly changes register, thereby change (PATTERN) value in the figure truth table (TTB), because (PATTERN) value has only L, two kinds of H, so described data comparator can be tested the data of chip under test output, all test with the data of the identical a string chip under test output of described register when figure place and to pass through, the data that the chip under test of then should going here and there is exported are identical with the data in the described register, thereby the value of register can be read as the data of this string chip under test output, again the value of register is imported into the array variable of background computer program, but be subject to the figure place of register, the once general maximum data that can only read 64Bit of this method are imported the array variable of background computer program into, and read chip information with needing a chips one chips, can consume a large amount of test durations.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method of utilizing semi-conductor test instrument to read chip information, can allow semi-conductor test instrument simultaneously the data of the storer in the multiple chips be read, and saves the test duration.
For solving the problems of the technologies described above, the method for utilizing semi-conductor test instrument to read chip information of the present invention, semi-conductor test instrument comprises main frame, measuring head, digital collection device; Described measuring head comprises channel electron loop, framework processor, data failure storer, sequence pattern generator, data selector;
Described channel electron loop comprises two comparers and datum generator, the data-signal of chip under test output connects described two comparers, reference high level and reference low level with the output of datum generator compares respectively, if the data signal levels of chip under test output is smaller or equal to reference low level, low datum comparer output 0, otherwise export 1, if the data signal levels of chip under test output is more than or equal to the reference high level, high with reference to level comparator output 0, otherwise export 1, thus the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor;
Described framework processor comprises data comparator, and described data comparator moves according to the pattern values in the figure truth table in the sequence pattern generator, when pattern values is 0,1 or during X, described data comparator is not worked; When pattern values is L, if low datum comparer output 0, then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if low datum comparer output 1, then the data test of chip output lost efficacy, and described data comparator will hang down the output of datum comparer to be done to export the data failure storer to as X result after negate is handled, and directly exports height to the data failure storer as Y result with reference to level comparator output; When pattern values is H, if it is high with reference to level comparator output 0, then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if it is high with reference to level comparator output 1, then the data test of chip output lost efficacy, and described data comparator is done height to export the data failure storer to as Y result after negate is handled with reference to level comparator output, will hang down the output of datum comparer and directly export the data failure storer to as X result; When pattern values is Z, data comparator can be done following processing: height is done negate with reference to level comparator output handle and export the data failure storer to as Y result, will hang down the output of datum comparer and do negate and handle and export the data failure storer to as X result;
Described sequence pattern generator wherein is provided with the figure truth table, and the sequence pattern generator can produce figure and pattern values is write described figure truth table, and the pattern values of the figure that the sequence pattern generator produces comprises 0,1, L, H, Z, X;
Described digital collection device comprises storer and exclusive or logic gate;
It is characterized in that:
When reading chip under test information, reference high level, the reference low level of the datum generator in channel electron loop are set by test procedure, height by the channel electron loop with reference to level comparator, low two comparers of datum comparer respectively relatively to the data signal levels of chip under test output, the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor;
The control sequence pattern generator produces pattern values and writes in the figure truth table, thereby described data comparator according to the pattern values in the figure truth table will hang down datum relatively chip under test output data relatively back output X result to the data failure storer, with height with reference to level ratio than the data of chip under test output relatively back output Y result to the data failure storer;
By test procedure data selector is set, each bit of setting digital collection device links with the chip testing passage;
Again the X result in the data failure storer, Y end value are generated the collection enable signal of digital collection device by the exclusive or logic gate in the digital collection device, be used for controlling H result or L end value are imported in the storer of digital collection device between the memory block with this chip testing passage correspondence;
By background process the data in the digital collection device storer are imported in the array variable of appointment at last.
The reference high level that the datum generator in channel electron loop can be set equals reference low level.
The method of utilizing semi-conductor test instrument to read chip information of the present invention, be by setting linking of each bit of digital collection device and chip testing passage, thereby the chip under test data that a plurality of chip testing passages transmit can be imported into respectively in the storer of digital collection device between memory block with this chip testing passage correspondence, by background process the data in the storer of digital collection device are imported in the array variable again, thereby can carry out read operation to the information of multiple chips simultaneously, and save the test duration.
Description of drawings
Below in conjunction with the drawings and the specific embodiments the present invention is described in further detail.
Fig. 1 is common semi-conductor test instrument structured flowchart;
Fig. 2 is the method one embodiment synoptic diagram that utilizes semi-conductor test instrument to read chip information of the present invention.
Embodiment
The method of utilizing semi-conductor test instrument to read chip information of the present invention, semi-conductor test instrument comprise main frame (Main Frame), measuring head (Test Head), digital collection device (DCAP); Unit of testing and controlling (Tester Controller), power supply unit (DPS) (being used to chip under test that power supply is provided), dc parameter measuring unit (be used for the measurement of chip under test dc parameter or provide chip exterior to apply electric current and voltage) are provided described main frame; Described measuring head comprises channel electron loop (PinElectronics), framework processor (FP, Frame Processor), frequency generator (RateGenerator), data failure storer (DFM), sequence pattern generator (SQPG), algorithm pattern generator (ALPG), data selector (PDS);
Described channel electron loop comprises two comparers (CP) and datum generator (VO), described two comparers (CP) are used for the comparison of logic high and logic low, the data-signal of chip under test output connects described two comparers (CP), reference high level (VOH) and reference low level (VOL) with datum generator (VO) output compares respectively, its detection (STROBE) point that compares the data signal waveforms of chip under test output is the time edge by the clock signal (STBL) of the timing sequencer generation of framework processor (FP), described datum generator (VO) is used to produce the datum of a logical one and a logical zero, if the data signal levels of chip under test output is smaller or equal to reference low level (VOL), low datum comparer output 0, otherwise export 1, if the data signal levels of chip under test output is more than or equal to reference high level (VOH), high with reference to level comparator output 0, otherwise export 1, thus the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor (FP).
Described framework processor (FP, Framr Processor) comprises data comparator (DigitalCompare), timing sequencer (Timing Generator), reshaper (Formatter), sequential memory (Timing Memory), wave memorizer (Waveform Memory), described sequential memory is used to produce different time edges, and the data-signal that is used for the generation of chip under test excitation waveform, I/O switching controls, chip under test output relatively waits; Described data comparator moves according to the pattern values in the figure truth table (TTB) (PATTERN value), and is as shown in table 1, and when the PATTERN value was 0, described data comparator was not worked; When the PATTERN value was 1, described data comparator was not worked; When the PATTERN value is L, if low datum comparer output 0 (data signal levels of chip under test output is smaller or equal to reference low level), then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if low datum comparer output 1 (data signal levels of chip under test output is greater than reference low level), then the data test of chip output lost efficacy, described data comparator will hang down the output of datum comparer to be done to export data failure storer DFM to as X result after negate is handled, and directly exports height to data failure storer DFM as Y result with reference to level comparator output; When the PATTERN value is H, if it is high with reference to level comparator output 0 (data signal levels of chip under test output is more than or equal to the reference high level), then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if it is high with reference to level comparator output 1 (data signal levels of chip under test output is less than the reference high level), then the data test of chip output lost efficacy, described data comparator is done height to export data failure storer DFM to as Y result after negate is handled with reference to level comparator output, will hang down the output of datum comparer and directly export data failure storer DFM to as X result; When the PATTERN value is Z, data comparator can be done following processing: height is done negate with reference to level comparator output handle and export data failure storer DFM to as Y result, will hang down the output of datum comparer and do negate and handle and export data failure storer DFM to as X result; When the PATTERN value was X, described data comparator was not worked;
Described reshaper, time edge and sample data according to timing sequencer produces generate the waveform that is applied on the chip under test); The described sequential memory rise time continues to use in each sequential configuration; Described wave memorizer is used for the sample data of storage sequence pattern generator.
Described sequence pattern generator (SQPG, Sequential Pattern Generator) generates the resolution chart that the chip under test functional evaluation is used, comprising figure truth table (TTB), figure (PATTERN) value that the sequence pattern generator produces is write in this figure truth table (TTB), and figure (PATTERN) value that the sequence pattern generator is written in the described figure truth table (TTB) comprises 0,1, L, H, Z, X;
Comprise register in the described algorithm pattern generator (ALPG), the graph data that the algorithm pattern generator produces writes in the described register, is used for producing the write operation figure and the comparison figure (PATTERN) of chip.When using the figure (PATTERN) of algorithm pattern generator, figure in the described register (PATTERN) data are written to the figure truth table (TTB) in the described sequence pattern generator (SQPG), figure (PATTERN) value that algorithm pattern generator (ALPG) is written in the described figure truth table (TTB) is corresponding with the every value in the register, and two kinds of L, H are arranged;
Described data selector (PDS) is generally used for select distributing the graph data that generated by ALPG, SCPG (scanning patter generator) the figure truth table (TTB) in the described sequence pattern generator (SQPG);
Described frequency generator generates main clock pulse and is used to determine test frequency;
Described digital collection device comprises storer and exclusive or logic gate.
One embodiment as shown in Figure 2, when reading chip under test information, the reference high level (VOH) of the datum generator in channel electron loop is set by test procedure, reference low level (VOL) and sampling time sequence, one preferred embodiment, will be with reference to high level (VOH), reference low level (VOL) is made as identical, height by the channel electron loop is with reference to level comparator, low two comparers of datum comparer respectively relatively to the data signal levels of chip under test output, the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor;
The control sequence pattern generator produces pattern values and writes in the figure truth table, thereby described data comparator according to the pattern values in the figure truth table will hang down datum relatively chip under test output data relatively back output X result to the data failure storer, with height with reference to level ratio than the data of chip under test output relatively back output Y result to the data failure storer;
By test procedure data selector is set, each bit of setting digital collection device links with the chip testing passage;
Again the X result in the data failure storer, Y end value are generated the collection enable signal of digital collection device by the exclusive or logic gate in the digital collection device, be used for controlling H result or L end value are imported in the storer of digital collection device between the memory block with this chip testing passage correspondence;
By background process the data in the digital collection device storer are imported in the array variable of appointment at last.
The method of utilizing semi-conductor test instrument to read chip information of the present invention, be by setting linking of each bit of digital collection device and chip testing passage, thereby the chip under test data that a plurality of chip testing passages transmit can be imported into respectively in the storer of digital collection device between memory block with this chip testing passage correspondence, by background process the data in the storer of digital collection device are imported in the array variable again, thereby can carry out read operation to the information of multiple chips simultaneously, and save the test duration.
Claims (2)
1. method of utilizing semi-conductor test instrument to read chip information, semi-conductor test instrument comprises main frame, measuring head, digital collection device; Described measuring head comprises channel electron loop, framework processor, data failure storer, sequence pattern generator, data selector;
Described channel electron loop comprises two comparers and datum generator, the data-signal of chip under test output connects described two comparers, reference high level and reference low level with the output of datum generator compares respectively, if the data signal levels of chip under test output is smaller or equal to reference low level, low datum comparer output 0, otherwise export 1, if the data signal levels of chip under test output is more than or equal to the reference high level, high with reference to level comparator output 0, otherwise export 1, thus the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor;
Described framework processor comprises data comparator, and described data comparator moves according to the pattern values in the figure truth table in the sequence pattern generator, when pattern values is 0,1 or during X, described data comparator is not worked; When pattern values is L, if low datum comparer output 0, then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if low datum comparer output 1, then the data test of chip output lost efficacy, and described data comparator will hang down the output of datum comparer to be done to export the data failure storer to as X result after negate is handled, and directly exports height to the data failure storer as Y result with reference to level comparator output; When pattern values is H, if it is high with reference to level comparator output 0, then the data test of chip output passes through, the data test of described data comparator pio chip output passes through signal, if it is high with reference to level comparator output 1, then the data test of chip output lost efficacy, and described data comparator is done height to export the data failure storer to as Y result after negate is handled with reference to level comparator output, will hang down the output of datum comparer and directly export the data failure storer to as X result; When pattern values is Z, data comparator can be done following processing: height is done negate with reference to level comparator output handle and export the data failure storer to as Y result, will hang down the output of datum comparer and do negate and handle and export the data failure storer to as X result;
Described sequence pattern generator wherein is provided with the figure truth table, and the sequence pattern generator can produce figure and pattern values is write described figure truth table, and the pattern values of the figure that the sequence pattern generator produces comprises 0,1, L, H, Z, X;
Described digital collection device comprises storer and exclusive or logic gate;
It is characterized in that:
When reading chip under test information, reference high level, the reference low level of the datum generator in channel electron loop are set by test procedure, height by the channel electron loop with reference to level comparator, low two comparers of datum comparer respectively relatively to the data signal levels of chip under test output, the low datum of output relatively chip under test output data and high with reference to level ratio than the data two paths of signals of the chip under test output data comparator in the framework processor;
The control sequence pattern generator produces pattern values and writes in the figure truth table, thereby described data comparator according to the pattern values in the figure truth table will hang down datum relatively chip under test output data relatively back output X result to the data failure storer, with height with reference to level ratio than the data of chip under test output relatively back output Y result to the data failure storer;
By test procedure data selector is set, each bit of setting digital collection device links with the chip testing passage;
Again the X result in the data failure storer, Y end value are generated the collection enable signal of digital collection device by the exclusive or logic gate in the digital collection device, be used for controlling H result or L end value are imported in the storer of digital collection device between the memory block with this chip testing passage correspondence;
By background process the data in the digital collection device storer are imported in the array variable of appointment at last.
2. require the 1 described method of utilizing semi-conductor test instrument to read chip information according to going there, it is characterized in that, the reference high level that the datum generator in channel electron loop is set equals reference low level.
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| US20030059967A1 (en) * | 2001-09-25 | 2003-03-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device, test method for semiconductor device, and tester for semiconductor device |
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Application publication date: 20110511 |