CN102044211B - Scanning display device control circuit - Google Patents

Abstract

The invention provides a control circuit of a scanning display device, which is suitable for receiving continuous picture data and driving a light emitting diode display device according to the continuous picture data. The scanning display device control circuit comprises a ping-pong storage area, a data storage controller, a line scanning controller, a buffer module and a scattered pulse width modulation signal generating device. The control circuit of the scanning display device can repeatedly and circularly utilize the picture data to avoid the repeated transmission of a large amount of data. Therefore, the bandwidth required by the input data can be greatly reduced. In addition, the scattered pulse width modulation signal generating device can scatter the pulse width modulation signal with a longer period into a plurality of scattered pulse width modulation signals with a shorter period, so that the refreshing frequency can be effectively improved under the condition of not changing the bandwidth of input data.

Description

Scanning display device control circuit

technical field

The present invention relates to a circuit, in particular to a control circuit for a scanning display device. the

Background technique

In recent years, the manufacturing cost of light-emitting diodes (Light-Emitting Diode, LED) has dropped significantly. Therefore, LED displays have been widely used in various occasions, such as gymnasiums, outdoor billboards, and the like. the

Light-emitting diode display devices usually use thousands of light-emitting diodes as display pixels. Pixels showing different brightness respectively can form a picture, and multiple pictures can be presented sequentially in time to form a dynamic image. the

These pixels are respectively controlled via the controller. According to the input data, the controller sends on or off signals to the LED driver to control the brightness of the pixels. the

Generally speaking, the dynamic image switches about 60 frames per second, that is to say, the switching frequency (Frame Rate) of the input screen is 60Hz. Because the period of switching images is very short, when the human eye watches the dynamic image, it will feel that the dynamic image is continuous due to the phenomenon of persistence of vision. the

Also, the time required to display one full screen is called refresh time. The reciprocal of the refresh time is the refresh rate. When the refresh rate is higher, the light-emitting diode display device is less prone to flickering (for example, when photographing with a high-speed shutter of photographic equipment). the

On the other hand, the number of LED driving circuits required by a general LED display device is very large. In order to save the number of LED driving circuits, the LED display device can adopt a scan-type controller. In a scanning controller, a plurality of LEDs can be driven at different time points through a switching device. Therefore, the same LED driving circuit can drive multiple LEDs. the

Although the scan-type controller can save the number of LED driving circuits, the amount of data to be processed by the same LED driving circuit is doubled. That is to say, the LED driving circuit needs a larger transmission bandwidth. In addition, because the time required to display a complete picture becomes longer, the refresh rate (refresh rate) will also decrease. the

Contents of the invention

In view of the above problems, the present invention proposes a scanning display device control circuit for increasing the refresh rate of the scanning display device and reducing the transmission bandwidth of the LED driving circuit. the

The scanning display device control circuit proposed by the present invention is suitable for receiving a plurality of continuous picture data and driving a light emitting diode display device accordingly. The scanning type display device control circuit includes a ping-pong storage area (Ping-pong buffer), a data storage controller, a row scanning controller, a register module and a discrete pulse width modulation signal generating device. the

The ping-pong storage area includes a first storage area and a second storage area. The data storage controller sequentially accepts the picture data and alternately stores the picture data in the first storage area or the second storage area. The line scan controller is logically connected to the ping-pong storage area, and the line scan controller is used to alternately capture one line of data in the frame data from the first storage area or the second storage area. The buffer module is logically connected to the row scan controller for temporarily storing row data. the

The Scrambled Pulse Width Modulation (Scrambled Pulse Width Modulation) generating device is logically connected to the register module and the row scan controller. The discrete pulse width modulation signal generating device acquires row data and generates a discrete pulse width modulation signal according to the row data to drive the light emitting diode display device. the

In one embodiment of the present invention, the row data is M bits, after a line feed period, the device for generating pulse width modulation signals of the scattered type generates and captures another row of data and generates another scattered pulse width modulation signal according to the other row of data. A pulse width modulated signal, wherein the line feed period is 2 ^N operation periods, and N is less than M.

In another embodiment of the present invention, the line data is M bits. After a line feed period, the dispersive pulse width modulation signal generating device generates and captures another line of data and generates another scatter signal according to another line of data. Type pulse width modulation signal, wherein the line feed cycle is 2 ^N operation cycles plus a blanking cycle, and N is less than M.

The present invention also proposes a control circuit for a scanning display device, which is suitable for receiving a plurality of consecutive picture data and driving a light emitting diode display device accordingly. The scanning type display device control circuit includes a ping-pong storage area (Ping-pong buffer), a data storage controller, a row scanning controller and a pulse width modulation signal generating device. Wherein, after the line scan controller passes through a cycle length corresponding to the line data and a blanking time, the line scan controller captures another line of data of the picture data, and sends the other line of data to the pulse width modulation signal to generate device. the

The control circuit of the scanning display device of the present invention can use the picture data repeatedly and cyclically, so as to avoid a large amount of repeated transmission. Therefore, the bandwidth required for inputting data can be greatly reduced. In addition, the discrete PWM signal generating device can disperse a pulse width modulation signal with a long period into multiple discrete pulse width modulation signals with a short period, so it can be used without changing the frequency of the input data. In the case of a wide range, the refresh rate can be effectively increased. the

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention. the

Description of drawings

Fig. 1 is the structural diagram of scanning type (scan-type) LED display device of the present invention;

Fig. 2 is the system block diagram of the first embodiment of the present invention;

3A and 3B are timing diagrams of driving signals of the present invention;

FIG. 4A is a system block diagram of the first embodiment of the discrete pulse width modulation signal of the present invention;

FIG. 4B is a system block diagram of a second embodiment of the discrete pulse width modulation signal of the present invention;

FIG. 5A, FIG. 5B and FIG. 5C are schematic diagrams of the operation mode of FIG. 2 of the present invention;

FIG. 6 is a system block diagram of the second embodiment of the present invention. the

Among them, reference signs

10 Scanning display device control circuit

11 Ping-pong storage area

12 The first storage area

14 Second storage area

20 data storage controller

30 line scan controller

41 first counter

42 second counter

43 random number generator

50 register module

51 first sub-register

52 second sub-register

53 main buffer

60 discrete pulse width modulation signal generator

60' Pulse Width Modulation Signal Generator

61 first comparator

62 second comparator

90 LED display device

92 switcher

Detailed ways

The detailed features and advantages of the present invention are described in detail below in the embodiments, the content of which is sufficient to enable any person familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the patent scope of the application and the accompanying drawings , anyone skilled in the relevant art can easily understand the related objects and advantages of the present invention. The following examples further illustrate the concept of the present invention in detail, but do not limit the scope of the present invention in any way. the

Please refer to FIG. 1 , which is a structural diagram of an LED display device 90 . The LED display device 90 is a one-line scanning display screen. The LED display device 90 needs to use a switcher 92 together. For example, the LEDs on the LED display device 90 can be divided into a first row of LEDs, a second row of LEDs, a third row of LEDs, . . . and an eighth row of LEDs. The switcher 92 circularly turns on the LEDs in the first row, the LEDs in the second row, the LEDs in the third row, . . . and the LEDs in the eighth row sequentially. the

When the switcher 92 turns on the first row of LEDs, the scanning display device control circuit 10 will output a driving signal corresponding to the first row of LEDs. The same goes for the other rows of LEDs. the

Please refer to FIG. 2 , which is a system block diagram of the first embodiment of the present invention. The scanning display device control circuit 10 includes a ping-pong storage area 11 , a data storage controller 20 , a row scanning controller 30 , a register module 50 and a discrete PWM signal generating device 60 . the

The ping-pong storage area 11 includes a first storage area 12 and a second storage area 14 . The ping-pong storage area 11 can write and read data without interruption. The data storage controller 20 is used to sequentially receive picture data, and the data storage controller 20 stores these data alternately in the first storage area 12 or the second storage area 14. the

The row scan controller 30 is logically connected to the ping-pong storage area 11 for alternately capturing one row of frame data from the first storage area 12 or the second storage area 14 . the

The register module 50 is logically connected to the row scan controller 30 for temporarily storing the row data in the frame data in the first storage area 12 or the second storage area 14 . the

The discrete pulse width modulation signal generating device 60 is logically connected to the row scan controller 30 and the register module 50 . The discrete PWM signal generating device 60 is used for capturing row data and generating a discrete PWM signal according to the row data. the

The detailed operating method of the present invention is hereby described as follows. the

In this embodiment, the frame data is a grayscale frame data. That is to say, the information stored in the picture data represents the grayscale brightness of the picture. The numerical value of grayscale brightness can represent the lightness and darkness of any color. The larger the value of the grayscale brightness, the brighter the color. Conversely, the smaller the value of the grayscale brightness, the darker the color. Take sixteen-bit black-and-white grayscale brightness as an example. Gray scale brightness "65535" represents white, and gray scale brightness "0" represents black. the

First, the data storage controller 20 stores the first frame data (frame 1) of the first frame period (frame period) in the first storage area 12, and stores the second frame data (frame 2) of the second frame period in the The third frame data (frame 3) of the second storage area 14, the third frame time is stored in the first storage area 12, and the fourth frame data (frame 4) of the fourth frame time is stored in the second storage area 14. According to this sequence, the picture data is continuously stored in the first storage area 12 or the second storage area 14 . the

At the second frame time, besides the second frame data is written into the second storage area 14 , and at the same time the first frame data can also be read from the first storage area 12 . At the third frame time, besides the third frame data is written into the first storage area 12 , and the second frame data can also be read from the second storage area 14 at the same time. Because the steps of writing and reading are alternately performed continuously, the ping-pong storage area 11 does not generate a pause interval between reading and writing. the

During the same frame time, the row scan controller 30 sequentially and cyclically captures one row of frame data, and sends the captured row data to the register module 50. Since each frame data is processed in the same manner, only the first frame data is used for illustration here. For example, the first frame includes eight rows of data (the first row of data, the second row of data, the third row of data . . . and the eighth row of data). The row scan controller 30 retrieves the row data sequentially as the first row data, the second row data, the third row data... and the eighth row data. After the eighth row of data is captured, the row scan controller 30 will immediately recapture the first row of data. In such a sequential cycle, the line scan controller 30 continuously captures and transmits each line data in a frame data to the register module 50 . the

The register module 50 includes a first sub-register 51 , a second sub-register 52 and a main register 53 . The first sub-register 51 and the second sub-register 52 are logically connected to the row scan controller 30 for temporarily storing a row of data in the first storage area 12 or the second storage area 14 . The main register 53 is used for retrieving row data of the first sub-register 51 or the second sub-register 52 . the

The scrambled pulse width modulation (Scrambled Pulse Width Modulation, SPWM) signal generating device 60 can scatter a pulse width modulation (Pulse Width Modulation, PWM) signal with a longer period into multiple scrambled pulse width modulation (PWM) signals with a shorter period. type pulse width modulation signal. Taking 16-bit black-and-white gray scale brightness as an example, the length of data stored in each line of data is 16 bits. The cycle of the pulse width modulation signal corresponding to the row data is 65,536 (2 ¹⁶ ) operating cycles. The discrete PWM signal generating device 60 can disperse the PWM signal with a length of 65,536 operating cycles into a plurality (for example, sixty-four) of discrete PWM signals. That is to say, the length of each discrete PWM signal is 1,024 (2 ¹⁰ ) operation periods.

Here, the operating cycle can be defined as the time between a rising edge of a frequency signal and another rising edge adjacent to it, or as the time between a falling edge of a frequency signal and an adjacent rising edge. The time between another falling edge. the

The discrete PWM signal generating device 60 transmits the discrete PWM signal to the LED display device 90 . The row scan controller 30 performs a row scan operation at intervals of a row-feed cycle. For example, the row scan controller 30 captures the first row of data, and sends the first row of data to the discrete pulse width modulation signal generating device 60 to output the driving signal. After a line feed cycle (1,024 operation cycles), the row scan controller 30 captures the second sub-row data, and sends the second row data to the discrete pulse width modulation signal generating device 60 to output a driving signal. This step is repeated continuously, and the row scan controller 30 sequentially captures the data of the first row, the data of the second row...the data of the eighth row. After capturing the eighth row of data, the row scan controller 30 recaptures the first row of data. the

Please refer to Figure 3A. FIG. 3A is a timing diagram of driving signals. In the first line feed cycle (1024 operation cycles), the first line of data is sent to the discrete PWM signal generating device 60 to generate the discrete PWM signal. In the second line feed cycle, that is, in the next 1024 operation cycles, the second line of data will be sent to the discrete PWM signal generating device 60 to generate the discrete PWM signal. Repeating the above actions, the first sub-row data, the second sub-row data ... and the eighth sub-row data are sequentially sent to the discrete pulse width modulation signal generating device 60 to generate the discrete pulse width modulation signal . the

After eight line feed cycles, a picture data can be completely displayed. The total time of eight sub-signal periods is called a sub-period. In this embodiment, the length of the first sub-cycle is 8,192 (8×1,024) operation cycles. Compared with the general method, it takes 524,288 (8×65,536) operation cycles to display a complete picture. The time required for the control circuit 10 of the scanning display device of the present invention to display a complete picture is only one sixty-fourth of that of the general method, that is to say, the refresh frequency of the control circuit 10 of the scanning display device is six times that of the general method. Fourteen times. the

In the line scan LED display device 90 , in order to prevent ghosting, after transmitting the driving signal corresponding to one line of data, it may pause for a period of time, and then transmit the driving signal corresponding to another line of data. The time of this pause is called the blanking period. the

Please refer to Figure 3B. FIG. 3B is a timing diagram of driving signals. During the first 1024 operation cycles, the first row of data will be sent to the discrete PWM signal generating device 60 to generate the discrete PWM signal. Afterwards, at the 1025th cycle, the scanning display device control circuit 10 temporarily stops generating the driving signal. The length of the 1025th cycle is the length of the vanishing cycle. the

In an embodiment of the present invention, the row scan controller 30 has an input port for an external frequency signal. The external frequency signal input port is used for inputting an external frequency signal. The external frequency signal is composed of a plurality of sub-frequency signals, and the period of each sub-frequency signal corresponds to an operation period. That is to say, the length of the blanking period can be changed by changing the length of the external frequency signal. the

The discrete PWM signal generating device 60 can be realized in at least two or more implementation manners, which are described below. the

FIG. 4A is a system block diagram of a first implementation of the discrete PWM signal generating device 60 . The discrete PWM signal generator 60 includes a first counter 41 , a first comparator 61 , a second counter 42 and a second comparator 62 . the

The first counter 41 is used for outputting a first value signal. The first value signal is preferably an increment signal. The first comparator 61 has a first input terminal and a second input terminal. The first input terminal is used to input the first N most significant bits (Most Significant Bits, MSB) of the row data, and the second input terminal is used to input the first numerical signal. The first comparator outputs the main signal according to the first input terminal and the second input terminal. For example, when the value at the first input terminal is greater than the value at the second input terminal, the first comparator 61 outputs a “logic 1” signal; when the value at the first input terminal is equal to or less than the value at the second input terminal, the first comparator 61 outputs a "logic 0" signal. The light-emitting diode emits light only when a “logic 1” signal is sent to the light-emitting diode, that is, the value of the first N most significant bits of the row data is greater than the value of the first counter 41 . the

The second counter 42 is used for outputting a second value signal. The second comparator 62 has a third input terminal and a fourth input terminal. The third input terminal is used to input the last L least significant bits (LeastSignificant Bits, LSB) of the row data, and the fourth input terminal is used to input the second numerical signal. The second comparator 62 outputs a compensation signal according to the third input terminal and the fourth input terminal. For example, when the value at the third input terminal is greater than the value at the fourth input terminal, the second comparator 62 outputs a “logic 1” signal, and when the value at the third input terminal is smaller than the value at the fourth input terminal, the second comparator 62 outputs "Logic 0" signal. Wherein, the second value signal changes its output value every other sub-period. Therefore, at the same time, it is possible to record the output period breakpoints of discrete PWM signals in each row, and when the same row is scanned next time, the interrupted pulse width modulation signal output period breakpoints from the last discrete pulse width modulation signal continue to the discrete PWM signal output cycle breakpoints. Change signal output. In this way, the pulse width modulation output cycle can be completely completed without being affected by the interruption of the line scan. The second counter 42 can adopt a sequential counting method. Uniform skip counting can also be used. The uniform skip counting method can make the output of the scattered pulse width modulation signal more uniform after breaking up. the

The discrete PWM signal output by the discrete PWM signal generator 60 includes the output main signal of the first comparator 61 and the output compensation signal value of the second comparator 62 . That is to say, the discrete PWM signal can be divided into the first segment and the second segment in time, the signal of the first segment is the main signal, and the signal of the second segment is the compensation signal. the

，其它五十九个打散式脉冲宽度调变讯号的工作周期(Duty Cycle)为 

。为了减少其低频 成分及视觉上的闪烁，第二计数器42可采用均匀跳跃计数方式，以使上述五个工作周期(Duty Cycle)为 

的打散式脉冲宽度调变讯号均匀分布于64个打散式脉冲宽度调变讯号中。此实施方法可参考中国台湾专利申请号200729133。  Take the sixteen-bit row data as an example, assuming that the decimal value of this row of data is "6405". The decimal value represented by the first ten most significant digits of this row of data is "100", and the decimal value represented by the last six least significant digits of the row of data is "5". The row of data will be broken into sixty-four scattered PWM signals, and the length of each scattered PWM signal is 1024 operation cycles. Since the decimal value represented by the last six least significant bits of the row data is "5", among the sixty-four scattered PWM signals, the compensation of five scattered PWM signals The signal is "1", and the compensation signals of the other fifty-nine discrete PWM signals are "0". That is to say, the duty cycle (Duty Cycle) of five discrete PWM signals is

, the duty cycle (Duty Cycle) of the other fifty-nine scattered pulse width modulation signals is

. In order to reduce its low-frequency components and visual flicker, the second counter 42 can adopt a uniform skip counting mode, so that the above-mentioned five duty cycles (Duty Cycle) are

The discrete pulse width modulation signals are evenly distributed among the 64 discrete pulse width modulation signals. For this implementation method, reference may be made to Taiwan Patent Application No. 200729133.

FIG. 4B is a system block diagram of a second implementation of the discrete PWM signal generating device 60 . The discrete PWM signal generator 60 includes a random number generator 43 and a first comparator 61 . The random number generator 43 generates a random number value signal. The first comparator 61 has a first input terminal and a second input terminal. The first input terminal is used for inputting row data, and the second input terminal is used for inputting a random number value signal. When the value at the first input terminal is greater than the value at the second input terminal, the first comparator 61 outputs a first signal, and when the value at the first input terminal is equal to or smaller than the value at the second input terminal, the first comparator outputs a second signal. For example, the first signal is a "logic 1" signal, and the second signal is a "logic 0" signal. The light emitting diode will emit light only when the "logic 1" signal is sent to the light emitting diode, that is, the value of the row data is greater than the random number value signal generated by the random number generator 43 . the

In the above two implementations, the line feed periods are equal. The action of changing the line can be executed by the line scan controller 30 . the

To further illustrate the process of generating the PWM signal, please refer to FIG. 5A , FIG. 5B and FIG. 5C . FIG. 5A , FIG. 5B and FIG. 5C are schematic diagrams of the operation mode according to FIG. 2 . the

Please refer to Figure 5A. The first sub-row data is stored in the main register 53 , and the second sub-row data is stored in the first sub-register 51 . At this time, the discrete PWM signal generating device 60 retrieves the value of the main register 53 and generates a discrete PWM signal. the

Please refer to FIG. 5B. After a line feed cycle, the second row of data in the first sub-buffer 51 in FIG. 5A is sent to the main buffer 53, and the row scan controller 30 sends the third row of data to the first Sub-buffer 51. the

After the control circuit 10 of the scanning display device sequentially outputs the discrete pulse width modulation signals of the first row of data, the second row of data ... and the eighth row of data, in the next time period, the scanning display device controls The circuit 10 re-outputs the discrete PWM signal of the first row of data. In this way, the row data of the same frame data is repeatedly intercepted, and the scanning display device control circuit 10 can avoid a large amount of repetitive transmission of frame data. Therefore, the bandwidth required for inputting data can be greatly reduced. the

In addition, the line scan controller 30 has a command input port (not shown in the figure), when the command input port (not shown in the figure) receives a screen switching command, the data retrieved by the main register 53 is from the first sub-frame The buffer 51 changes from the second sub-buffer 52 or from the second sub-buffer 52 to the first sub-buffer 51 . Please refer to Figure 5C. One sub-row data in the second sub-register 52 will be transferred to the main register 53, that is to say, the operation mode in FIG. 5A is changed to the operation mode in FIG. 5C. the

With the structure of two registers (the first sub-register 51 and the second sub-register 52 ) and the mechanism of storing data in advance, the scan-type display device control circuit 10 can continuously transmit the driving signals corresponding to the frame data without interruption. the

In an embodiment of the present invention, if there are multiple values in a row of data, the driving signals corresponding to the multiple values can be output in parallel. The scanning display device control circuit 10 includes a plurality of register modules 50 and a plurality of discrete PWM signal generating devices 60 . the

Please refer to FIG. 6 , which is a system block diagram of the second embodiment of the present invention. The scan type display device control circuit 10 includes a ping-pong storage area 11, a data storage controller 20, a line scan controller 30, a register module 50 and a pulse width modulation signal generating device 60'. The pulse width modulation signal generating device 60' can be a general pulse width modulation signal generating device, or a discrete pulse width modulation signal generating device 60. The operation of the scanning display device control circuit 10 is similar to that of the first embodiment, so it will not be repeated here. the

Based on the above, the control circuit of the scanning display device of the present invention can use the image data repeatedly and cyclically, so as to avoid a large amount of repeated transmission. Therefore, the bandwidth required for inputting data can be greatly reduced. In addition, the discrete PWM signal generating device can disperse a pulse width modulation signal with a long period into multiple discrete pulse width modulation signals with a short period, so it can be used without changing the frequency of the input data. In the case of a wide range, the refresh rate can be effectively increased. the

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention. the

Claims (15)

1. a scanning type display device control circuit, be suitable for and accept continuous a plurality of picture datas and drive according to this a light emitting display device, it is characterized in that, this scanning type display device control circuit comprises:

One table tennis storage area, this table tennis storage area comprises one first storage area and one second storage area;

One data storing controller is sequentially accepted those picture datas and alternately stores those picture datas in this first storage area or this second storage area;

Delegation's scanning monitor, logic are connected in this table tennis storage area, capture a plurality of row data among those picture datas in order to this first storage area or this second storage area certainly;

One buffer module, logic are connected in this line scanning controller, in order to temporary those row data; And

One breaks up formula pulse width modulation signal generation device, logic is connected in this buffer module and this line scanning controller, and this is broken up formula pulse width modulation signal generation device and captures the data line in those row data and break up formula pulse width modulation signal to drive this light emitting display device according to the row data generation one of acquisition.

2. scanning type display device control circuit as claimed in claim 1, it is characterized in that, the row data of acquisition are M position, when through one the line feed all after dates, this is broken up the formula pulse width modulation signal generation device another data line of acquisition and produces another according to another data line and breaks up formula pulse width modulation signal, should be wherein 2 in the line feed cycle ^NIndividual operation period, and N is less than M.

3. scanning type display device control circuit as claimed in claim 2, is characterized in that, this is broken up formula pulse width modulation signal and comprises main signal and a compensating signature, and this is broken up formula pulse width modulation signal generation device and comprises:

One first counter is in order to export one first numerical value signal;

One first comparer, have a first input end and one second input end, this first input end is in order to a front N highest significant position of the row data of input acquisition, this second input end is in order to input this first numerical value signal, and this first comparer is according to a front N highest significant position of the row data of the acquisition of this first input end input and this this main signal of the first numerical value signal output of this second input end input;

One second counter, in order to export a second value signal, this second value signal just can change its output numerical value every a subcycle; And

One second comparer, have one the 3rd input end and a four-input terminal, the 3rd input end is in order to a back L least significant bit (LSB) of the row data of input acquisition, this four-input terminal is in order to input this second value signal, and this second comparer is exported this compensating signature according to a back L least significant bit (LSB) of the row data of the acquisition of the 3rd input end input and this second value signal of this four-input terminal input.

4. scanning type display device control circuit as claimed in claim 2, is characterized in that, this is broken up formula pulse width modulation signal generation device and comprises:

One tandom number generator is in order to export a random number numerical value signal; And

One first comparer, have a first input end and one second input end, this first input end is in order to the row data of input acquisition, this second input end is in order to input this random number numerical value signal, and this first comparer is according to the row data of the acquisition of this first input end input and this random number numerical value signal output one main signal of this second input end input.

5. scanning type display device control circuit as claimed in claim 1, it is characterized in that, the row data of acquisition are M position, when through one the line feed all after dates, this is broken up the formula pulse width modulation signal generation device another data line of acquisition and produces another according to another data line and breaks up formula pulse width modulation signal, should be wherein 2 in the line feed cycle ^NIndividual operation period adds one and disappears the shadow cycle, and N is less than M.

6. scanning type display device control circuit as claimed in claim 5, it is characterized in that, this line scanning controller has a foreign frequency signal input end mouth, and in order to input a foreign frequency signal, the cycle of this foreign frequency signal is in order to control this operation period and the length in this shadow cycle that disappears.

7. scanning type display device control circuit as claimed in claim 1, is characterized in that, this buffer module comprises:

One first sub-buffer, logic connect this line scanning controller, in order to the data line of temporary this first storage area;

One second sub-buffer, logic connect this line scanning controller, in order to the data line of temporary this second storage area; And

One master cache device, in order to capture the row data of this first sub-buffer or this second sub-buffer, this master cache device logic is connected in this and breaks up formula pulse width modulation signal generation device.

8. scanning type display device control circuit as claimed in claim 7, it is characterized in that, this line scanning controller has an instruction input port, when this instruction input port receives a Picture switch instruction, the data of this master cache device acquisition for become from this first sub-buffer capture from this second sub-buffer or become from this second sub-buffer and capture from this first sub-buffer.

9. a scanning type display device control circuit, be suitable for and accept continuous a plurality of picture datas and drive according to this a light emitting display device, it is characterized in that, this scanning type display device control circuit comprises:

One table tennis storage area, this table tennis storage area comprises one first storage area and one second storage area;

One data storing controller is sequentially accepted those picture datas and alternately stores those picture datas in this first storage area or this second storage area;

Delegation's scanning monitor, logic are connected in this table tennis storage area, in order to a plurality of row data among this first storage area or this second storage area capture those picture datas alternately;

One buffer module, logic are connected in this line scanning controller, in order to temporary those row data; And

One pulse width modulation signal generation device, logic is connected in this buffer module and this line scanning controller, and this pulse width modulation signal generation device captures the data line in those row data and produces a pulse width modulation signal according to the row data that capture;

Wherein the row data of acquisition are M position, and when through all after dates of line feed, this pulse width modulation signal generation device produces the another data line of acquisition and produces another pulse width modulation signal according to another data line;

Should it be wherein 2 in the line feed cycle ^NIndividual operation period adds one and disappears the shadow cycle, and N is less than M.

10. scanning type display device control circuit as claimed in claim 9, is characterized in that, the length in this shadow cycle that disappears is controlled by a foreign frequency signal.

11. scanning type display device control circuit as claimed in claim 9, it is characterized in that, this pulse width modulation signal generation device is to break up formula pulse width modulation signal generation device, and this is broken up formula pulse width modulation signal generation device and breaks up formula pulse width modulation signal in order to produce one.

12. scanning type display device control circuit as claimed in claim 11 is characterized in that, this is broken up formula pulse width modulation signal and comprises main signal and a compensating signature, and this is broken up formula pulse width modulation signal generation device and comprises:

One first counter is in order to export one first numerical value signal;

One first comparer, have a first input end and one second input end, this first input end is in order to a front N highest significant position of the row data of input acquisition, this second input end is in order to input this first numerical value signal, and this first comparer is according to a front N highest significant position of the row data of the acquisition of this first input end input and this this main signal of the first numerical value signal output of this second input end input;

One second counter is in order to export a second value signal; And

One second comparer, have one the 3rd input end and a four-input terminal, the 3rd input end is in order to a back L least significant bit (LSB) of the row data of input acquisition, this four-input terminal is in order to input this second value signal, and this second comparer is exported this compensating signature according to a back L least significant bit (LSB) of the row data of the acquisition of the 3rd input end input and this second value signal of this four-input terminal input.

13. scanning type display device control circuit as claimed in claim 11 is characterized in that, this is broken up formula pulse width modulation signal generation device and comprises:

One tandom number generator is in order to export a random number numerical value signal; And

One first comparer, have a first input end and one second input end, this first input end is in order to the row data of input acquisition, this second input end is in order to input this random number numerical value signal, and this first comparer is according to the row data of the acquisition of this first input end input and this random number numerical value signal output one main signal of this second input end input.

14. scanning type display device control circuit as claimed in claim 11 is characterized in that, this buffer module comprises:

One first sub-buffer, logic connect this line scanning controller, in order to the data line of temporary this first storage area;

One second sub-buffer, logic connect this line scanning controller, in order to the data line of temporary this second storage area; And

One master cache device, in order to capture the row data of this first sub-buffer or this second sub-buffer, this master cache device logic is connected in this and breaks up formula pulse width modulation signal generation device.

15. scanning type display device control circuit as claimed in claim 14, it is characterized in that, this line scanning controller has an instruction input port, when this instruction input port receives a Picture switch instruction, the data of this master cache device acquisition for become from this first sub-buffer capture from this second sub-buffer or become from this second sub-buffer and capture from this first sub-buffer.

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