CN102034762A - Method for manufacturing NOR flash memory - Google Patents
Method for manufacturing NOR flash memory Download PDFInfo
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- CN102034762A CN102034762A CN200910178434XA CN200910178434A CN102034762A CN 102034762 A CN102034762 A CN 102034762A CN 200910178434X A CN200910178434X A CN 200910178434XA CN 200910178434 A CN200910178434 A CN 200910178434A CN 102034762 A CN102034762 A CN 102034762A
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- ion implantation
- semiconductor substrate
- implantation technology
- inclination angle
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Abstract
本发明是揭露一种NOR型闪存的制作方法，利用两次的倾角离子注入工艺以形成倾角注入源极区，通过此种注入步骤来改善源极区的注入分布，以降低NOR型闪存中漏极区与源极区之间短沟道效应发生的机率。
The invention discloses a method for manufacturing a NOR flash memory, which uses two tilted ion implantation processes to form a tilted implanted source region. The implantation steps are used to improve the implantation distribution of the source region to reduce the probability of the short channel effect between the drain region and the source region in the NOR flash memory.
Description
Technical field
The invention relates to a kind of manufacture method of NOR type flash memory, more particularly about a kind of manufacture method that improves the NOR type flash memory of source electrode ion implantation technology.
Background technology
Along with the progress of semiconductor process techniques, metal-oxide semiconductor (MOS) (Metal-Oxide-Semiconductor, dwindle gradually, thereby significantly reduce the assembly integrated level (Integration) of manufacturing cost and raising integrated circuit by size MOS).Yet, along with dwindling of metal-oxide semiconductor (MOS) size, its short-channel effect of deriving (Short Channel Effect SCE) but produces many problems, as: (roll-off) falls in the skew of critical voltage, the commentaries on classics of critical voltage.Therefore, design one is applicable to that the structure of utmost point short channel assembly is very important.
Fig. 1 is the vertical view of NOR type flash memory array.Fig. 1 is the NOR type flash memory array of display part, has a plurality of grid structures 102 as mnemon in this memory array, and those grid structures 102 are connected into the character line of vertical arrangement by deposition control grid 102d thereon.Each grid structure 102 is adjacent a drain region 104 and a gate regions 106.As shown in FIG., have a contact hole 110 on this drain region 104 that two grid structures are 102, its with so that those grid structures 102 can be electrically connected with doing perpendicular to the bit line (not shown) of character line.In this NOR type flash memory array, have perpendicular to character line, and the fleet plough groove isolation structure 112 that two adjacent grid structures 102 are separated (Shallow Trench Isolation, STI).
Then seeing also Fig. 2, is the transverse cross-sectional view of known NOR type flash memory, and this horizontal section is corresponding to BB ' the horizontal section line among Fig. 1.By among the figure as can be known, have a grid structure 102 on semi-conductive substrate 100, this grid structure 102 comprises: a tunnel oxidation layer 102a (tunnel oxide layer), a floating boom 102b (floating gate), a dielectric layer 102c, a control gate 102d (control gate) and be positioned at the dioxide layer wall 202 of these grid structure 102 both sides.Have the shallow doped drain region 104a and the dark doped drain region 104b that form drain region 104 precipitous knots in the Semiconductor substrate 100 of these grid structure 102 1 sides, opposite side then has and utilizes formed one first source area 106a of known source electrode ion implantation technology and one second source area 106b.Along with the micro of memory size, the formed first source area 106a of known source electrode ion implantation technology is owing to protrude, and increased and this shallow doped drain region 104a between the probability that takes place of short-channel effect.
Then seeing also Fig. 3, is the longitudinal stereoscopic profile of known NOR type flash memory, and this longitudinal profile is corresponding to AA ' the longitudinal profile line among Fig. 1, and the shown zone of Fig. 3 is the zone 130 that corresponds among Fig. 1.It among the figure the known source electrode ion implantation technology that self-aligned is carried out in expression, before carrying out known source electrode ion implantation technology prior to this shallow doped drain region 104a with should be dark doped drain region 104b top cover with a mask 204, then carry out the source electrode ion implantation technology 206a first time at tool inclination angle, carry out vertical second time of source electrode ion implantation technology 208, the last ion implantation technology of the source electrode for the third time 206b that carries out the tool inclination angle more again.Formed this first source area of known source electrode ion implantation technology 106a and this shallow doped drain region 104a be quite near (see figure 2), so when the assembly micro with easier generation short-channel effect.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of NOR type flash memory, and the injection that improves source area by improvement source electrode ion implantation technology distributes, and can effectively reduce the probability that short-channel effect takes place in the NOR type flash memory under the micro size.
For reaching above-mentioned purpose, the present invention provides a kind of manufacture method of NOR type flash memory, and its step comprises: form many fleet plough groove isolation structures in semi-conductive substrate, the spacing between described these fleet plough groove isolation structures is about 50nm～150nm; Form a plurality of grid structures on described Semiconductor substrate, described these grid structures are to connect into the vertical bar shape with a control gate, and the orientation of described control gate on described Semiconductor substrate is perpendicular to described these fleet plough groove isolation structures; Carry out a shallow doped-drain ion implantation technology, in the described Semiconductor substrate of described these grid structure one sides, form a plurality of shallow doped drain regions; Form an oxide layer wall respectively in the both sides of described these grid structures; Carry out a dark doped-drain ion implantation technology, form a plurality of dark doped drain regions in the described Semiconductor substrate of described these grid structure one sides, wherein said these shallow doped drain regions and described these dark doped drain regions are the described Semiconductor substrate that are arranged in described these grid structure the same sides; Carry out an etching technics, described these fleet plough groove isolation structure etchings that described these grid structure opposite sides do not had in the described Semiconductor substrate of drain region are removed to form a plurality of openings; And carry out the inclination angle ion implantation technology, be used in the described Semiconductor substrate that described these grid structure opposite sides do not have the drain region and form an inclination angle in the described Semiconductor substrate under described these openings inject source area.
According to the manufacture method of the described NOR type of embodiment of the invention flash memory, wherein said Semiconductor substrate is to be a P type semiconductor substrate.
Manufacture method according to the described NOR type of embodiment of the invention flash memory, wherein said inclination angle ion implantation technology comprises inclination angle ion implantation technology and the inclination angle ion implantation technology second time for the first time, and injects described Semiconductor substrate with the incidence angles of about 25 to 35 degree.
Manufacture method according to the described NOR type of embodiment of the invention flash memory, the wherein said first time inclination angle ion implantation technology and the described second time inclination angle ion implantation technology be to use N type ion (as: arsenic, phosphorus), energy is about 20KeV～60KeV, and implantation dosage is about 1 * 10
14Atom/cm
2To 1 * 10
15Atom/cm
2
In sum, the manufacture method of NOR type flash memory of the present invention, utilize twice inclination angle ion implantation technology to inject source area to form the inclination angle, the injection that improves source area by this kind implantation step distributes, allow between the drain region and source area in the NOR type flash memory, can not increase the probability that short-channel effect takes place because of spacing is too short.
Description of drawings
Fig. 1 is the vertical view of NOR type flash memory array;
Fig. 2 is the transverse cross-sectional view of known NOR type flash memory;
Fig. 3 is the longitudinal stereoscopic profile of known NOR type flash memory;
Fig. 4 to Fig. 9 when being presented at the different process step, the longitudinal stereoscopic profile of NOR type flash memory process flow of the present invention;
Figure 10 is the transverse cross-sectional view of NOR type flash memory of the present invention.
Drawing reference numeral
100 Semiconductor substrate
102 grid structures
The 102a tunnel oxidation layer
The 102b floating boom
The 102c dielectric layer
The 102d control gate
104 drain regions
The shallow doped drain region of 104a
The dark doped drain region of 104b
106 source areas
106a first source area
106b second source area
Source area is injected at the 106c inclination angle
110 contact holes
112 fleet plough groove isolation structures
130 zones
202 oxide layer walls
204 masks
206a is ion implantation technology for the first time
206b is ion implantation technology for the third time
208 ion implantation technologies for the second time
302 fleet plough groove isolation structures
304 oxide layer walls
306 masks
307 openings
308a is ion implantation technology for the first time
308b is ion implantation technology for the second time
AA ' longitudinal profile line
BB ' horizontal section line
The X spacing
The θ incidence angle
Embodiment
For fully understanding purpose of the present invention, feature and effect, now by following specific embodiment, and cooperate appended accompanying drawing, the present invention is described in detail, after being illustrated in.In these different accompanying drawings and embodiment, identical assembly will use identical drawing reference numeral.
The manufacture method of NOR type flash memory of the present invention mainly is the method for implanting in the improvement source electrode ion implantation technology.Embodiments of the invention are to be a kind of internal storage structure of N channel and source area and drain region with N type.Fig. 4 to Fig. 9 is when being presented at the different process step, the longitudinal stereoscopic profile of NOR type flash memory process flow of the present invention, and shown zone is zone 130 and AA ' the longitudinal profile line that corresponds among Fig. 1 among Fig. 4 to Fig. 9.
At first see also Fig. 4, implantation dosage about 1 * 10 in semi-conductive substrate 100
13Atom/cm
2Boron ion (Boron) to form the P type semiconductor substrate, then forming spacing X in this Semiconductor substrate 100 is many fleet plough groove isolation structures 302 of 50～150 (nm).In Fig. 4 to Figure 10, only show two fleet plough groove isolation structures 302.The material of this Semiconductor substrate 100 can be silicon (Si), SiGe (SiGe), silicon-on-insulator (Silicon On Insulator, SOI), silicon-on-insulator germanium (Silicon Germanium On Insulator, SGOI), cover on the insulating barrier germanium (Germanium On Insulator, GOI).In present embodiment, the material of this Semiconductor substrate 100 is to be silicon.
Then see also Fig. 5, on this Semiconductor substrate 100, utilize thermal oxidation process to make tunnel oxidation layer 102a (tunnel oxide layer), utilize low-pressure chemical vapor deposition method (Low Pressure Chemical Vapor Deposition, LPCVD) deposition floating boom 102b (floating gate) again.Utilize thermal oxidation process dielectric layer 102c (see figure 6) at last, form a kind of ONO (Oxide-Nitride-Oxide) structure.
Then see also Fig. 6, utilize photoresist and etching technics that each ONO structure is independent to orient after a while with the grid structure that forms.Then see also Fig. 7, utilize photoresist and etching technics to form a control gate 102d again, this control gate 102d is deposited on each ONO structure as shown in Figure 7 to form a plurality of grid structures 102, and this control gate 102d is long vertical bar shape and connects those grid structures 102.Wherein, the orientation of this control gate 102d on this Semiconductor substrate 100 is perpendicular to those fleet plough groove isolation structures 302.Each grid structure 102 comprises: a tunnel oxidation layer 102a (tunnel oxide layer), a floating boom 102b (floating gate), a dielectric layer 102c and a control gate 102d (control gate).Then utilize mask (figure does not show) that the part semiconductor substrate 100 of those grid structure 102 1 sides is covered, carry out a shallow doped-drain ion implantation technology in this Semiconductor substrate 100 of those grid structure 102 1 sides, to form a plurality of shallow doped drain region 104a.The ion that uses in this shallow doped-drain ion implantation technology is arsenic, and dosage is about 1 * 10
14Atom/cm
2～5 * 10
15Atom/cm
2, energy is about 10Kev～30Kev.
Then see also Fig. 8, deposit an oxide layer and form an oxide layer wall 304 respectively as resilient coating (those grid structures 102 are covered so can't all demonstrate by this oxide layer wall 304 among the figure) in the both sides of those grid structures 102 via etching.Utilize mask (figure does not show) that the part semiconductor substrate 100 of those grid structure 102 1 sides is covered again, carry out a dark doped-drain ion implantation technology to form a plurality of dark doped drain region 104b.Those shallow doped drain region 104a and those dark doped drain region 104b are this Semiconductor substrate 100 that is arranged in those grid structure 102 the same sides, and form drain region 104 as shown in Figure 1.The ion that uses in this dark doped-drain ion implantation technology is arsenic, and dosage is about 1 * 10
14Atom/cm
2～5 * 10
15Atom/cm
2, energy is about 40Kev～60Kev.
Then see also Fig. 9, utilize a mask 306 to cover a side (being a side at those shallow doped drain region 104a and those dark doped drain region 104b places) of those grid structures 102, carry out a self-aligned etching technics (Self-Align Etch), those fleet plough groove isolation structure 302 etchings that those grid structure 102 opposite sides do not had in this Semiconductor substrate 100 of drain region 104 are removed in order to form a plurality of openings 307.Then carry out the inclination angle ion implantation technology, this inclination angle ion implantation technology comprises inclination angle ion implantation technology 308a and the inclination angle ion implantation technology 308b second time for the first time, each incidence angle θ with about 25 to 35 degree of this two injection technology injects this Semiconductor substrate 100, be used in this Semiconductor substrate 100 that those grid structure 102 opposite sides do not have drain region 104, and form an inclination angle that links to each other in this Semiconductor substrate 100 under those openings 307 and inject source area 106c.Wherein this first time inclination angle ion implantation technology 308a and this second time inclination angle ion implantation technology 308b be to use ion implantation technology to be to use N type ion (as: arsenic, phosphorus), energy is 20KeV～60KeV, implantation dosage is about 1 * 10
14Atom/cm
2To 1 * 10
15Atom/cm
2It is the source area 106 that corresponds to Fig. 1 that source area 106c is injected at this inclination angle.
Then seeing also Figure 10, is the transverse cross-sectional view of NOR type flash memory of the present invention, and this section is corresponding to BB ' the horizontal section line among Fig. 1.Characteristics of the present invention are, compare with the known technology (see figure 2) of carrying out three source electrode ion implantation technologies, it is the source electrode ion implantation technology of zero degree that the present invention gives up the injection incidence angle, makes this inclination angle inject the first source area 106a that source area 106c is different from the approaching shallow doped drain region 104a of known technology.Therefore, the present invention can keep spacing far away with shallow doped drain region 104a compared to known technology, and then effectively reduces the probability that short-channel effect takes place.
In sum, the manufacture method of NOR type flash memory of the present invention, utilize twice inclination angle ion implantation technology to inject source area to form the inclination angle, the injection that improves source area by this kind implantation step distributes, allow between the drain region and source area in the NOR type flash memory, can not increase the probability that short-channel effect takes place because of spacing is too short.
The present invention discloses with preferred embodiment hereinbefore, yet it will be understood by those skilled in the art that this embodiment only is used for describing a part of structure of internal memory of the present invention, does not limit the scope of the invention and should not be read as.It should be noted,, all should be made as and be covered by in the category of the present invention such as with the variation and the displacement of this embodiment equivalence.Therefore, protection scope of the present invention is as the criterion when defining with claims.
Claims (5)
1. the manufacture method of a NOR type flash memory is characterized in that, described method comprises:
Form many fleet plough groove isolation structures in semi-conductive substrate, the spacing between described these fleet plough groove isolation structures is about 50nm～150nm;
Form a plurality of grid structures on described Semiconductor substrate, described these grid structures are to connect into the vertical bar shape with a control gate, and the orientation of described control gate on described Semiconductor substrate is perpendicular to described these fleet plough groove isolation structures;
Carry out a shallow doped-drain ion implantation technology, in the described Semiconductor substrate of described these grid structure one sides, form a plurality of shallow doped drain regions;
Form an oxide layer wall respectively in the both sides of described these grid structures;
Carry out a dark doped-drain ion implantation technology, form a plurality of dark doped drain regions in the described Semiconductor substrate of described these grid structure one sides, wherein said these shallow doped drain regions and described these dark doped drain regions are the described Semiconductor substrate that are arranged in described these grid structure the same sides;
Carry out an etching technics, described these fleet plough groove isolation structure etchings that described these grid structure opposite sides do not had in the described Semiconductor substrate of drain region are removed to form a plurality of openings; And
Carry out the inclination angle ion implantation technology, be used in the described Semiconductor substrate that described these grid structure opposite sides do not have the drain region and form an inclination angle in the described Semiconductor substrate under described these openings inject source area.
2. the manufacture method of NOR type flash memory as claimed in claim 1 is characterized in that, described Semiconductor substrate is to be a P type semiconductor substrate.
3. the manufacture method of NOR type flash memory as claimed in claim 1, it is characterized in that, described inclination angle ion implantation technology comprises inclination angle ion implantation technology and the inclination angle ion implantation technology second time for the first time, and injects described Semiconductor substrate with the incidence angles of about 25 to 35 degree.
4. the manufacture method of NOR type flash memory as claimed in claim 1 is characterized in that, the described first time inclination angle ion implantation technology and the described second time inclination angle ion implantation technology, be to use N type ion.
5. the manufacture method of NOR type flash memory as claimed in claim 4, it is characterized in that, the described first time inclination angle ion implantation technology and the described second time, the injection energy of the ion implantation technology that the inclination angle ion implantation technology is used was 20KeV～60KeV, and implantation dosage is about 1 * 10
14Atom/cm
2To 1 * 10
15Atom/cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910178434XA CN102034762A (en) | 2009-09-27 | 2009-09-27 | Method for manufacturing NOR flash memory |
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|---|---|---|---|
| CN200910178434XA CN102034762A (en) | 2009-09-27 | 2009-09-27 | Method for manufacturing NOR flash memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103177942A (en) * | 2013-03-01 | 2013-06-26 | 溧阳市虹翔机械制造有限公司 | Doping method for PMOS (p-channel metal oxide semiconductor) tube |
| CN111463120A (en) * | 2020-03-25 | 2020-07-28 | 派恩杰半导体（杭州）有限公司 | A kind of preparation method of channel inclined implantation of silicon carbide MOSFET |
-
2009
- 2009-09-27 CN CN200910178434XA patent/CN102034762A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103177942A (en) * | 2013-03-01 | 2013-06-26 | 溧阳市虹翔机械制造有限公司 | Doping method for PMOS (p-channel metal oxide semiconductor) tube |
| CN103177942B (en) * | 2013-03-01 | 2015-07-15 | 溧阳市虹翔机械制造有限公司 | Doping method for PMOS (p-channel metal oxide semiconductor) tube |
| CN111463120A (en) * | 2020-03-25 | 2020-07-28 | 派恩杰半导体（杭州）有限公司 | A kind of preparation method of channel inclined implantation of silicon carbide MOSFET |
| CN111463120B (en) * | 2020-03-25 | 2023-02-17 | 派恩杰半导体（杭州）有限公司 | Channel inclined injection preparation method of silicon carbide MOSFET |
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Application publication date: 20110427 |